ARM: BCM63XX: add support for BCM63138 SoC
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cover ARM: BCM63XX: add support for BCM63138 SoC
Hi all,
This patchset adds very minimal support for the BCM63138 SoC which is a xDSL SoC using a dual Cortex A9 CPU complex.
Future work will focus on:
- clock device/driver/providers
- SMP support (already working)
Resending with a wider audience this time, and hopefully at the right time.
Florian Fainelli (5):
ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
ARM: BCM63XX: add low-level UART debug support
ARM: BCM63XX: add BCM63138 minimal Device Tree
ARM: BCM63XX: add BCM963138DVT Reference platform DTS
MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs
.../devicetree/bindings/arm/bcm/bcm63138.txt | 9 ++ MAINTAINERS | 11 +++ arch/arm/Kconfig.debug | 18 +++- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/bcm63138.dtsi | 109 +++++++++++++++++++++ arch/arm/boot/dts/bcm63138dvt.dts | 18 ++++ arch/arm/include/debug/bcm63xxx.S | 33 +++++++ arch/arm/mach-bcm/Kconfig | 20 ++++ arch/arm/mach-bcm/Makefile | 1 + arch/arm/mach-bcm/bcm63xx.h | 29 ++++++ arch/arm/mach-bcm/board_bcm63xx.c | 94 ++++++++++++++++++ 11 files changed, 343 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm63138.txt create mode 100644 arch/arm/boot/dts/bcm63138.dtsi create mode 100644 arch/arm/boot/dts/bcm63138dvt.dts create mode 100644 arch/arm/include/debug/bcm63xxx.S create mode 100644 arch/arm/mach-bcm/bcm63xx.h create mode 100644 arch/arm/mach-bcm/board_bcm63xx.c
Signature · 1 line
1.9.1
PATCH RESEND 1/5 ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC.
Due to the two specific register address spaces located at 0x8000_0000 and 0xfffe_0000, we need to setup a specific iotable descriptor for those to be remapped at the expected virtual addresses.
Finally, the PL310 cache controller requires a bit of tweaking before handing its initialization over l2x0_of_init(), this is also taken care of to make sure that its size is properly configured.
--- .../devicetree/bindings/arm/bcm/bcm63138.txt | 9 +++ arch/arm/mach-bcm/Kconfig | 20 +++++ arch/arm/mach-bcm/Makefile | 1 + arch/arm/mach-bcm/bcm63xx.h | 29 +++++++ arch/arm/mach-bcm/board_bcm63xx.c | 94 ++++++++++++++++++++++ 5 files changed, 153 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm63138.txt create mode 100644 arch/arm/mach-bcm/bcm63xx.h create mode 100644 arch/arm/mach-bcm/board_bcm63xx.c
Documentation/devicetree/bindings/arm/bcm/bcm63138.txt new file +9 -0
@@ -0,0 +1,9 @@ +Broadcom BCM63138 DSL System-on-a-Chip device tree bindings +----------------------------------------------------------- + +Boards compatible with the BCM63138 DSL System-on-a-Chip should have the +following properties: + +Required root node property: + +compatible: should be "brcm,bcm63138"
arch/arm/mach-bcm/Kconfig +20 -0
@@ -69,6 +69,26 @@ config ARCH_BCM_5301X different SoC or with the older BCM47XX and BCM53XX based network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx +config ARCH_BCM_63XX + bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7 + depends on MMU + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select ARM_GLOBAL_TIMER + select CACHE_L2X0 + select COMMON_CLK + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_ARM_ARCH_TIMER + select HAVE_ARM_TWD if SMP + select HAVE_ARM_SCU if SMP + select HAVE_SMP + help + This enables support for systems based on Broadcom DSL SoCs. + It currently supports the 'BCM63XX' ARM-based family, which includes + the BCM63138 variant. + endmenu endif
arch/arm/mach-bcm/Makefile +1 -0
@@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o +obj-$(CONFIG_ARCH_BCM_63XX) := board_bcm63xx.o
arch/arm/mach-bcm/bcm63xx.h new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2014 Broadcom Corporation +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation version 2. +* +* This program is distributed "as is" WITHOUT ANY WARRANTY of any +* kind, whether express or implied; without even the implied warranty +* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __ARM_BCM63XX_H +#define __ARM_BCM63XX_H + +#define IO_ADDRESS (x) (((x) & 0x00ffffff) + 0xfc000000) + +/* AHB register space */ +#define BCM63XX_AHB_PHYS 0x80001000 +#define BCM63XX_AHB_VIRT IO_ADDRESS(BCM63XX_AHB_PHYS) +#define BCM63XX_AHB_SIZE 0x800000 + +/* PERIPH (legacy) register space */ +#define BCM63XX_PERIPH_PHYS 0xfffe8000 +#define BCM63XX_PERIPH_VIRT IO_ADDRESS(BCM63XX_PERIPH_PHYS) +#define BCM63XX_PERIPH_SIZE 0x10000 + +#endif /* __ARM_BCM63XX_H */
arch/arm/mach-bcm/board_bcm63xx.c new file +94 -0
94 lines not on this page · raw message
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH RESEND 1/5 ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
Quoted 7 lines · On Monday 21 April 2014 18:39:14 Florian Fainelli wrote:
This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC.
Due to the two specific register address spaces located at 0x8000_0000 and 0xfffe_0000, we need to setup a specific iotable descriptor for those to be remapped at the expected virtual addresses.
What is the significance of the "expected virtual address"? All drivers nowadays should call ioremap() and use whatever virtual address comes out of that.
Quoted 3 lines
Finally, the PL310 cache controller requires a bit of tweaking before handing its initialization over
l2x0_of_init(), this is also taken care of to make sure that its size is properly configured.
Russell has just spent a lot of work on cleaning up the l2x0 setup of various platforms. I really don't want to see new platform specific code for this.
Quoted 13 lines
arch/arm/mach-bcm/Kconfig +5
-0@@ -69,6 +69,26 @@ config ARCH_BCM_5301X different SoC or with the older BCM47XX and BCM53XX based network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx +config ARCH_BCM_63XX + bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7 + depends on MMU + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP
arch/arm/mach-bcm/Kconfig config ARCH_BCM_5301X · line 86
Quoted 10 lines
arch/arm/mach-bcm/Kconfig +10
-0+ select ARM_GIC + select ARM_GLOBAL_TIMER + select CACHE_L2X0 + select COMMON_CLK + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_ARM_ARCH_TIMER + select HAVE_ARM_TWD if SMP + select HAVE_ARM_SCU if SMP + select HAVE_SMP
A lot of these are already selected by ARCH_MULTI_V7 and can be omitted here.
Quoted 4 lines
arch/arm/mach-bcm/Kconfig +4
-0+#ifndef __ARM_BCM63XX_H +#define __ARM_BCM63XX_H + +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + 0xfc000000)
arch/arm/mach-bcm/Kconfig config ARCH_BCM_5301X
Quoted 10 lines
arch/arm/mach-bcm/Kconfig +10
-0+ +/* AHB register space */ +#define BCM63XX_AHB_PHYS 0x80001000 +#define BCM63XX_AHB_VIRT IO_ADDRESS(BCM63XX_AHB_PHYS) +#define BCM63XX_AHB_SIZE 0x800000 + +/* PERIPH (legacy) register space */ +#define BCM63XX_PERIPH_PHYS 0xfffe8000 +#define BCM63XX_PERIPH_VIRT IO_ADDRESS(BCM63XX_PERIPH_PHYS) +#define BCM63XX_PERIPH_SIZE 0x10000
You shouldn't need these any more. If you do, just move all of this into the main file, to ensure no other file accidentally relies on hardcoded values.
Note that BCM63XX_AHB_PHYS is nor aligned, so AFAICT you don't actually get a huge page entry for it, and there is no point doing this at all, as it has neither functional nor performance relevance.
You may have out-of-tree drivers that you haven't cleaned up or posted yet relying on specific static mappings, but that is no reason to have these mappings in the mainline kernel.
arch/arm/mach-bcm/board_bcm63xx.c
Quoted 5 lines
arch/arm/mach-bcm/board_bcm63xx.c new file +0
-0
Maybe just "bcm63xx.c"? We don't really do "board" files any more.
Quoted 17 lines
arch/arm/mach-bcm/board_bcm63xx.c new file +17
-0+static void __init bcm63xx_l2cc_init (void ) +{ +u32 auxctl_val =0 , auxctl_msk = ~0UL ; + +/* 16-way cache */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT ); + auxctl_msk &= ~(1 <<L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT ); +/* 32 KB */ + auxctl_val |= (2 <<L2X0_AUX_CTRL_WAY_SIZE_SHIFT ); + auxctl_msk &= ~(L2X0_AUX_CTRL_WAY_SIZE_MASK ); + +/* +* Set bit 22 in the auxiliary control register. If this bit +* is cleared, PL310 treats Normal Shared Non-cacheable +* accesses as Cacheable no-allocate. +*/ + auxctl_val |= (1 <<L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT );
arch/arm/mach-bcm/board_bcm63xx.c line 54
Quoted 10 lines
arch/arm/mach-bcm/board_bcm63xx.c new file +10
-0+ +/* Allow non-secure access */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT ); +/* Instruction prefetch */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT ); +/* Early BRESP */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_EARLY_BRESP_SHIFT ); + +l2x0_of_init (auxctl_val, auxctl_msk); +}
What are the power-on values of bits you override here? Are you sure you have to force all of them?
Don't we already have ways to specify the same things in DT properties?
Arnd
PATCH RESEND 1/5 ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
2014-04-22 3:45 GMT-07:00 Arnd Bergmann <[email protected]>:
Quoted 13 lines · On Monday 21 April 2014 18:39:14 Florian Fainelli wrote:
Quoted 7 lines
This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC.
Due to the two specific register address spaces located at 0x8000_0000 and 0xfffe_0000, we need to setup a specific iotable descriptor for those to be remapped at the expected virtual addresses.
What is the significance of the "expected virtual address"? All drivers nowadays should call
ioremap()and use whatever virtual address comes out of that.
Quoted 7 lines
Quoted 3 lines
Finally, the PL310 cache controller requires a bit of tweaking before handing its initialization over
l2x0_of_init(), this is also taken care of to make sure that its size is properly configured.Russell has just spent a lot of work on cleaning up the l2x0 setup of various platforms. I really don't want to see new platform specific code for this.
Ok, I will try with his cleanup patchset applied and see if I need any platform specific implementation.
Quoted 47 lines
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arch/arm/mach-bcm/Kconfig +5
-0@@ -69,6 +69,26 @@ config ARCH_BCM_5301X different SoC or with the older BCM47XX and BCM53XX based network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx +config ARCH_BCM_63XX + bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7 + depends on MMU + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMParch/arm/mach-bcm/Kconfig config ARCH_BCM_5301X · line 86
Quoted 10 lines
arch/arm/mach-bcm/Kconfig +10
-0+ select ARM_GIC + select ARM_GLOBAL_TIMER + select CACHE_L2X0 + select COMMON_CLK + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_ARM_ARCH_TIMER + select HAVE_ARM_TWD if SMP + select HAVE_ARM_SCU if SMP + select HAVE_SMPA lot of these are already selected by
ARCH_MULTI_V7and can be omitted here.Quoted 4 lines
arch/arm/mach-bcm/Kconfig +4
-0+#ifndef __ARM_BCM63XX_H +#define __ARM_BCM63XX_H + +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + 0xfc000000)arch/arm/mach-bcm/Kconfig config ARCH_BCM_5301X
Quoted 10 lines
arch/arm/mach-bcm/Kconfig +10
-0+ +/* AHB register space */ +#define BCM63XX_AHB_PHYS 0x80001000 +#define BCM63XX_AHB_VIRT IO_ADDRESS(BCM63XX_AHB_PHYS) +#define BCM63XX_AHB_SIZE 0x800000 + +/* PERIPH (legacy) register space */ +#define BCM63XX_PERIPH_PHYS 0xfffe8000 +#define BCM63XX_PERIPH_VIRT IO_ADDRESS(BCM63XX_PERIPH_PHYS) +#define BCM63XX_PERIPH_SIZE 0x10000You shouldn't need these any more. If you do, just move all of this into the main file, to ensure no other file accidentally relies on hardcoded values.
Quoted 8 lines
Note that
BCM63XX_AHB_PHYSis nor aligned, so AFAICT you don't actually get a huge page entry for it, and there is no point doing this at all, as it has neither functional nor performance relevance.You may have out-of-tree drivers that you haven't cleaned up or posted yet relying on specific static mappings, but that is no reason to have these mappings in the mainline kernel.
I tried without the iotable entries, and any register access to these regions did hang the system, I will check harder what was going on there.
Quoted 8 lines
arch/arm/mach-bcm/board_bcm63xx.c
Quoted 6 lines
arch/arm/mach-bcm/board_bcm63xx.c new file +0
-0Maybe just "
bcm63xx.c"? We don't really do "board" files any more.
Makes sense, there is nothing board specific here (and there should not be anyway).
Quoted 35 lines
Quoted 18 lines
arch/arm/mach-bcm/board_bcm63xx.c new file +17
-0+static void __init bcm63xx_l2cc_init (void ) +{ +u32 auxctl_val =0 , auxctl_msk = ~0UL ; + +/* 16-way cache */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT ); + auxctl_msk &= ~(1 <<L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT ); +/* 32 KB */ + auxctl_val |= (2 <<L2X0_AUX_CTRL_WAY_SIZE_SHIFT ); + auxctl_msk &= ~(L2X0_AUX_CTRL_WAY_SIZE_MASK ); + +/* +* Set bit 22 in the auxiliary control register. If this bit +* is cleared, PL310 treats Normal Shared Non-cacheable +* accesses as Cacheable no-allocate. +*/ + auxctl_val |= (1 <<L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT );arch/arm/mach-bcm/board_bcm63xx.c line 54
Quoted 10 lines
arch/arm/mach-bcm/board_bcm63xx.c new file +10
-0+ +/* Allow non-secure access */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT ); +/* Instruction prefetch */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT ); +/* Early BRESP */ + auxctl_val |= (1 <<L2X0_AUX_CTRL_EARLY_BRESP_SHIFT ); + +l2x0_of_init (auxctl_val, auxctl_msk); +}What are the power-on values of bits you override here? Are you sure you have to force all of them?
Don't we already have ways to specify the same things in DT properties?
Arnd
Signature · 1 line
Florian
Arnd Bergmann
maintainerPATCH RESEND 1/5 ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
Quoted 24 lines · On Thursday 01 May 2014 22:32:27 Florian Fainelli wrote:
Quoted 24 lines
Quoted 4 lines
arch/arm/mach-bcm/bcm63xx.h new file +4
-0+#ifndef __ARM_BCM63XX_H +#define __ARM_BCM63XX_H + +#define IO_ADDRESS (x) (((x) & 0x00ffffff) + 0xfc000000)arch/arm/mach-bcm/bcm63xx.h line 27
Quoted 10 lines
arch/arm/mach-bcm/bcm63xx.h new file +10
-0+ +/* AHB register space */ +#define BCM63XX_AHB_PHYS 0x80001000 +#define BCM63XX_AHB_VIRT IO_ADDRESS(BCM63XX_AHB_PHYS) +#define BCM63XX_AHB_SIZE 0x800000 + +/* PERIPH (legacy) register space */ +#define BCM63XX_PERIPH_PHYS 0xfffe8000 +#define BCM63XX_PERIPH_VIRT IO_ADDRESS(BCM63XX_PERIPH_PHYS) +#define BCM63XX_PERIPH_SIZE 0x10000You shouldn't need these any more. If you do, just move all of this into the main file, to ensure no other file accidentally relies on hardcoded values.
Note that
BCM63XX_AHB_PHYSis nor aligned, so AFAICT you don't actually get a huge page entry for it, and there is no point doing this at all, as it has neither functional nor performance relevance.
Quoted 7 lines
Quoted 3 lines
You may have out-of-tree drivers that you haven't cleaned up or posted yet relying on specific static mappings, but that is no reason to have these mappings in the mainline kernel.
I tried without the iotable entries, and any register access to these regions did hang the system, I will check harder what was going on there.
Can you clarify what you mean with 'any register access to these regions did hang the system'? If you remove the call to iotable_init, you obviously can't access the registers through BCM63XX_{AHB,PERIPH}_VIRT any longer, but accesses through a pointer returned from ioremap() should keep working as before.
The DEBUG_LL early output is a special case here, these need one of three options:
- .map_io is NULL (preferred)
- .map_io points to a function that calls debug_ll_io_init()
- .map_io points to a function that calls iotable_init with an equivalent or larger mapping as debug_ll_io_init() would.
I suspect you were doing the third here for historic reasons.
Arnd
PATCH RESEND 1/5 ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
2014-05-02 0:55 GMT-07:00 Arnd Bergmann <[email protected]>:
Quoted 29 lines · On Thursday 01 May 2014 22:32:27 Florian Fainelli wrote:
Quoted 28 lines
Quoted 27 lines
Quoted 4 lines
arch/arm/mach-bcm/bcm63xx.h new file +4
-0+#ifndef __ARM_BCM63XX_H +#define __ARM_BCM63XX_H + +#define IO_ADDRESS (x) (((x) & 0x00ffffff) + 0xfc000000)arch/arm/mach-bcm/bcm63xx.h line 27
Quoted 10 lines
arch/arm/mach-bcm/bcm63xx.h new file +10
-0+ +/* AHB register space */ +#define BCM63XX_AHB_PHYS 0x80001000 +#define BCM63XX_AHB_VIRT IO_ADDRESS(BCM63XX_AHB_PHYS) +#define BCM63XX_AHB_SIZE 0x800000 + +/* PERIPH (legacy) register space */ +#define BCM63XX_PERIPH_PHYS 0xfffe8000 +#define BCM63XX_PERIPH_VIRT IO_ADDRESS(BCM63XX_PERIPH_PHYS) +#define BCM63XX_PERIPH_SIZE 0x10000You shouldn't need these any more. If you do, just move all of this into the main file, to ensure no other file accidentally relies on hardcoded values.
Note that
BCM63XX_AHB_PHYSis nor aligned, so AFAICT you don't actually get a huge page entry for it, and there is no point doing this at all, as it has neither functional nor performance relevance.You may have out-of-tree drivers that you haven't cleaned up or posted yet relying on specific static mappings, but that is no reason to have these mappings in the mainline kernel.
Quoted 6 lines
Quoted 3 lines
I tried without the iotable entries, and any register access to these regions did hang the system, I will check harder what was going on there.
Can you clarify what you mean with 'any register access to these regions did hang the system'?
I would not get any console output progress around the time we initialize the MMU (roughly), neither would I get an exception since that is too early in the boot process.
Quoted 8 lines
If you remove the call to
iotable_init,
you obviously can't access the registers through BCM63XX_{AHB,PERIPH}_VIRT any longer, but accesses through a pointer returned fromioremap()should keep working as before.The
DEBUG_LLearly output is a special case here, these need one of three options:
Quoted 6 lines
- .map_io is NULL (preferred)
- .map_io points to a function that callsdebug_ll_io_init()
- .map_io points to a function that callsiotable_initwith an equivalent or larger mapping asdebug_ll_io_init()would.I suspect you were doing the third here for historic reasons.
I think you are right, I was in the 3rd case where accessing the UART using its virtual address would make the system. Reading through devicemaps_init(), defining a custom map_io() functions means you are in control and you explicitely need to call debug_ll_io_init(), which I was not doing when I removed my custom map_io() implementation.
Thanks!
Signature · 1 line
Florian
Arnd Bergmann
maintainerPATCH RESEND 1/5 ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
Quoted 15 lines · On Monday 05 May 2014 15:41:43 Florian Fainelli wrote:
2014-05-02 0:55 GMT-07:00 Arnd Bergmann <[email protected]>:
Quoted 14 lines · On Thursday 01 May 2014 22:32:27 Florian Fainelli wrote:
If you remove the call to
iotable_init,
you obviously can't access the registers through BCM63XX_{AHB,PERIPH}_VIRT any longer, but accesses through a pointer returned fromioremap()should keep working as before.The
DEBUG_LLearly output is a special case here, these need one of three options:- .map_io is NULL (preferred)
- .map_io points to a function that callsdebug_ll_io_init()
- .map_io points to a function that callsiotable_initwith an equivalent or larger mapping asdebug_ll_io_init()would.
Quoted 7 lines
Quoted 1 line
I suspect you were doing the third here for historic reasons.
I think you are right, I was in the 3rd case where accessing the UART using its virtual address would make the system. Reading through
devicemaps_init(), defining a custommap_io()functions means you are in control and you explicitely need to calldebug_ll_io_init(), which I was not doing when I removed my custommap_io()implementation.
Ok, so I guess it should all work now if you remove the function from the submission, or keep one in your private tree that sets up any mapping needed by drivers that are not converted along with debug_ll_io_init().
Arnd
PATCH RESEND 2/5 ARM: BCM63XX: add low-level UART debug support
In reply to Florian FainelliBroadcom BCM63xx DSL SoCs have a different UART implementation for which we need specially crafted low-level debug assembly code to support. Add support for this using the standard definitions provided in include/linux/serial_bcm63xx.h (shared with their MIPS counterparts).
--- arch/arm/Kconfig.debug | 18 ++++++++++++++++-- arch/arm/include/debug/bcm63xxx.S | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/debug/bcm63xxx.S
arch/arm/Kconfig.debug +16 -2
@@ -122,6 +122,11 @@ choice mobile SoCs in the Kona family of chips (e.g. bcm28155, bcm11351, etc...) + config DEBUG_BCM63XX + bool "Kernel low-level debugging on BCM63XX UART" + depends on ARCH_BCM_63XX + select DEBUG_UART_BCM63XX + config DEBUG_BERLIN_UART bool "Marvell Berlin SoC Debug UART" depends on ARCH_BERLIN
@@ -981,6 +986,7 @@ config DEBUG_LL_INCLUDE default "debug/vf.S" if DEBUG_VF_UART default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 + default "debug/bcm63xxx.S" if DEBUG_UART_BCM63XX default "mach/debug-macro.S" # Compatibility options for PL01x
@@ -1000,6 +1006,10 @@ config DEBUG_UART_8250 ARCH_IOP33X || ARCH_IXP4XX || ARCH_KIRKWOOD || \ ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC +# Compatibility options for BCM63xx +config DEBUG_UART_BCM63XX + def_bool ARCH_BCM_63XX + config DEBUG_UART_PHYS hex "Physical base address of debug UART" default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
@@ -1055,10 +1065,12 @@ config DEBUG_UART_PHYS default 0xffc02000 if DEBUG_SOCFPGA_UART default 0xffd82340 if ARCH_IOP13XX default 0xfff36000 if DEBUG_HIGHBANK_UART + default 0xfffe8600 if DEBUG_UART_BCM63XX default 0xfffff700 if ARCH_IOP33X depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ DEBUG_LL_UART_EFM32 || \ - DEBUG_UART_8250 || DEBUG_UART_PL01X + DEBUG_UART_8250 || DEBUG_UART_PL01X || \ + DEBUG_UART_BCM63XX config DEBUG_UART_VIRT hex "Virtual base address of debug UART"
@@ -1080,6 +1092,7 @@ config DEBUG_UART_VIRT default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 default 0xfb009000 if DEBUG_REALVIEW_STD_PORT default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT + default 0xfcfe8600 if DEBUG_UART_BCM63XX default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX default 0xfd000000 if ARCH_SPEAR13XX default 0xfd012000 if ARCH_MV78XX0
@@ -1116,7 +1129,8 @@ config DEBUG_UART_VIRT default 0xff003000 if DEBUG_U300_UART default DEBUG_UART_PHYS if !MMU depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ - DEBUG_UART_8250 || DEBUG_UART_PL01X + DEBUG_UART_8250 || DEBUG_UART_PL01X || \ + DEBUG_UART_BCM63XX config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART"
arch/arm/include/debug/bcm63xxx.S new file +33 -0
@@ -0,0 +1,33 @@ +/* + * Broadcom BCM63xxx low-level UART debug + * + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/serial_bcm63xx.h> + + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm + + .macro senduart, rd, rx + /* word access do not work */ + strb \rd, [\rx, #UART_FIFO_REG] + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #UART_IR_REG] + tst \rd, #(1 << UART_IR_TXEMPTY) + beq 1001b + .endm + + .macro busyuart, rd, rx +1002: ldr \rd, [\rx, #UART_IR_REG] + tst \rd, #(1 << UART_IR_TXTRESH) + beq 1002b + .endm
Signature · 1 line
1.9.1
PATCH RESEND 3/5 ARM: BCM63XX: add BCM63138 minimal Device Tree
In reply to Florian FainelliAdd a very minimalistic BCM63138 Device Tree include file which describes the BCM63138 SoC with only the basic set of required peripherals:
- Cortex A9 CPU
- ARM GIC
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
--- arch/arm/boot/dts/bcm63138.dtsi | 109 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63138.dtsi
arch/arm/boot/dts/bcm63138.dtsi new file +109 -0
@@ -0,0 +1,109 @@ +/* + * Broadcom BCM63138 DSL SoCs Device Tree + * + * Copyright (C) 2014 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63138"; + model = "Broadcom BCM63138 DSL SoC"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + }; + }; + + /* ARM bus */ + axi at 80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x783003>; + reg = <0x80000000 0x783003>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller at 1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + mpcore at 1e000 { + compatible = "simple-bus"; + reg = <0x1e000 0x20000>; + ranges = <0 0x1e000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + + scu: scu at 0 { + compatible = "arm,cortex-a9-scu"; + reg = <0x0 0x100>; + }; + + gic: interrupt-controller at 100 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1000 0x1000 + 0x100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + + global_timer: timer at 200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x200 0x20>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&arm_timer_clk>; + }; + + local_timer: local-timer at 600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&arm_timer_clk>; + }; + + twd_watchdog: watchdog at 620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x620 0x20>; + interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + + /* Legacy UBUS base */ + ubus at fffe8000 { + compatible = "simple-bus"; + reg = <0xfffe8000 0x8053>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8053>; + }; +};
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH RESEND 3/5 ARM: BCM63XX: add BCM63138 minimal Device Tree
Quoted 9 lines · On Monday 21 April 2014 18:39:16 Florian Fainelli wrote:
arch/arm/boot/dts/bcm63138.dtsi new file +8
-0+#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63138"; + model = "Broadcom BCM63138 DSL SoC"; + interrupt-parent = <&gic>; + + cpus {
arch/arm/boot/dts/bcm63138.dtsi line 29
Quoted 10 lines
arch/arm/boot/dts/bcm63138.dtsi new file +10
-0+ #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + };
Even if you don't support SMP yet, I can see no reason not to list both CPUs here. The binding is known and the code should ignore the extra cores if it doesn't know how to turn them on.
arch/arm/boot/dts/bcm63138.dtsi line 46
Quoted 6 lines
arch/arm/boot/dts/bcm63138.dtsi new file +6
-0+ + /* ARM bus */ + axi at 80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x783003>; + reg = <0x80000000 0x783003>;
The length seems odd, I would expect that the bus actually translates all addresses in the 0x80000000 range to downstream devices even if there is nothing connected. Just round it up to your best knowledge.
I would also drop the 'reg' property. Since you don't have a specific "compatible" value, there is no way to use the registers in this node.
Quoted 7 lines
arch/arm/boot/dts/bcm63138.dtsi new file +7
-0+ #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller at 1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified;
arch/arm/boot/dts/bcm63138.dtsi line 63
Quoted 10 lines
arch/arm/boot/dts/bcm63138.dtsi new file +10
-0+ cache-level = <2>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + mpcore at 1e000 { + compatible = "simple-bus"; + reg = <0x1e000 0x20000>; + ranges = <0 0x1e000 0x20000>; + #address-cells = <1>; + #size-cells = <1>;
Same thing here.
Also, can you explain why there is a separate 'mpcore' bus, and why the cache controller is not part of that?
Do you have reason to believe that this is how the hardware actually looks?
arch/arm/boot/dts/bcm63138.dtsi line 109
Quoted 10 lines
arch/arm/boot/dts/bcm63138.dtsi new file +10
-0+ + /* Legacy UBUS base */ + ubus at fffe8000 { + compatible = "simple-bus"; + reg = <0xfffe8000 0x8053>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8053>; + }; +};
Again, use a proper 'length' here and remove the 'reg' property.
Arnd
PATCH RESEND 3/5 ARM: BCM63XX: add BCM63138 minimal Device Tree
2014-04-22 3:52 GMT-07:00 Arnd Bergmann <[email protected]>:
Quoted 17 lines · On Monday 21 April 2014 18:39:16 Florian Fainelli wrote:
Quoted 16 lines
arch/arm/boot/dts/bcm63138.dtsi new file +15
-0+#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63138"; + model = "Broadcom BCM63138 DSL SoC"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>;
Quoted 8 lines
arch/arm/boot/dts/bcm63138.dtsi line 29
Quoted 3 lines
arch/arm/boot/dts/bcm63138.dtsi new file +3
-0+ reg = <0>; + }; + };Even if you don't support SMP yet, I can see no reason not to list both CPUs here. The binding is known and the code should ignore the extra cores if it doesn't know how to turn them on.
OK.
Quoted 8 lines
arch/arm/boot/dts/bcm63138.dtsi line 46
Quoted 7 lines
arch/arm/boot/dts/bcm63138.dtsi new file +6
-0+ + /* ARM bus */ + axi at 80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x783003>; + reg = <0x80000000 0x783003>;
Quoted 8 lines
The length seems odd, I would expect that the bus actually translates all addresses in the
0x80000000range to downstream devices even if there is nothing connected. Just round it up to your best knowledge.I would also drop the 'reg' property. Since you don't have a specific "compatible" value, there is no way to use the registers in this node.
OK.
Quoted 22 lines
Quoted 8 lines
arch/arm/boot/dts/bcm63138.dtsi new file +7
-0+ #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller at 1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified;arch/arm/boot/dts/bcm63138.dtsi line 63
Quoted 10 lines
arch/arm/boot/dts/bcm63138.dtsi new file +10
-0+ cache-level = <2>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + mpcore at 1e000 { + compatible = "simple-bus"; + reg = <0x1e000 0x20000>; + ranges = <0 0x1e000 0x20000>; + #address-cells = <1>; + #size-cells = <1>;Same thing here.
Quoted 5 lines
Also, can you explain why there is a separate 'mpcore' bus, and why the cache controller is not part of that?
Do you have reason to believe that this is how the hardware actually looks?
I think I was just mistaken by how the register space looks like and is named, but there probably is not a separate underlying bus, so I will move this up one level as it should.
Quoted 23 lines
arch/arm/boot/dts/bcm63138.dtsi line 109
Quoted 11 lines
arch/arm/boot/dts/bcm63138.dtsi new file +10
-0+ + /* Legacy UBUS base */ + ubus at fffe8000 { + compatible = "simple-bus"; + reg = <0xfffe8000 0x8053>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8053>; + }; +};Again, use a proper 'length' here and remove the 'reg' property.
Arnd
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Signature · 1 line
Florian
PATCH RESEND 4/5 ARM: BCM63XX: add BCM963138DVT Reference platform DTS
In reply to Florian FainelliAdd a DTS file for the Broadcom BCM963138DVT reference platform board which leverages the bcm63138.dtsi SoC DTSi file.
--- arch/arm/boot/dts/Makefile | 3 +++ arch/arm/boot/dts/bcm63138dvt.dts | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63138dvt.dts
arch/arm/boot/dts/Makefile +3 -0
@@ -53,8 +53,11 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ bcm21664-garnet.dtb +dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ + bcm28155-ap.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb +dtb-$(CONFIG_ARCH_BCM_63XX) += bcm63138dvt.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ berlin2cd-google-chromecast.dtb
arch/arm/boot/dts/bcm63138dvt.dts new file +18 -0
@@ -0,0 +1,18 @@ +/* + * Broadcom BCM63138 Reference Board DTS + * + * Copyright (C) 2014 Broadcom Corporation + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + compatible = "BCM963138DVT", "brcm,bcm63138"; + model = "Broadcom BCM963138DVT"; + + memory { + reg = <0x0 0x08000000>; + }; +};
Signature · 1 line
1.9.1
PATCH RESEND 4/5 ARM: BCM63XX: add BCM963138DVT Reference platform DTS
Quoted 9 lines · Florian Fainelli
Add a DTS file for the Broadcom BCM963138DVT reference platform board which leverages the
bcm63138.dtsiSoC DTSi file.Signed-off-by Florian Fainelli <[email protected]>--- arch/arm/boot/dts/Makefile | 3 +++ arch/arm/boot/dts/bcm63138dvt.dts | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63138dvt.dts
Shouldn't the file be called bcm*9*63138dvt.dts, same as the board name?
Regards
Jonas
PATCH RESEND 4/5 ARM: BCM63XX: add BCM963138DVT Reference platform DTS
In reply to Florian FainelliQuoted 15 lines · Florian Fainelli
Add a DTS file for the Broadcom BCM963138DVT reference platform board which leverages the
bcm63138.dtsiSoC DTSi file.Signed-off-by Florian Fainelli <[email protected]>--- arch/arm/boot/dts/Makefile | 3 +++ arch/arm/boot/dts/bcm63138dvt.dts | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63138dvt.dtsarch/arm/boot/dts/Makefile +0
-0
arch/arm/boot/dts/Makefile dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb · line 57
Quoted 5 lines
arch/arm/boot/dts/Makefile +2
-0@@ -53,8 +53,11 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ bcm21664-garnet.dtb +dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ + bcm28155-ap.dtb
Remove this stray change.
Quoted 14 lines
arch/arm/boot/dts/Makefile +1
-0dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb +dtb-$(CONFIG_ARCH_BCM_63XX) += bcm63138dvt.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ berlin2cd-google-chromecast.dtbarch/arm/boot/dts/bcm63138dvt.dts new file +2
-0@@ -0,0 +1,18 @@ +/* + * Broadcom BCM63138 Reference Board DTS
arch/arm/boot/dts/bcm63138dvt.dts line 12
Quoted 10 lines
arch/arm/boot/dts/bcm63138dvt.dts new file +10
-0+ * + * Copyright (C) 2014 Broadcom Corporation + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + compatible = "BCM963138DVT", "brcm,bcm63138";
The specific board compatible string needs a vendor prefix. Also, there's only some rare old examples that use upper case in their compatible strings. Let's conform to what 99% of compatible strings do here and have:
compatible = "brcm,bcm963138dvt", "brcm,bcm63138";
Along the lines of Jonas' question? Is there really a "9" prepended in this board name given that the filename is bcm63138dvt.dts? Either way, this should be consistent between compatible and filename.
-Matt
Quoted 9 lines
arch/arm/boot/dts/bcm63138dvt.dts new file +6
-0+ model = "Broadcom BCM963138DVT"; + + memory { + reg = <0x0 0x08000000>; + }; +};Signature · 1 line
1.9.1
PATCH RESEND 5/5 MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs
In reply to Florian FainelliAdd a MAINTAINERS entry covering all the Broadcom BCM63xx ARM DSL SoCs files along with the relevant git tree and mailing-list.
--- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+)
MAINTAINERS +11 -0
@@ -1916,6 +1916,7 @@ F: arch/arm/boot/dts/bcm2835* F: arch/arm/configs/bcm2835_defconfig F: drivers/*/*bcm2835* + BROADCOM BCM5301X ARM ARCHICTURE M: Hauke Mehrtens <[email protected]> L: linux-arm-kernel at lists.infradead.org
@@ -1924,6 +1925,16 @@ F: arch/arm/mach-bcm/bcm_5301x.c F: arch/arm/boot/dts/bcm5301x.dtsi F: arch/arm/boot/dts/bcm470* +BROADCOM BCM63XX ARM ARCHITECTURE +M: Florian Fainelli <[email protected]> +L: linux-arm-kernel at lists.infradead.org +T: git git://git.github.com/broadcom/arm-bcm63xx +S: Maintained +F: arch/arm/mach-bcm/board_bcm63xx.c +F: arch/arm/mach-bcm/bcm63xx.h +F: arch/arm/include/debug/bcm63xxx.S +F: arch/arm/configs/bcm_defconfig + BROADCOM TG3 GIGABIT ETHERNET DRIVER M: Nithin Nayak Sujir <[email protected]> M: Michael Chan <[email protected]>
Signature · 1 line
1.9.1