clk: Samsung: audss: Add support for Exynos5420

From: Andrew Bresticker <[email protected]>

Different Exynos SoCs have different names for certain input clocks to the AudioSS block. Since the order in which clock providers are probed is not guaranteed, we can't use the device-tree to pass the correct input clocks.

Instead, use the compatibility string to determine what the correct parent clocks should be.

Signed-off-by Andrew Bresticker <[email protected]>

---
 drivers/clk/samsung/clk-exynos-audss.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

drivers/clk/samsung/clk-exynos-audss.c +11 -1

index 86d2606..d81c5f8 100644
@@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = {
 /* list of all parent clock list */
 static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
 static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+static const char *sclk_pcm_p = "sclk_pcm0";
 
 #ifdef CONFIG_PM_SLEEP
 static int exynos_audss_clk_suspend(void)

@@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np)
                return;
        }
 
+       /* fix up clock parent names based on SoC */
+       if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {
+               mout_i2s_p[2] = "sclk_maudio0";
+               sclk_pcm_p = "sclk_maupcm0";
+       } else if (of_device_is_compatible(np,
+                                       "samsung,exynos5250-audss-clock")) {
+               sclk_pcm_p = "div_pcm0";
+       }
+
        clk_data.clks = clk_table;
        clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

@@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np)
                                reg_base + ASS_CLK_GATE, 4, 0, &lock);
 
        clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
-                               "div_pcm0", CLK_SET_RATE_PARENT,
+                               sclk_pcm_p, CLK_SET_RATE_PARENT,
                                reg_base + ASS_CLK_GATE, 5, 0, &lock);
 
        if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {

Signature · 1 line

1.7.4.4

Quoting Padmavathi Venna (2013-08-16 00:49:36)

Quoted 2 lines

From: Andrew Bresticker <[email protected]>

Quoted 4 lines

Different Exynos SoCs have different names for certain input clocks to the AudioSS block. Since the order in which clock providers are probed is not guaranteed, we can't use the device-tree to pass the correct input clocks.

Why not? Could your audss binding include something like a "clocks" property with phandles to the input clocks? Then your audss clock driver could just use clk_get like a regular driver to get the parents.

This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420 audio subsystem has a gate bit for ADMA controller and the some of the parent clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch adds provision for supporting both the platforms by determining the parent clk names based on compatible string.

Changes since V1:
- parent clocks are determined by using the compatible string and not passed via device tree as done in V1 because the probing order of the clock providers can't be guaranteed.

Andrew Bresticker (3):
clk: exynos-audss: add support for Exynos 5420
clk: exynos-audss: set correct parent clocks

ARM: dts: exynos5420: add audio clock controller

Padmavathi Venna (1):
ARM: dts: Correct the /include entry on exynos5420 dtsi file

 .../devicetree/bindings/clock/clk-exynos-audss.txt |    7 +++++--
 arch/arm/boot/dts/exynos5420.dtsi                  |   11 ++++++++++-
 drivers/clk/samsung/clk-exynos-audss.c             |   20 +++++++++++++++++++-
 include/dt-bindings/clk/exynos-audss-clk.h         |    3 ++-
 4 files changed, 36 insertions(+), 5 deletions(-)

--
1.7.4.4

Hi Mike,

Quoted 11 lines · Padmavathi Venna

This patch set adds support for audio subsystem clks on Exynos5420. Exynos5420 audio subsystem has a gate bit for ADMA controller and the some of the parent clks for mout_i2s and sclk_pcm are different from Exynos5250. So this patch adds provision for supporting both the platforms by determining the parent clk names based on compatible string.

Changes since V1:
- parent clocks are determined by using the compatible string and not passed via device tree as done in V1 because the probing order of the clock providers can't be guaranteed.

Quoted 3 lines

Andrew Bresticker (3):
clk: exynos-audss: add support for Exynos 5420
clk: exynos-audss: set correct parent clocks

Can you apply the above two patches into your tree?