features and bugfixes for hns3
v2 cover features and bugfixes for hns3
This series add five features according to the 21.05 roadmap, and also two cleanups added.
Chengchang Tang (1):
net/hns3: support for outer UDP cksum
Chengwen Feng (2):
net/hns3: support runtime config to select IO burst func net/hns3: support Tx push quick doorbell to improve perf
Hongbo Zheng (4):
net/hns3: adjust the format of RAS related structures net/hns3: delete redundant xstats RAS statistics net/hns3: support query Tx descriptor status net/hns3: support query Rx descriptor status
Min Hu (Connor) (2):
net/hns3: support imissed stats for PF/VF
net/hns3: support oerrors stats in PF
doc/guides/nics/features/hns3.ini | 2 + doc/guides/nics/features/hns3_vf.ini | 2 + doc/guides/rel_notes/release_21_05.rst | 5 + drivers/net/hns3/hns3_cmd.c | 3 + drivers/net/hns3/hns3_cmd.h | 14 + drivers/net/hns3/hns3_ethdev.c | 87 +- drivers/net/hns3/hns3_ethdev.h | 73 +- drivers/net/hns3/hns3_ethdev_vf.c | 19 +- drivers/net/hns3/hns3_intr.c | 2127 ++++++++++++++++++-------------- drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_rxtx.c | 288 ++++- drivers/net/hns3/hns3_rxtx.h | 30 +- drivers/net/hns3/hns3_rxtx_vec_neon.h | 2 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 7 +- drivers/net/hns3/hns3_stats.c | 388 +++--- drivers/net/hns3/hns3_stats.h | 2 +- 16 files changed, 1923 insertions(+), 1128 deletions(-)
Signature · 1 line
2.7.4
PATCH v2 1/9 net/hns3: support runtime config to select IO burst func
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common.
The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.
Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 74 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 12 ++++++ drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 54 ++++++++++++++++++------- 5 files changed, 128 insertions(+), 14 deletions(-)
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +74 -0
92 lines not on this page · raw message
drivers/net/hns3/hns3_ethdev.h +12 -0
@@ -772,9 +772,20 @@ struct hns3_adapter {bool tx_simple_allowed;bool tx_vec_allowed; +uint32_t rx_func_hint; +uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { +HNS3_IO_FUNC_HINT_NONE =0 , +HNS3_IO_FUNC_HINT_VEC , +HNS3_IO_FUNC_HINT_SVE , +HNS3_IO_FUNC_HINT_SIMPLE , +HNS3_IO_FUNC_HINT_COMMON +}; +#define HNS3_DEV_SUPPORT_DCB_B 0x0#define HNS3_DEV_SUPPORT_COPPER_B 0x1#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
@@ -975,6 +986,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info);void hns3vf_update_link_status (struct hns3_hw *hw,uint8_t link_status,uint32_t link_speed,uint8_t link_duplex); +void hns3_parse_devargs (struct rte_eth_dev *dev);static inline bool is_reset_pending (struct hns3_adapter *hns)
drivers/net/hns3/hns3_ethdev_vf.c +1 -0
@@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state =HNS3_NIC_UNINITIALIZED ; hns->is_vf = true; hw->data = eth_dev->data; +hns3_parse_devargs (eth_dev); ret =hns3_reset_init (hw);if (ret)
drivers/net/hns3/hns3_rxtx.c +40 -14
72 lines not on this page · raw message
Signature · 1 line
2.7.4
Re: [dpdk-dev] [PATCH v2 1/9] net/hns3: support runtime config to select IO burst func
Quoted 37 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>
Quoted 8 lines
--- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 74 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 12 ++++++ drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 54 ++++++++++++++++++------- 5 files changed, 128 insertions(+), 14 deletions(-)
Hi Connor,
There are two recently added APIs to enable user to select vector datapath:
'rte_vect_set_max_simd_bitwidth()' 'rte_vect_get_max_simd_bitwidth()'
Also there is an eal parameter around those APIs: '--force-max-simd-bitwidth'
I wonder these existing APIs can be utilized to select the vector path instead of adding device args to the PMD, can you please check?
Thanks,
ferruh
Re: [dpdk-dev] [PATCH v2 1/9] net/hns3: support runtime config to select IO burst func
Quoted 50 lines · Ferruh Yigit
Quoted 37 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>Quoted 9 lines
---
doc/guides/rel_notes/release_21_05.rst| 1 + drivers/net/hns3/hns3_ethdev.c | 74
++++++++++++++++++++++++++++++++++
drivers/net/hns3/hns3_ethdev.h | 12 ++++++ drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 54 ++++++++++++++++++-------5 files changed, 128 insertions(+), 14 deletions(-)Hi Connor,
Quoted 7 lines
There are two recently added APIs to enable user to select vector datapath:
'rte_vect_set_max_simd_bitwidth()' 'rte_vect_get_max_simd_bitwidth()'Also there is an eal parameter around those APIs: '--force-max-simd-bitwidth'
I wonder these existing APIs can be utilized to select the vector path instead of adding device args to the PMD, can you please check?
Hi, ferruh,
we will support the two methods to select IO patch. By the way,
the method of "simd bitwidth" will be supported in next patches, thanks.
Quoted 3 lines
Thanks,
ferruh
.
Re: [dpdk-dev] [PATCH v2 1/9] net/hns3: support runtime config to select IO burst func
In reply to Min Hu (Connor)Quoted 37 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>
<...>
drivers/net/hns3/hns3_ethdev.c hns3_get_module_info(struct rte_eth_dev *dev, · line 6569
Quoted 6 lines
drivers/net/hns3/hns3_ethdev.c +6
-0+ +rte_kvargs_process (kvlist,"rx_func_hint" , &hns3_parse_io_hint_func, + &rx_func_hint); +rte_kvargs_process (kvlist,"tx_func_hint" , &hns3_parse_io_hint_func, + &tx_func_hint); +rte_kvargs_free (kvlist);
If you will continue with the device argument method, those should be documented in the device documentation, you can have a section as "Runtime Config Options" and can detail new devargs there.
Also 'RTE_PMD_REGISTER_PARAM_STRING' should be added for new devargs.
Re: [dpdk-dev] [PATCH v2 1/9] net/hns3: support runtime config to select IO burst func
Quoted 48 lines · Ferruh Yigit
Quoted 37 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]><...>
Quoted 6 lines
+
+rte_kvargs_process(kvlist, "rx_func_hint", &hns3_parse_io_hint_func, + &rx_func_hint);
+rte_kvargs_process(kvlist, "tx_func_hint", &hns3_parse_io_hint_func, + &tx_func_hint);
+rte_kvargs_free(kvlist);
Quoted 4 lines
If you will continue with the device argument method, those should be documented in the device documentation, you can have a section as "Runtime Config Options" and can detail new devargs there.
Also '
RTE_PMD_REGISTER_PARAM_STRING' should be added for new devargs. .
ok, I will do it in V3, thanks.
PATCH v2 2/9 net/hns3: support Tx push quick doorbell to improve perf
In reply to Min Hu (Connor)From: Chengwen Feng <[email protected]>
Kunpeng 930 support Tx push mode which could improve performance, It works like below:
1. Add pcie bar45 which support driver direct write the Tx descriptor or tail reg to it.
2. Support three operations: a) direct write one Tx descriptor, b) direct write two Tx descriptors, c) direct write tail reg.
3. The original tail reg located at bar23, the above bar45 tail reg could provide better bandwidth from the hardware perspective.
The hns3 driver only support direct write tail reg (also have the name of quick doorbell), the detail:
1. Considering compatibility, firmware will report Tx push capa if the hardware support it.
2. Add control macro RTE_LIBRTE_HNS3_ENABLE_TX_PUSH which was not defined default.
3. If user define macro RTE_LIBRTE_HNS3_ENABLE_TX_PUSH and hardware support, then driver will direct write bar45 tail reg to inform the hardware.
Signed-off-by Chengwen Feng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 4 +- drivers/net/hns3/hns3_ethdev_vf.c | 4 +- drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++++++++- drivers/net/hns3/hns3_rxtx.h | 24 ++++++++++ drivers/net/hns3/hns3_rxtx_vec_neon.h | 2 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 2 +- 7 files changed, 116 insertions(+), 6 deletions(-)
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for Tx push qick doorbell to improve performance. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +3 -1
@@ -4886,6 +4886,8 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } +hns3_tx_push_init (eth_dev); +/* * To ensure that the hardware environment is clean during * initialization, the driver actively clear the hardware environment
@@ -6682,8 +6684,8 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) "process, ret = %d", ret); goto err_mp_init_secondary; } - hw->secondary_cnt++; +hns3_tx_push_init (eth_dev);return 0 ; }
drivers/net/hns3/hns3_ethdev_vf.c +3 -1
@@ -1841,6 +1841,8 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } +hns3_tx_push_init (eth_dev); +/* Get VF resource */ ret =hns3_query_vf_resource (hw);if (ret)
@@ -2818,8 +2820,8 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) "process, ret = %d", ret); goto err_mp_init_secondary; } - hw->secondary_cnt++; +hns3_tx_push_init (eth_dev);return 0 ; }
drivers/net/hns3/hns3_rxtx.c +83 -2
109 lines not on this page · raw message
drivers/net/hns3/hns3_rxtx.h +24 -0
@@ -406,6 +406,7 @@ struct hns3_tx_dfx_stats {struct hns3_tx_queue {void *io_base; +/* The io_tail_reg is write-only if working in tx push mode */ volatile void *io_tail_reg;struct hns3_adapter *hns;struct hns3_desc *tx_ring;
@@ -471,6 +472,7 @@ struct hns3_tx_queue {uint8_t max_non_tso_bd_num;/* max BD number of one non-TSO packet */ bool tx_deferred_start;/* don't start this queue in dev start */ +bool tx_push_enable;/* check whether the tx push is enabled */ bool configured;/* indicate if tx queue has been configured */ /* * Indicate whether add the vlan_tci of the mbuf to the inner VLAN field
@@ -638,6 +640,27 @@ hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info, ptype_tbl->l4table[l4id]; } +/* +* If enable using tx push feature and also device support it, then use qick +* doorbell (bar45) to inform the hardware. +* +* The other cases (such as: device don't support or user don't enable using) +* then use normal doorbell (bar23) to inform the hardware. +*/ +static inline void +hns3_write_txq_tail_reg (struct hns3_tx_queue *txq,uint32_t value) +{ +rte_io_wmb (); +#ifdef RTE_LIBRTE_HNS3_ENABLE_TX_PUSH +if (txq->tx_push_enable) +rte_write64_relaxed (rte_cpu_to_le_32 (value), txq->io_tail_reg); +else +rte_write32_relaxed (rte_cpu_to_le_32 (value), txq->io_tail_reg); +#else +rte_write32_relaxed (rte_cpu_to_le_32 (value), txq->io_tail_reg); +#endif +} +void hns3_dev_rx_queue_release (void *queue);void hns3_dev_tx_queue_release (void *queue);void hns3_free_all_queues (struct rte_eth_dev *dev);
@@ -718,5 +741,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev);void hns3_restore_tqp_enable_state (struct hns3_hw *hw);int hns3_tx_done_cleanup (void *txq,uint32_t free_cnt);void hns3_enable_rxd_adv_layout (struct hns3_hw *hw); +void hns3_tx_push_init (struct rte_eth_dev *dev);#endif /* _HNS3_RXTX_H_ */
drivers/net/hns3/hns3_rxtx_vec_neon.h +1 -1
@@ -84,7 +84,7 @@ hns3_xmit_fixed_burst_vec(void *__restrict tx_queue, txq->next_to_use = next_to_use; txq->tx_bd_ready -= nb_tx; -hns3_write_reg_opt (txq->io_tail_reg, nb_tx); +hns3_write_txq_tail_reg (txq, nb_tx);return nb_tx; }
drivers/net/hns3/hns3_rxtx_vec_sve.c +1 -1
@@ -452,7 +452,7 @@ hns3_xmit_fixed_burst_vec_sve(void *__restrict tx_queue, txq->next_to_use += nb_pkts - nb_tx; txq->tx_bd_ready -= nb_pkts; -hns3_write_reg_opt (txq->io_tail_reg, nb_pkts); +hns3_write_txq_tail_reg (txq, nb_pkts);return nb_pkts; }
Signature · 1 line
2.7.4
Re: [dpdk-dev] [PATCH v2 2/9] net/hns3: support Tx push quick doorbell to improve perf
Quoted 11 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Kunpeng 930 support Tx push mode which could improve performance, It works like below:
1. Add pcie bar45 which support driver direct write the Tx descriptor or tail reg to it.
2. Support three operations: a) direct write one Tx descriptor, b) direct write two Tx descriptors, c) direct write tail reg.
3. The original tail reg located at bar23, the above bar45 tail reg could provide better bandwidth from the hardware perspective.
Quoted 9 lines
The hns3 driver only support direct write tail reg (also have the name of quick doorbell), the detail:
1. Considering compatibility, firmware will report Tx push capa if the hardware support it.
2. Add control macroRTE_LIBRTE_HNS3_ENABLE_TX_PUSHwhich was not defined default.
3. If user define macroRTE_LIBRTE_HNS3_ENABLE_TX_PUSHand hardware support, then driver will direct write bar45 tail reg to inform the hardware.
Can you convert the copile time 'RTE_LIBRTE_HNS3_ENABLE_TX_PUSH' flag to runtime device argument?
There is already 'tx_push_enable' variable check on datapath, so converting to devarg shouldn't add any additional checks and shouldn't have performance impact.
Quoted 3 lines
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>
<...>
Re: [dpdk-dev] [PATCH v2 2/9] net/hns3: support Tx push quick doorbell to improve perf
Quoted 22 lines · Ferruh Yigit
Quoted 11 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Kunpeng 930 support Tx push mode which could improve performance, It works like below:
1. Add pcie bar45 which support driver direct write the Tx descriptor or tail reg to it.
2. Support three operations: a) direct write one Tx descriptor, b) direct write two Tx descriptors, c) direct write tail reg.
3. The original tail reg located at bar23, the above bar45 tail reg could provide better bandwidth from the hardware perspective.Quoted 9 lines
The hns3 driver only support direct write tail reg (also have the name of quick doorbell), the detail:
1. Considering compatibility, firmware will report Tx push capa if the hardware support it.
2. Add control macroRTE_LIBRTE_HNS3_ENABLE_TX_PUSHwhich was not defined default.
3. If user define macroRTE_LIBRTE_HNS3_ENABLE_TX_PUSHand hardware support, then driver will direct write bar45 tail reg to inform the hardware.
Quoted 4 lines
Can you convert the copile time '
RTE_LIBRTE_HNS3_ENABLE_TX_PUSH' flag to runtime device argument?There is already '
tx_push_enable' variable check on datapath, so converting to devarg shouldn't add any additional checks and shouldn't have performance impact.
After much thought, We choose to take the patch down from this patch set, because we want to take more test for this patch in new platform.
we will send the patch again in future.
thanks
Quoted 6 lines
Quoted 3 lines
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]><...>
.
PATCH v2 3/9 net/hns3: support for outer UDP cksum
In reply to Min Hu (Connor)From: Chengchang Tang <[email protected]>
Kunpeng930 support outer UDP cksum, this patch add support for it.
Signed-off-by Chengchang Tang <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-)
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for Tx push qick doorbell to improve performance. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_cmd.c +3 -0
@@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw,if (hns3_get_bit (caps,HNS3_CAPS_RXD_ADV_LAYOUT_B ))hns3_set_bit (hw->capability,HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B ,1 ); +if (hns3_get_bit (caps,HNS3_CAPS_UDP_TUNNEL_CSUM_B )) +hns3_set_bit (hw->capability, +HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B ,1 ); } static uint32_t
drivers/net/hns3/hns3_ethdev.c +3 -0
@@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); +if (hns3_dev_outer_udp_cksum_supported (hw)) + info->tx_offload_capa |=DEV_TX_OFFLOAD_OUTER_UDP_CKSUM ; +if (hns3_dev_indep_txrx_supported (hw)) info->dev_capa =RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP ;
drivers/net/hns3/hns3_ethdev.h +4 -0
@@ -795,6 +795,7 @@ enum {#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6#define HNS3_DEV_SUPPORT_STASH_B 0x7#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA#define hns3_dev_dcb_supported (hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
@@ -828,6 +829,9 @@ enum {#define hns3_dev_rxd_adv_layout_supported (hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported (hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) +#define HNS3_DEV_PRIVATE_TO_HW (adapter) \ (&((struct hns3_adapter *)adapter)->hw)#define HNS3_DEV_PRIVATE_TO_PF (adapter) \
drivers/net/hns3/hns3_ethdev_vf.c +3 -0
@@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); +if (hns3_dev_outer_udp_cksum_supported (hw)) + info->tx_offload_capa |=DEV_TX_OFFLOAD_OUTER_UDP_CKSUM ; +if (hns3_dev_indep_txrx_supported (hw)) info->dev_capa =RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP ;
drivers/net/hns3/hns3_rxtx.c +69 -16
149 lines not on this page · raw message
drivers/net/hns3/hns3_rxtx.h +3 -1
@@ -149,6 +149,7 @@#define HNS3_TXD_MSS_S 0#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22#define HNS3_L2_LEN_UNIT 1UL#define HNS3_L3_LEN_UNIT 2UL#define HNS3_L4_LEN_UNIT 2UL
@@ -234,7 +235,7 @@ struct hns3_desc { }; }; -uint32_t paylen; +uint32_t paylen_fd_dop_ol4cs;uint16_t tp_fe_sc_vld_ra_ri;uint16_t mss; } tx;
@@ -505,6 +506,7 @@ struct hns3_queue_info { };#define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \
drivers/net/hns3/hns3_rxtx_vec_sve.c +3 -2
@@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0));/* save offset 24~31byte of every BD */ -svst1_scatter_u64offset_u64 (pg, (uint64_t *)&txdp->tx.paylen, - offsets,svdup_n_u64 (valid_bit)); +svst1_scatter_u64offset_u64 (pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets,svdup_n_u64 (valid_bit));/* Increment bytes counter */ uint32_t idx;
Signature · 1 line
2.7.4
PATCH v2 4/9 net/hns3: adjust the format of RAS related structures
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function.
The correspond warnings of reviewbot_c:
When struct and union members are initialized, each member is initialized on a separate line.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-)
drivers/net/hns3/hns3_intr.c +1224 -902
@@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { };static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk =BIT (0 ), - .msg ="egu_cge_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (1 ), - .msg ="egu_cge_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="egu_lge_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (3 ), - .msg ="egu_lge_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="cge_igu_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="cge_igu_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="lge_igu_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="lge_igu_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="cge_igu_afifo_overflow_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="lge_igu_afifo_overflow_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="egu_cge_afifo_underrun_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="egu_lge_afifo_underrun_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="egu_ge_afifo_underrun_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="ge_igu_afifo_overflow_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="egu_cge_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (1 ), + .msg ="egu_cge_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="egu_lge_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (3 ), + .msg ="egu_lge_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="cge_igu_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="cge_igu_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="lge_igu_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="lge_igu_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="cge_igu_afifo_overflow_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="lge_igu_afifo_overflow_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="egu_cge_afifo_underrun_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="egu_lge_afifo_underrun_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="egu_ge_afifo_underrun_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="ge_igu_afifo_overflow_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk =0xFFFFFFFF , - .msg ="rpu_rx_pkt_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =0xFFFFFFFF , + .msg ="rpu_rx_pkt_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk =BIT (13 ), - .msg ="rpu_rx_pkt_bit32_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="rpu_rx_pkt_bit33_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="rpu_rx_pkt_bit34_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="rpu_rx_pkt_bit35_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="rcb_tx_ring_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="rcb_rx_ring_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="rcb_tx_fbd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="rcb_rx_ebd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="rcb_tso_info_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="rcb_tx_int_info_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="rcb_rx_int_info_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (24 ), - .msg ="tpu_tx_pkt_0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (25 ), - .msg ="tpu_tx_pkt_1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (26 ), - .msg ="rd_bus_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (27 ), - .msg ="wr_bus_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (30 ), - .msg ="ooo_ecc_err_detect" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (31 ), - .msg ="ooo_ecc_err_multpl" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (13 ), + .msg ="rpu_rx_pkt_bit32_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="rpu_rx_pkt_bit33_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="rpu_rx_pkt_bit34_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="rpu_rx_pkt_bit35_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="rcb_tx_ring_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="rcb_rx_ring_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="rcb_tx_fbd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="rcb_rx_ebd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="rcb_tso_info_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="rcb_tx_int_info_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="rcb_rx_int_info_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (24 ), + .msg ="tpu_tx_pkt_0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (25 ), + .msg ="tpu_tx_pkt_1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (26 ), + .msg ="rd_bus_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (27 ), + .msg ="wr_bus_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (30 ), + .msg ="ooo_ecc_err_detect" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (31 ), + .msg ="ooo_ecc_err_multpl" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk =BIT (29 ), - .msg ="rx_q_search_miss" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (29 ), + .msg ="rx_q_search_miss" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk =BIT (0 ), - .msg ="roc_pkt_without_key_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="low_water_line_err_port" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="roc_pkt_without_key_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="low_water_line_err_port" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk =BIT (0 ), - .msg ="tx_vlan_tag_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (1 ), - .msg ="rss_list_tc_unassigned_queue_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="tx_vlan_tag_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (1 ), + .msg ="rss_list_tc_unassigned_queue_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk =BIT (3 ), - .msg ="tx_rd_fbd_poison" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =BIT (4 ), - .msg ="rx_rd_ebd_poison" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (3 ), + .msg ="tx_rd_fbd_poison" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =BIT (4 ), + .msg ="rx_rd_ebd_poison" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk =BIT (0 ), - .msg ="over_8bd_no_fe" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =BIT (1 ), - .msg ="tso_mss_cmp_min_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (2 ), - .msg ="tso_mss_cmp_max_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="buf_wait_timeout" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="over_8bd_no_fe" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =BIT (1 ), + .msg ="tso_mss_cmp_min_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (2 ), + .msg ="tso_mss_cmp_max_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="buf_wait_timeout" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="imp_itcm0_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (3 ), - .msg ="imp_itcm1_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="imp_itcm2_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="imp_itcm3_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (9 ), - .msg ="imp_dtcm0_mem0_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (11 ), - .msg ="imp_dtcm0_mem1_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (13 ), - .msg ="imp_dtcm1_mem0_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (15 ), - .msg ="imp_dtcm1_mem1_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (17 ), - .msg ="imp_itcm4_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="imp_itcm0_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (3 ), + .msg ="imp_itcm1_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="imp_itcm2_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="imp_itcm3_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (9 ), + .msg ="imp_dtcm0_mem0_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (11 ), + .msg ="imp_dtcm0_mem1_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (13 ), + .msg ="imp_dtcm1_mem0_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (15 ), + .msg ="imp_dtcm1_mem1_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (17 ), + .msg ="imp_itcm4_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="cmdq_nic_rx_depth_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (3 ), - .msg ="cmdq_nic_tx_depth_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="cmdq_nic_rx_tail_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="cmdq_nic_tx_tail_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (9 ), - .msg ="cmdq_nic_rx_head_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (11 ), - .msg ="cmdq_nic_tx_head_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (13 ), - .msg ="cmdq_nic_rx_addr_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (15 ), - .msg ="cmdq_nic_tx_addr_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="cmdq_nic_rx_depth_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (3 ), + .msg ="cmdq_nic_tx_depth_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="cmdq_nic_rx_tail_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="cmdq_nic_tx_tail_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (9 ), + .msg ="cmdq_nic_rx_head_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (11 ), + .msg ="cmdq_nic_tx_head_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (13 ), + .msg ="cmdq_nic_rx_addr_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (15 ), + .msg ="cmdq_nic_tx_addr_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk =BIT (6 ), - .msg ="tqp_int_cfg_even_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="tqp_int_cfg_odd_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (8 ), - .msg ="tqp_int_ctrl_even_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (9 ), - .msg ="tqp_int_ctrl_odd_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (10 ), - .msg ="tx_queue_scan_int_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (11 ), - .msg ="rx_queue_scan_int_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (6 ), + .msg ="tqp_int_cfg_even_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tqp_int_cfg_odd_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (8 ), + .msg ="tqp_int_ctrl_even_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (9 ), + .msg ="tqp_int_ctrl_odd_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (10 ), + .msg ="tx_que_scan_int_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (11 ), + .msg ="rx_que_scan_int_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk =BIT (0 ), - .msg ="imp_rd_poison_int" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="imp_rd_poison_int" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };#define HNS3_SSU_MEM_ECC_ERR (x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +}static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {HNS3_SSU_MEM_ECC_ERR (0 ),
@@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { };static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk =BIT (0 ), - .msg ="ssu_mem32_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="ssu_mem32_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk =BIT (0 ), - .msg ="buf_sum_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (1 ), - .msg ="ppp_mb_num_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (2 ), - .msg ="ppp_mbid_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="ppp_rlt_mac_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="ppp_rlt_host_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="cks_edit_position_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="cks_edit_condition_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="vlan_edit_condition_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="vlan_num_ot_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="vlan_num_in_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="buf_sum_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (1 ), + .msg ="ppp_mb_num_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (2 ), + .msg ="ppp_mbid_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="ppp_rlt_mac_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="ppp_rlt_host_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="cks_edit_position_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="cks_edit_condition_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="vlan_edit_condition_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="vlan_num_ot_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="vlan_num_in_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error igu_int[] = { - { .int_msk =BIT (0 ), - .msg ="igu_rx_buf0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="igu_rx_buf1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="igu_rx_buf0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="igu_rx_buf1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="msix_nic_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="msix_nic_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk =BIT (0 ), - .msg ="vf_vlan_ad_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="umv_mcast_group_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="umv_key_mem0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="umv_key_mem1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="umv_key_mem2_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="umv_key_mem3_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="umv_ad_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="rss_tc_mode_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="rss_idt_mem0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="rss_idt_mem1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="rss_idt_mem2_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="rss_idt_mem3_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="rss_idt_mem4_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="rss_idt_mem5_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="rss_idt_mem6_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="rss_idt_mem7_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="rss_idt_mem8_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="rss_idt_mem9_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="rss_idt_mem10_ecc_m1bit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="rss_idt_mem11_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="rss_idt_mem12_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="rss_idt_mem13_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="rss_idt_mem14_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="rss_idt_mem15_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (24 ), - .msg ="port_vlan_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (25 ), - .msg ="mcast_linear_table_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (26 ), - .msg ="mcast_result_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (27 ), - .msg ="flow_director_ad_mem0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (28 ), - .msg ="flow_director_ad_mem1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (29 ), - .msg ="rx_vlan_tag_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (30 ), - .msg ="Tx_UP_mapping_config_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="vf_vlan_ad_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="umv_mcast_group_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="umv_key_mem0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="umv_key_mem1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="umv_key_mem2_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="umv_key_mem3_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="umv_ad_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="rss_tc_mode_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="rss_idt_mem0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="rss_idt_mem1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="rss_idt_mem2_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="rss_idt_mem3_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="rss_idt_mem4_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="rss_idt_mem5_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="rss_idt_mem6_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="rss_idt_mem7_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="rss_idt_mem8_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="rss_idt_mem9_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="rss_idt_mem10_ecc_m1bit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="rss_idt_mem11_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="rss_idt_mem12_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="rss_idt_mem13_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="rss_idt_mem14_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="rss_idt_mem15_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (24 ), + .msg ="port_vlan_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (25 ), + .msg ="mcast_linear_table_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (26 ), + .msg ="mcast_result_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (27 ), + .msg ="flow_director_ad_mem0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (28 ), + .msg ="flow_director_ad_mem1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (29 ), + .msg ="rx_vlan_tag_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (30 ), + .msg ="Tx_UP_mapping_config_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk =BIT (0 ), - .msg ="hfs_fifo_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="rslt_descr_fifo_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="tx_vlan_tag_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="FD_CN0_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="FD_CN1_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="GRO_AD_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="hfs_fifo_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="rslt_descr_fifo_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="tx_vlan_tag_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="FD_CN0_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="FD_CN1_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="GRO_AD_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk =BIT (4 ), - .msg ="gro_bd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="gro_context_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="rx_stash_cfg_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="axi_rd_fbd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (4 ), + .msg ="gro_bd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="gro_context_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="rx_stash_cfg_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="axi_rd_fbd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk =BIT (1 ), - .msg ="tm_sch_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="tm_sch_port_shap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="tm_sch_port_shap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="tm_sch_pg_pshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="tm_sch_pg_pshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="tm_sch_pg_cshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="tm_sch_pg_cshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="tm_sch_pri_pshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="tm_sch_pri_pshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="tm_sch_pri_cshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="tm_sch_pri_cshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="tm_sch_port_shap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="tm_sch_port_shap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="tm_sch_pg_pshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="tm_sch_pg_pshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="tm_sch_pg_cshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="tm_sch_pg_cshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="tm_sch_pri_pshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="tm_sch_pri_pshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="tm_sch_pri_cshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="tm_sch_pri_cshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="tm_sch_rq_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="tm_sch_rq_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (24 ), - .msg ="tm_sch_nq_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (25 ), - .msg ="tm_sch_nq_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (26 ), - .msg ="tm_sch_roce_up_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (27 ), - .msg ="tm_sch_roce_up_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (28 ), - .msg ="tm_sch_rcb_byte_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (29 ), - .msg ="tm_sch_rcb_byte_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (30 ), - .msg ="tm_sch_ssu_byte_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (31 ), - .msg ="tm_sch_ssu_byte_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="tm_sch_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="tm_sch_port_shap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="tm_sch_port_shap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="tm_sch_pg_pshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="tm_sch_pg_pshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="tm_sch_pg_cshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tm_sch_pg_cshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="tm_sch_pri_pshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="tm_sch_pri_pshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="tm_sch_pri_cshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="tm_sch_pri_cshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="tm_sch_port_shap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="tm_sch_port_shap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="tm_sch_pg_pshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="tm_sch_pg_pshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="tm_sch_pg_cshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="tm_sch_pg_cshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="tm_sch_pri_pshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="tm_sch_pri_pshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="tm_sch_pri_cshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="tm_sch_pri_cshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="tm_sch_rq_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="tm_sch_rq_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (24 ), + .msg ="tm_sch_nq_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (25 ), + .msg ="tm_sch_nq_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (26 ), + .msg ="tm_sch_roce_up_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (27 ), + .msg ="tm_sch_roce_up_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (28 ), + .msg ="tm_sch_rcb_byte_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (29 ), + .msg ="tm_sch_rcb_byte_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (30 ), + .msg ="tm_sch_ssu_byte_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (31 ), + .msg ="tm_sch_ssu_byte_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk =BIT (0 ), - .msg ="qcn_shap_gp0_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="qcn_shap_gp0_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="qcn_shap_gp1_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="qcn_shap_gp1_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="qcn_shap_gp2_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="qcn_shap_gp2_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="qcn_shap_gp3_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="qcn_shap_gp3_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="qcn_shap_gp0_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="qcn_shap_gp0_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="qcn_shap_gp1_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="qcn_shap_gp1_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="qcn_shap_gp2_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="qcn_shap_gp2_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="qcn_shap_gp3_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="qcn_shap_gp3_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="qcn_byte_info_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="qcn_byte_info_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="qcn_shap_gp0_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="qcn_shap_gp0_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="qcn_shap_gp1_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="qcn_shap_gp1_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="qcn_shap_gp2_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="qcn_shap_gp2_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="qcn_shap_gp3_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="qcn_shap_gp3_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="qcn_shap_gp0_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="qcn_shap_gp0_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="qcn_shap_gp1_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="qcn_shap_gp1_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="qcn_shap_gp2_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="qcn_shap_gp2_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="qcn_shap_gp3_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="qcn_shap_gp3_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="qcn_byte_info_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="qcn_byte_info_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="qcn_byte_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="qcn_time_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="qcn_fb_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="qcn_link_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="qcn_rate_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="qcn_tmplt_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="qcn_shap_cfg_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="qcn_gp0_barrel_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="qcn_gp1_barrel_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="qcn_gp2_barrel_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="qcn_gp3_barral_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="qcn_byte_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="qcn_time_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="qcn_fb_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="qcn_link_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="qcn_rate_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="qcn_tmplt_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="qcn_shap_cfg_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="qcn_gp0_barrel_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="qcn_gp1_barrel_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="qcn_gp2_barrel_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="qcn_gp3_barral_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="ncsi_tx_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="ncsi_tx_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk =BIT (0 ), - .msg ="ig_mac_inf_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="ig_host_inf_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="ig_roc_buf_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="ig_host_data_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="ig_host_key_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="tx_qcn_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="rx_qcn_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="tx_pf_rd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="rx_pf_rd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="qm_eof_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="mb_rlt_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="dup_uncopy_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="dup_cnt_rd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="dup_cnt_drop_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="dup_cnt_wrb_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="host_cmd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="mac_cmd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="host_cmd_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="mac_cmd_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="dup_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="out_queue_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="bank2_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="bank1_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="bank0_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="ig_mac_inf_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="ig_host_inf_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="ig_roc_buf_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="ig_host_data_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="ig_host_key_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="tx_qcn_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="rx_qcn_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tx_pf_rd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="rx_pf_rd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="qm_eof_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="mb_rlt_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="dup_uncopy_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="dup_cnt_rd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="dup_cnt_drop_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="dup_cnt_wrb_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="host_cmd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="mac_cmd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="host_cmd_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="mac_cmd_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="dup_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="out_queue_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="bank2_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="bank1_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="bank0_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk =BIT (0 ), - .msg ="ets_rd_int_rx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="ets_wr_int_rx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="ets_rd_int_tx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="ets_wr_int_tx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="ets_rd_int_rx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="ets_wr_int_rx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="ets_rd_int_tx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="ets_wr_int_tx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk =BIT (0 ), - .msg ="rx_buf_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="rx_stp_fifo_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="rx_stp_fifo_underflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="tx_buf_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="tx_buf_underrun" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="rx_stp_buf_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="rx_buf_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="rx_stp_fifo_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="rx_stp_fifo_underflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="tx_buf_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="tx_buf_underrun" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="rx_stp_buf_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk =BIT (0 ), - .msg ="roc_pkt_without_key_port" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =BIT (1 ), - .msg ="tpu_pkt_without_key_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="igu_pkt_without_key_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="roc_eof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="tpu_eof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="igu_eof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="roc_sof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="tpu_sof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="igu_sof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="ets_rd_int_rx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="ets_wr_int_rx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="ets_rd_int_tx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="ets_wr_int_tx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="roc_pkt_without_key_port" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =BIT (1 ), + .msg ="tpu_pkt_without_key_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="igu_pkt_without_key_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="roc_eof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="tpu_eof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="igu_eof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="roc_sof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tpu_sof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="igu_sof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="ets_rd_int_rx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="ets_wr_int_rx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="ets_rd_int_tx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="ets_wr_int_tx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset =0 , - .data_offset =0 , - .msg ="IMP_TCM_ECC_INT_STS" , - .hw_err = imp_tcm_ecc_int }, - { .desc_offset =0 , - .data_offset =1 , - .msg ="CMDQ_MEM_ECC_INT_STS" , - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset =0 , - .data_offset =2 , - .msg ="IMP_RD_POISON_INT_STS" , - .hw_err = imp_rd_poison_int }, - { .desc_offset =0 , - .data_offset =3 , - .msg ="TQP_INT_ECC_INT_STS" , - .hw_err = tqp_int_ecc_int }, - { .desc_offset =0 , - .data_offset =4 , - .msg ="MSIX_ECC_INT_STS" , - .hw_err = msix_ecc_int }, - { .desc_offset =2 , - .data_offset =2 , - .msg ="SSU_ECC_MULTI_BIT_INT_0" , - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset =2 , - .data_offset =3 , - .msg ="SSU_ECC_MULTI_BIT_INT_1" , - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset =2 , - .data_offset =4 , - .msg ="SSU_COMMON_ERR_INT" , - .hw_err = ssu_common_ecc_int }, - { .desc_offset =3 , - .data_offset =0 , - .msg ="IGU_INT_STS" , - .hw_err = igu_int }, - { .desc_offset =4 , - .data_offset =1 , - .msg ="PPP_MPF_ABNORMAL_INT_ST1" , - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset =4 , - .data_offset =3 , - .msg ="PPP_MPF_ABNORMAL_INT_ST3" , - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset =5 , - .data_offset =1 , - .msg ="PPU_MPF_ABNORMAL_INT_ST1" , - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset =5 , - .data_offset =2 , - .msg ="PPU_MPF_ABNORMAL_INT_ST2_RAS" , - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset =5 , - .data_offset =3 , - .msg ="PPU_MPF_ABNORMAL_INT_ST3" , - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset =6 , - .data_offset =0 , - .msg ="TM_SCH_RINT" , - .hw_err = tm_sch_int }, - { .desc_offset =7 , - .data_offset =0 , - .msg ="QCN_FIFO_RINT" , - .hw_err = qcn_fifo_int }, - { .desc_offset =7 , - .data_offset =1 , - .msg ="QCN_ECC_RINT" , - .hw_err = qcn_ecc_int }, - { .desc_offset =9 , - .data_offset =0 , - .msg ="NCSI_ECC_INT_RPT" , - .hw_err = ncsi_ecc_int }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =0 , + .data_offset =0 , + .msg ="IMP_TCM_ECC_INT_STS" , + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset =0 , + .data_offset =1 , + .msg ="CMDQ_MEM_ECC_INT_STS" , + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset =0 , + .data_offset =2 , + .msg ="IMP_RD_POISON_INT_STS" , + .hw_err = imp_rd_poison_int + }, { + .desc_offset =0 , + .data_offset =3 , + .msg ="TQP_INT_ECC_INT_STS" , + .hw_err = tqp_int_ecc_int + }, { + .desc_offset =0 , + .data_offset =4 , + .msg ="MSIX_ECC_INT_STS" , + .hw_err = msix_ecc_int + }, { + .desc_offset =2 , + .data_offset =2 , + .msg ="SSU_ECC_MULTI_BIT_INT_0" , + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset =2 , + .data_offset =3 , + .msg ="SSU_ECC_MULTI_BIT_INT_1" , + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset =2 , + .data_offset =4 , + .msg ="SSU_COMMON_ERR_INT" , + .hw_err = ssu_common_ecc_int + }, { + .desc_offset =3 , + .data_offset =0 , + .msg ="IGU_INT_STS" , + .hw_err = igu_int + }, { + .desc_offset =4 , + .data_offset =1 , + .msg ="PPP_MPF_ABNORMAL_INT_ST1" , + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset =4 , + .data_offset =3 , + .msg ="PPP_MPF_ABNORMAL_INT_ST3" , + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset =5 , + .data_offset =1 , + .msg ="PPU_MPF_ABNORMAL_INT_ST1" , + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset =5 , + .data_offset =2 , + .msg ="PPU_MPF_ABNORMAL_INT_ST2_RAS" , + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset =5 , + .data_offset =3 , + .msg ="PPU_MPF_ABNORMAL_INT_ST3" , + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset =6 , + .data_offset =0 , + .msg ="TM_SCH_RINT" , + .hw_err = tm_sch_int + }, { + .desc_offset =7 , + .data_offset =0 , + .msg ="QCN_FIFO_RINT" , + .hw_err = qcn_fifo_int + }, { + .desc_offset =7 , + .data_offset =1 , + .msg ="QCN_ECC_RINT" , + .hw_err = qcn_ecc_int + }, { + .desc_offset =9 , + .data_offset =0 , + .msg ="NCSI_ECC_INT_RPT" , + .hw_err = ncsi_ecc_int + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset =0 , - .data_offset =0 , - .msg ="SSU_PORT_BASED_ERR_INT_RAS" , - .hw_err = ssu_port_based_err_int }, - { .desc_offset =0 , - .data_offset =1 , - .msg ="SSU_FIFO_OVERFLOW_INT" , - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset =0 , - .data_offset =2 , - .msg ="SSU_ETS_TCG_INT" , - .hw_err = ssu_ets_tcg_int }, - { .desc_offset =1 , - .data_offset =0 , - .msg ="IGU_EGU_TNL_INT_STS" , - .hw_err = igu_egu_tnl_int }, - { .desc_offset =3 , - .data_offset =0 , - .msg ="PPU_PF_ABNORMAL_INT_ST_RAS" , - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =0 , + .data_offset =0 , + .msg ="SSU_PORT_BASED_ERR_INT_RAS" , + .hw_err = ssu_port_based_err_int + }, { + .desc_offset =0 , + .data_offset =1 , + .msg ="SSU_FIFO_OVERFLOW_INT" , + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset =0 , + .data_offset =2 , + .msg ="SSU_ETS_TCG_INT" , + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset =1 , + .data_offset =0 , + .msg ="IGU_EGU_TNL_INT_STS" , + .hw_err = igu_egu_tnl_int + }, { + .desc_offset =3 , + .data_offset =0 , + .msg ="PPU_PF_ABNORMAL_INT_ST_RAS" , + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset =1 , - .data_offset =0 , - .msg ="MAC_AFIFO_TNL_INT_R" , - .hw_err = mac_afifo_tnl_int }, - { .desc_offset =5 , - .data_offset =2 , - .msg ="PPU_MPF_ABNORMAL_INT_ST2_MSIX" , - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =1 , + .data_offset =0 , + .msg ="MAC_AFIFO_TNL_INT_R" , + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset =5 , + .data_offset =2 , + .msg ="PPU_MPF_ABNORMAL_INT_ST2_MSIX" , + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset =0 , - .data_offset =0 , - .msg ="SSU_PORT_BASED_ERR_INT_MSIX" , - .hw_err = ssu_port_based_pf_int }, - { .desc_offset =2 , - .data_offset =0 , - .msg ="PPP_PF_ABNORMAL_INT_ST0" , - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset =3 , - .data_offset =0 , - .msg ="PPU_PF_ABNORMAL_INT_ST_MSIX" , - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =0 , + .data_offset =0 , + .msg ="SSU_PORT_BASED_ERR_INT_MSIX" , + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset =2 , + .data_offset =0 , + .msg ="PPP_PF_ABNORMAL_INT_ST0" , + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset =3 , + .data_offset =0 , + .msg ="PPU_PF_ABNORMAL_INT_ST_MSIX" , + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };enum hns3_hw_err_type {
Signature · 1 line
2.7.4
Re: [dpdk-dev] [PATCH v2 4/9] net/hns3: adjust the format of RAS related structures
Quoted 12 lines · Min Hu (Connor)
From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function.
The correspond warnings of
reviewbot_c:
When struct and union members are initialized, each member is initialized on a separate line.Signed-off-by Hongbo Zheng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>
<...>
Quoted 7 lines
static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = {drivers/net/hns3/hns3_intr.c +0
-6- { .int_msk = 0xFFFFFFFF, - .msg = "rpu_rx_pkt_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET}
drivers/net/hns3/hns3_intr.c static const char *reset_string[HNS3_MAX_RESET] = { · line 104
Quoted 10 lines
drivers/net/hns3/hns3_intr.c +9
-0+ { + .int_msk = 0xFFFFFFFF, + .msg = "rpu_rx_pkt_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } };
Hi Connor,
This looks like just a syntax change, I wonder what is mentioned 'reviewbot_c' that generates a warning?
Re: [dpdk-dev] [PATCH v2 4/9] net/hns3: adjust the format of RAS related structures
Quoted 34 lines · Ferruh Yigit
Quoted 12 lines · Min Hu (Connor)
From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function.
The correspond warnings of
reviewbot_c:
When struct and union members are initialized, each member is initialized on a separate line.Signed-off-by Hongbo Zheng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]><...>
Quoted 9 lines
static const struct
hns3_hw_errorppu_mpf_abnormal_int_st1[] = { - { .int_msk =0xFFFFFFFF,
- .msg = "rpu_rx_pkt_ecc_mbit_err",
- .reset_level =HNS3_GLOBAL_RESET},
- { .int_msk = 0,
- .msg = NULL,
- .reset_level =HNS3_NONE_RESET}
+ {
+ .int_msk =0xFFFFFFFF,Quoted 8 lines
+ .msg = "
rpu_rx_pkt_ecc_mbit_err",
+ .reset_level =HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level =HNS3_NONE_RESET
+ }
};
Quoted 4 lines
Hi Connor,
This looks like just a syntax change, I wonder what is mentioned '
reviewbot_c' that generates a warning?
Hi, Ferruh, the description of 'reviewbot_c' may be misleading, actually, it means "Huawei General Coding Specification". code from Our company should follow that, thanks
Quoted 2 lines
.
Re: [dpdk-dev] [PATCH v2 4/9] net/hns3: adjust the format of RAS related structures
Quoted 37 lines · Min Hu (Connor)
Quoted 34 lines · Ferruh Yigit
Quoted 12 lines · Min Hu (Connor)
From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function.
The correspond warnings of
reviewbot_c:
When struct and union members are initialized, each member is initialized on a separate line.Signed-off-by Hongbo Zheng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]><...>
Quoted 17 lines
static const struct
hns3_hw_errorppu_mpf_abnormal_int_st1[] = { - { .int_msk =0xFFFFFFFF,
- .msg = "rpu_rx_pkt_ecc_mbit_err",
- .reset_level =HNS3_GLOBAL_RESET},
- { .int_msk = 0,
- .msg = NULL,
- .reset_level =HNS3_NONE_RESET}
+ {
+ .int_msk =0xFFFFFFFF,
+ .msg = "rpu_rx_pkt_ecc_mbit_err",
+ .reset_level =HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level =HNS3_NONE_RESET
+ }
};
Quoted 7 lines
Quoted 4 lines
Hi Connor,
This looks like just a syntax change, I wonder what is mentioned '
reviewbot_c' that generates a warning?Hi, Ferruh, the description of '
reviewbot_c' may be misleading, actually, it means "Huawei General Coding Specification". code from Our company should follow that, thanks
Got it, you can remove the reference it if it is not publicly accessible, otherwise it doesn't add any values and it may be confusing.
Re: [dpdk-dev] [PATCH v2 4/9] net/hns3: adjust the format of RAS related structures
Quoted 40 lines · Ferruh Yigit
Quoted 39 lines · Min Hu (Connor)
Quoted 36 lines · Ferruh Yigit
Quoted 12 lines · Min Hu (Connor)
From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function.
The correspond warnings of
reviewbot_c:
When struct and union members are initialized, each member is initialized on a separate line.Signed-off-by Hongbo Zheng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]><...>
Quoted 9 lines
static const struct
hns3_hw_errorppu_mpf_abnormal_int_st1[] = { - { .int_msk =0xFFFFFFFF,
- .msg = "rpu_rx_pkt_ecc_mbit_err",
- .reset_level =HNS3_GLOBAL_RESET},
- { .int_msk = 0,
- .msg = NULL,
- .reset_level =HNS3_NONE_RESET}
+ {
+ .int_msk =0xFFFFFFFF,Quoted 8 lines
+ .msg = "
rpu_rx_pkt_ecc_mbit_err",
+ .reset_level =HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level =HNS3_NONE_RESET
+ }
};Hi Connor,
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
This looks like just a syntax change, I wonder what is mentioned '
reviewbot_c' that generates a warning?Hi, Ferruh, the description of '
reviewbot_c' may be misleading, actually, it means "Huawei General Coding Specification". code from Our company should follow that, thanksGot it, you can remove the reference it if it is not publicly accessible, otherwise it doesn't add any values and it may be confusing.
OK , I will fix it in V3, thanks.
Quoted 1 line
.
Re: [dpdk-dev] [PATCH v2 4/9] net/hns3: adjust the format of RAS related structures
Hi, Ferruh and all,
I have already sent V3 for this set of patches. Do you have any other
advice?
Quoted 54 lines · Min Hu (Connor)
Quoted 40 lines · Ferruh Yigit
Quoted 39 lines · Min Hu (Connor)
Quoted 36 lines · Ferruh Yigit
Quoted 12 lines · Min Hu (Connor)
From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function.
The correspond warnings of
reviewbot_c:
When struct and union members are initialized, each member is initialized on a separate line.Signed-off-by Hongbo Zheng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]><...>
Quoted 9 lines
static const struct
hns3_hw_errorppu_mpf_abnormal_int_st1[] = { - { .int_msk =0xFFFFFFFF,
- .msg = "rpu_rx_pkt_ecc_mbit_err",
- .reset_level =HNS3_GLOBAL_RESET},
- { .int_msk = 0,
- .msg = NULL,
- .reset_level =HNS3_NONE_RESET}
+ {
+ .int_msk =0xFFFFFFFF,Quoted 8 lines
+ .msg = "
rpu_rx_pkt_ecc_mbit_err",
+ .reset_level =HNS3_GLOBAL_RESET
+ }, {
+ .int_msk = 0,
+ .msg = NULL,
+ .reset_level =HNS3_NONE_RESET
+ }
};Hi Connor,
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
This looks like just a syntax change, I wonder what is mentioned '
reviewbot_c' that generates a warning?Hi, Ferruh, the description of '
reviewbot_c' may be misleading, actually, it means "Huawei General Coding Specification". code from Our company should follow that, thanksGot it, you can remove the reference it if it is not publicly accessible, otherwise it doesn't add any values and it may be confusing.
OK , I will fix it in V3, thanks.
Quoted 1 line
.
.
PATCH v2 5/9 net/hns3: delete redundant xstats RAS statistics
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-)
drivers/net/hns3/hns3_ethdev.c +0 -2
@@ -5770,14 +5770,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val =hns3_read_dev (hw,HNS3_VECTOR0_OTER_EN_REG );if (hns3_get_bit (reg_val,HNS3_VECTOR0_IMP_RD_POISON_B )) {hns3_warn (hw,"Detected IMP RD poison!" ); -hns3_error_int_stats_add (hns,"IMP_RD_POISON_INT_STS" );hns3_set_bit (reg_val,HNS3_VECTOR0_IMP_RD_POISON_B ,0 );hns3_write_dev (hw,HNS3_VECTOR0_OTER_EN_REG , reg_val); }if (hns3_get_bit (reg_val,HNS3_VECTOR0_IMP_CMDQ_ERR_B )) {hns3_warn (hw,"Detected IMP CMDQ error!" ); -hns3_error_int_stats_add (hns,"CMDQ_MEM_ECC_INT_STS" );hns3_set_bit (reg_val,HNS3_VECTOR0_IMP_CMDQ_ERR_B ,0 );hns3_write_dev (hw,HNS3_VECTOR0_OTER_EN_REG , reg_val); }
drivers/net/hns3/hns3_ethdev.h +0 -35
@@ -561,38 +561,6 @@ struct hns3_hw {#define HNS3_FLAG_TC_BASE_SCH_MODE 1#define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { -uint64_t mac_afifo_tnl_int_cnt; -uint64_t ppu_mpf_abn_int_st2_msix_cnt; -uint64_t ssu_port_based_pf_int_cnt; -uint64_t ppp_pf_abnormal_int_cnt; -uint64_t ppu_pf_abnormal_int_msix_cnt; - -uint64_t imp_tcm_ecc_int_cnt; -uint64_t cmdq_mem_ecc_int_cnt; -uint64_t imp_rd_poison_int_cnt; -uint64_t tqp_int_ecc_int_cnt; -uint64_t msix_ecc_int_cnt; -uint64_t ssu_ecc_multi_bit_int_0_cnt; -uint64_t ssu_ecc_multi_bit_int_1_cnt; -uint64_t ssu_common_ecc_int_cnt; -uint64_t igu_int_cnt; -uint64_t ppp_mpf_abnormal_int_st1_cnt; -uint64_t ppp_mpf_abnormal_int_st3_cnt; -uint64_t ppu_mpf_abnormal_int_st1_cnt; -uint64_t ppu_mpf_abn_int_st2_ras_cnt; -uint64_t ppu_mpf_abnormal_int_st3_cnt; -uint64_t tm_sch_int_cnt; -uint64_t qcn_fifo_int_cnt; -uint64_t qcn_ecc_int_cnt; -uint64_t ncsi_ecc_int_cnt; -uint64_t ssu_port_based_err_int_cnt; -uint64_t ssu_fifo_overflow_int_cnt; -uint64_t ssu_ets_tcg_int_cnt; -uint64_t igu_egu_tnl_int_cnt; -uint64_t ppu_pf_abnormal_int_ras_cnt; -}; -/* vlan entry information. */ struct hns3_user_vlan_table {LIST_ENTRY (hns3_user_vlan_table) next;
@@ -738,9 +706,6 @@ struct hns3_pf {uint16_t max_umv_size;uint16_t used_umv_size; -/* Statistics information for abnormal interrupt */ -struct hns3_err_msix_intr_stats abn_int_stats; -bool support_sfp_query;uint32_t fec_mode;/* current FEC mode for ethdev */
drivers/net/hns3/hns3_intr.c +0 -1
@@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } -hns3_error_int_stats_add (hns, reg); } err++; }
drivers/net/hns3/hns3_stats.c +1 -99
154 lines not on this page · raw message
drivers/net/hns3/hns3_stats.h +0 -1
@@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,const uint64_t *ids, uint32_t size);int hns3_stats_reset (struct rte_eth_dev *dev); -void hns3_error_int_stats_add (struct hns3_adapter *hns,const char *err);int hns3_tqp_stats_init (struct hns3_hw *hw);void hns3_tqp_stats_uninit (struct hns3_hw *hw);int hns3_update_imissed_stats (struct hns3_hw *hw,bool is_clear);
Signature · 1 line
2.7.4
PATCH v2 6/9 net/hns3: support imissed stats for PF/VF
In reply to Min Hu (Connor)This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF.
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_cmd.h | 14 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 233 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-)
drivers/net/hns3/hns3_cmd.h +14 -0
@@ -111,6 +111,8 @@ enum hns3_opcode_type {HNS3_OPC_QUERY_DEV_SPECS =0x0050 , +HNS3_OPC_SSU_DROP_REG =0x0065 , +/* MAC command */ HNS3_OPC_CONFIG_MAC_MODE =0x0301 , HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
@@ -957,6 +959,18 @@ struct hns3_query_rpu_cmd {uint32_t rsv2[2 ]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { +uint8_t rxtx; +uint8_t rsv[3 ]; +uint32_t full_drop_cnt; +uint32_t part_drop_cnt; +uint32_t ncsi_full_drop_cnt; +uint32_t ncsi_part_drop_cnt; +uint32_t oq_glb_drop_cnt; +}; +#define HNS3_MAX_TQP_NUM_HIP08_PF 64#define HNS3_DEFAULT_TX_BUF 0x4000/* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000/* 1.03125M bytes */
drivers/net/hns3/hns3_ethdev.c +2 -0
@@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_2US ; hw->tso_mode =HNS3_TSO_SW_CAL_PSEUDO_H_CSUM ; hw->vlan_mode =HNS3_SW_SHIFT_AND_DISCARD_MODE ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE1 ; hw->min_tx_pkt_len =HNS3_HIP08_MIN_TX_PKT_LEN ; pf->tqp_config_mode =HNS3_FIXED_MAX_TQP_NUM_MODE ; hw->rss_info.ipv6_sctp_offload_supported = false;
@@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_1US ; hw->tso_mode =HNS3_TSO_HW_CAL_PSEUDO_H_CSUM ; hw->vlan_mode =HNS3_HW_SHIFT_AND_DISCARD_MODE ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE2 ; hw->min_tx_pkt_len =HNS3_HIP09_MIN_TX_PKT_LEN ; pf->tqp_config_mode =HNS3_FLEX_MAX_TQP_NUM_MODE ; hw->rss_info.ipv6_sctp_offload_supported = true;
drivers/net/hns3/hns3_ethdev.h +21 -0
@@ -426,6 +426,9 @@ struct hns3_queue_intr {#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 +struct hns3_hw {struct rte_eth_dev_data *data;void *io_base;
@@ -544,6 +547,24 @@ struct hns3_hw {* port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + +/* +* drop_stats_mode mode. +* value range: +* HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 +* +* - HNS3_PKTS_DROP_STATS_MODE1 +* This mode for kunpeng920. In this mode, port level imissed stats +* is supported. It only includes RPU drop stats. +* +* - HNS3_PKTS_DROP_STATS_MODE2 +* This mode for kunpeng930. In this mode, imissed stats and oerrors +* stats is supported. Function level imissed stats is supported. It +* includes RPU drop stats in VF, and includes both RPU drop stats +* and SSU drop stats in PF. Oerror stats is also supported in PF. +*/ +uint8_t drop_stats_mode; +uint8_t max_non_tso_bd_num;/* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg;
drivers/net/hns3/hns3_ethdev_vf.c +9 -0
@@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode =HNS3_INTR_MAPPING_VEC_RSV_ONE ; hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_2US ; hw->tso_mode =HNS3_TSO_SW_CAL_PSEUDO_H_CSUM ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE1 ; hw->min_tx_pkt_len =HNS3_HIP08_MIN_TX_PKT_LEN ; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode =HNS3_UNLIMIT_PROMISC_MODE ;
@@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode =HNS3_INTR_MAPPING_VEC_ALL ; hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_1US ; hw->tso_mode =HNS3_TSO_HW_CAL_PSEUDO_H_CSUM ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE2 ; hw->min_tx_pkt_len =HNS3_HIP09_MIN_TX_PKT_LEN ; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode =HNS3_LIMIT_PROMISC_MODE ;
@@ -1877,6 +1879,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev)if (ret) goto err_get_config; +/* Hardware statistics of imissed registers cleared. */ + ret =hns3_update_imissed_stats (hw, true); +if (ret) { +hns3_err (hw,"clear imissed stats failed, ret = %d" , ret); + goto err_set_tc_queue; + } + ret =hns3vf_set_tc_queue_mapping (hns, hw->tqps_num, hw->tqps_num);if (ret) {PMD_INIT_LOG (ERR ,"failed to set tc info, ret = %d." , ret);
drivers/net/hns3/hns3_regs.h +2 -0
@@ -36,6 +36,8 @@#define HNS3_GLOBAL_RESET_REG 0x20A00#define HNS3_FUN_RST_ING 0x20C00#define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004#define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008/* Vector0 register bits for reset */
drivers/net/hns3/hns3_stats.c +181 -52
325 lines not on this page · raw message
drivers/net/hns3/hns3_stats.h +1 -0
@@ -112,6 +112,7 @@ struct hns3_mac_stats {struct hns3_rx_missed_stats {uint64_t rpu_rx_drop_cnt; +uint64_t ssu_rx_drop_cnt; };/* store statistics names and its offset in stats structure */
Signature · 1 line
2.7.4
PATCH v2 7/9 net/hns3: support oerrors stats in PF
In reply to Min Hu (Connor)This patch added oerrors stats for PF in kunpeng930.
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 61 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+)
drivers/net/hns3/hns3_ethdev.h +1 -0
@@ -443,6 +443,7 @@ struct hns3_hw {/* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats;struct hns3_rx_missed_stats imissed_stats; +uint64_t oerror_stats;uint32_t fw_version;uint16_t num_msi;
drivers/net/hns3/hns3_stats.c +61 -0
85 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v2 8/9 net/hns3: support query Tx descriptor status
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+)
doc/guides/nics/features/hns3.ini +1 -0
@@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y
doc/guides/nics/features/hns3_vf.ini +1 -0
@@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for Tx push qick doorbell to improve performance. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +1 -0
@@ -6776,6 +6776,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; + eth_dev->tx_descriptor_status =NULL ;rte_free (eth_dev->process_private); eth_dev->process_private =NULL ;return ret;
drivers/net/hns3/hns3_ethdev_vf.c +1 -0
@@ -2919,6 +2919,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; + eth_dev->tx_descriptor_status =NULL ;rte_free (eth_dev->process_private); eth_dev->process_private =NULL ;
drivers/net/hns3/hns3_rxtx.c +28 -0
@@ -4125,6 +4125,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst =hns3_get_rx_function (eth_dev); eth_dev->tx_pkt_burst =hns3_get_tx_function (eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; }else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
@@ -4337,6 +4338,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt)return -ENOTSUP ; } +int +hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset) +{ +volatile struct hns3_desc *txdp; +struct hns3_tx_queue *txq; +struct rte_eth_dev *dev; +uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; +if (offset >= txq->nb_tx_desc) +return -EINVAL ; + + dev = &rte_eth_devices[txq->port_id]; +if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) +return RTE_ETH_TX_DESC_UNAVAIL ; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; +if (txdp->tx.tp_fe_sc_vld_ra_ri &rte_cpu_to_le_16 (BIT (HNS3_TXD_VLD_B ))) +return RTE_ETH_TX_DESC_FULL ; +else +return RTE_ETH_TX_DESC_DONE ; +} +uint32_t hns3_rx_queue_count (struct rte_eth_dev *dev,uint16_t rx_queue_id) {
drivers/net/hns3/hns3_rxtx.h +1 -0
@@ -743,6 +743,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev);void hns3_restore_tqp_enable_state (struct hns3_hw *hw);int hns3_tx_done_cleanup (void *txq,uint32_t free_cnt);void hns3_enable_rxd_adv_layout (struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset);void hns3_tx_push_init (struct rte_eth_dev *dev);#endif /* _HNS3_RXTX_H_ */
Signature · 1 line
2.7.4
PATCH v2 9/9 net/hns3: support query Rx descriptor status
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+)
doc/guides/nics/features/hns3.ini +1 -0
@@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y
doc/guides/nics/features/hns3_vf.ini +1 -0
@@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -64,6 +64,7 @@ New Features * Added support for Tx push qick doorbell to improve performance. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +1 -0
@@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops =NULL ; eth_dev->rx_pkt_burst =NULL ; + eth_dev->rx_descriptor_status =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; eth_dev->tx_descriptor_status =NULL ;
drivers/net/hns3/hns3_ethdev_vf.c +1 -0
@@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops =NULL ; eth_dev->rx_pkt_burst =NULL ; + eth_dev->rx_descriptor_status =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; eth_dev->tx_descriptor_status =NULL ;
drivers/net/hns3/hns3_rxtx.c +36 -0
@@ -4123,6 +4123,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)if (hns->hw.adapter_state ==HNS3_NIC_STARTED &&__atomic_load_n (&hns->hw.reset.resetting, __ATOMIC_RELAXED) ==0 ) { eth_dev->rx_pkt_burst =hns3_get_rx_function (eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst =hns3_get_tx_function (eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status;
@@ -4339,6 +4340,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) }int +hns3_dev_rx_descriptor_status (void *rx_queue,uint16_t offset) +{ +volatile struct hns3_desc *rxdp; +struct hns3_rx_queue *rxq; +struct rte_eth_dev *dev; +uint32_t bd_base_info; +uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; +if (offset >= rxq->nb_rx_desc) +return -EINVAL ; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info =rte_le_to_cpu_32 (rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; +if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { +if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) +return RTE_ETH_RX_DESC_UNAVAIL ; + }else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ +if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) +return RTE_ETH_RX_DESC_UNAVAIL ; + }else { +return RTE_ETH_RX_DESC_UNAVAIL ; + } + +if (!(bd_base_info &BIT (HNS3_RXD_VLD_B ))) +return RTE_ETH_RX_DESC_AVAIL ; +else +return RTE_ETH_RX_DESC_DONE ; +} + +int hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset) {volatile struct hns3_desc *txdp;
drivers/net/hns3/hns3_rxtx.h +1 -0
@@ -743,6 +743,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev);void hns3_restore_tqp_enable_state (struct hns3_hw *hw);int hns3_tx_done_cleanup (void *txq,uint32_t free_cnt);void hns3_enable_rxd_adv_layout (struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status (void *rx_queue,uint16_t offset);int hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset);void hns3_tx_push_init (struct rte_eth_dev *dev);
Signature · 1 line
2.7.4
v3 cover features and bugfixes for hns3
In reply to Min Hu (Connor)This series add four features according to the 21.05 roadmap, and also two cleanups added.
Chengchang Tang (1):
net/hns3: support for outer UDP cksum
Chengwen Feng (1):
net/hns3: support runtime config to select IO burst func
Hongbo Zheng (4):
net/hns3: adjust the format of RAS related structures net/hns3: delete redundant xstats RAS statistics net/hns3: support query Tx descriptor status net/hns3: support query Rx descriptor status
Min Hu (Connor) (2):
net/hns3: support imissed stats for PF/VF
net/hns3: support oerrors stats in PF
doc/guides/nics/features/hns3.ini | 2 + doc/guides/nics/features/hns3_vf.ini | 2 + doc/guides/nics/hns3.rst | 20 + doc/guides/rel_notes/release_21_05.rst | 4 + drivers/net/hns3/hns3_cmd.c | 3 + drivers/net/hns3/hns3_cmd.h | 14 + drivers/net/hns3/hns3_ethdev.c | 86 +- drivers/net/hns3/hns3_ethdev.h | 76 +- drivers/net/hns3/hns3_ethdev_vf.c | 18 + drivers/net/hns3/hns3_intr.c | 2127 ++++++++++++++++++-------------- drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_rxtx.c | 203 ++- drivers/net/hns3/hns3_rxtx.h | 6 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- drivers/net/hns3/hns3_stats.c | 388 +++--- drivers/net/hns3/hns3_stats.h | 2 +- 16 files changed, 1836 insertions(+), 1122 deletions(-)
Signature · 1 line
2.7.4
PATCH v3 1/8 net/hns3: support runtime config to select IO burst func
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common.
The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.
Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/nics/hns3.rst | 20 +++++++++ doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- 6 files changed, 157 insertions(+), 14 deletions(-)
doc/guides/nics/hns3.rst +20 -0
@@ -46,6 +46,26 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. +Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Rx usage condition then use the neon Rx function. + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function. + When equal "common" then use the common Rx function. + +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Tx usage condition then use the neon Tx function. + When equal "sve" and meet the sve Tx usage condition then use the sve Tx function. + When equal "simple" and meet the simple Tx usage condition then use the simple Tx function. + When equal "common" then use the common Tx function. + + Driver compilation and testing ------------------------------
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +77 -0
100 lines not on this page · raw message
drivers/net/hns3/hns3_ethdev.h +15 -0
@@ -772,9 +772,23 @@ struct hns3_adapter {bool tx_simple_allowed;bool tx_vec_allowed; +uint32_t rx_func_hint; +uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { +HNS3_IO_FUNC_HINT_NONE =0 , +HNS3_IO_FUNC_HINT_VEC , +HNS3_IO_FUNC_HINT_SVE , +HNS3_IO_FUNC_HINT_SIMPLE , +HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" +#define HNS3_DEV_SUPPORT_DCB_B 0x0#define HNS3_DEV_SUPPORT_COPPER_B 0x1#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
@@ -975,6 +989,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info);void hns3vf_update_link_status (struct hns3_hw *hw,uint8_t link_status,uint32_t link_speed,uint8_t link_duplex); +void hns3_parse_devargs (struct rte_eth_dev *dev);static inline bool is_reset_pending (struct hns3_adapter *hns)
drivers/net/hns3/hns3_ethdev_vf.c +4 -0
@@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state =HNS3_NIC_UNINITIALIZED ; hns->is_vf = true; hw->data = eth_dev->data; +hns3_parse_devargs (eth_dev); ret =hns3_reset_init (hw);if (ret)
@@ -2962,3 +2963,6 @@ static struct rte_pci_driver rte_hns3vf_pmd = {RTE_PMD_REGISTER_PCI (net_hns3_vf, rte_hns3vf_pmd);RTE_PMD_REGISTER_PCI_TABLE (net_hns3_vf, pci_id_hns3vf_map);RTE_PMD_REGISTER_KMOD_DEP (net_hns3_vf,"* igb_uio | vfio-pci" ); +RTE_PMD_REGISTER_PARAM_STRING (net_hns3_vf, +HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " +HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " );
drivers/net/hns3/hns3_rxtx.c +40 -14
72 lines not on this page · raw message
Signature · 1 line
2.7.4
Re: [dpdk-dev] [PATCH v3 1/8] net/hns3: support runtime config to select IO burst func
Quoted 63 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>--- doc/guides/nics/hns3.rst | 20 +++++++++ doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- 6 files changed, 157 insertions(+), 14 deletions(-)doc/guides/nics/hns3.rst +9
-0@@ -46,6 +46,26 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. +Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Rx usage condition then use the neon Rx function. + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function.
doc/guides/nics/hns3.rst Prerequisites · line 67
Quoted 10 lines
doc/guides/nics/hns3.rst +10
-0+ When equal "common" then use the common Rx function. + +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Tx usage condition then use the neon Tx function. + When equal "sve" and meet the sve Tx usage condition then use the sve Tx function. + When equal "simple" and meet the simple Tx usage condition then use the simple Tx function. + When equal "common" then use the common Tx function. +
I think 'vec' & 'sve' are more self explenatory, but can you please describe what is 'common' and 'simple', and the difference of these two?
btw, since both 'neon' and 'sve' are vector implementations, what do you think to have arguments as 'neon' & 'sve', instead of 'vec' & 'sve'?
Re: [dpdk-dev] [PATCH v3 1/8] net/hns3: support runtime config to select IO burst func
Quoted 75 lines · Ferruh Yigit
Quoted 74 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>---
doc/guides/nics/hns3.rst | 20 +++++++++doc/guides/rel_notes/release_21_05.rst| 1 + drivers/net/hns3/hns3_ethdev.c | 77
++++++++++++++++++++++++++++++++++
drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++-------6 files changed, 157 insertions(+), 14 deletions(-)doc/guides/nics/hns3.rst +0
-0@@ -46,6 +46,26 @@ Prerequisites- Follow the DPDK :ref:
Getting Started Guide for Linux <linux_gsg>to setup the basic DPDK environment.doc/guides/nics/hns3.rst +6
-0+Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve","simple", "common".
+ When equal "vec" and meet the vector Rx usage condition then use the neon Rx function.
+ When equal "sve" and meet the sve Rx usage condition then use the sve Rx function.
+ When equal "simple" and meet the simple Rx usage condition then use the simple Rx function.
+ When equal "common" then use the common Rx function.doc/guides/nics/hns3.rst +4
-0+ +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve","simple", "common".
+ When equal "vec" and meet the vector Tx usage condition then use the neon Tx function.
Quoted 8 lines
Quoted 6 lines
+ When equal "sve" and meet the sve Tx usage condition then use the sve Tx function.
+ When equal "simple" and meet the simple Tx usage condition then use the simple Tx function.
+ When equal "common" then use the common Tx function.
+I think 'vec' & 'sve' are more self explenatory, but can you please describe what is 'common' and 'simple', and the difference of these two?
In the Rx direction, simple indicates that the Scalar algorithm obtained from rte_eth_rx_burst_mode_get, and common indicates that the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get.
In the TX direction, simple indicates that the Scalar Simple algorithm in the rte_eth_tx_burst_mode_get, and common indicates that the Scalar algorithm obtained in the rte_eth_tx_burst_mode_get.
Later, we will send a patch to modify the names obtained in rte_eth_rx_burst_mode_get, that is, the original Scalar is renamed Scalar Simple and Scalar Scattered is renamed Scalar. The Rx and Tx are not in correspondence, which may leads to misunderstanding.
Quoted 2 lines
btw, since both 'neon' and 'sve' are vector implementations, what do you think to have arguments as 'neon' & 'sve', instead of 'vec' & 'sve'?
'vec' here means the default vector type in the current platform(In future, we will support NIC in different kinds of platform). when the DPDK run on different platform, the default vector will be different. For instance, now in ARM soc, 'vec' means 'neon', in X86 platform, 'vec' means 'SSE/AVX' or others.
thanks
Quoted 1 line
.
Re: [dpdk-dev] [PATCH v3 1/8] net/hns3: support runtime config to select IO burst func
Quoted 85 lines · Min Hu (Connor)
Quoted 74 lines · Ferruh Yigit
Quoted 73 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>---
doc/guides/nics/hns3.rst | 20 +++++++++doc/guides/rel_notes/release_21_05.rst| 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++-------6 files changed, 157 insertions(+), 14 deletions(-)doc/guides/nics/hns3.rst +0
-0@@ -46,6 +46,26 @@ Prerequisites- Follow the DPDK :ref:
Getting Started Guide for Linux <linux_gsg>to setup the basic DPDK environment.doc/guides/nics/hns3.rst +6
-0+Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve","simple", "common".
+ When equal "vec" and meet the vector Rx usage condition then use the neon Rx function.
+ When equal "sve" and meet the sve Rx usage condition then use the sve Rx function.
+ When equal "simple" and meet the simple Rx usage condition then use the simple Rx function.
+ When equal "common" then use the common Rx function.doc/guides/nics/hns3.rst +4
-0+ +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve","simple", "common".
+ When equal "vec" and meet the vector Tx usage condition then use the neon Tx function.Quoted 8 lines
Quoted 6 lines
+ When equal "sve" and meet the sve Tx usage condition then use the sve Tx function.
+ When equal "simple" and meet the simple Tx usage condition then use the simple Tx function.
+ When equal "common" then use the common Tx function.
+I think 'vec' & 'sve' are more self explenatory, but can you please describe what is 'common' and 'simple', and the difference of these two?
Quoted 4 lines
In the Rx direction, simple indicates that the Scalar algorithm obtained from
rte_eth_rx_burst_mode_get, and common indicates that the Scalar Scattered algorithm obtained fromrte_eth_rx_burst_mode_get.In the TX direction, simple indicates that the Scalar Simple algorithm in the
rte_eth_tx_burst_mode_get, and common indicates that the Scalar algorithm obtained in therte_eth_tx_burst_mode_get.
Got it, can you please document what you described above in this document?
Quoted 7 lines
Later, we will send a patch to modify the names obtained in
rte_eth_rx_burst_mode_get, that is, the original Scalar is renamed Scalar Simple and Scalar Scattered is renamed Scalar. The Rx and Tx are not in correspondence, which may leads to misunderstanding.Quoted 2 lines
btw, since both 'neon' and 'sve' are vector implementations, what do you think to have arguments as 'neon' & 'sve', instead of 'vec' & 'sve'?
'vec' here means the default vector type in the current
platform(In future, we will support NIC in different kinds of platform). when the DPDK run on different platform, the default vector will be different. For instance, now in ARM soc, 'vec' means 'neon', in X86 platform, 'vec' means 'SSE/AVX' or others.
I see, again can you document this above, in document for 'vec' it says "use the neon", instead it can say something like "use default vector implementation, 'neon' for Arm" ...
Btw, I can see v4 sent, but there is no changelog, and documentation seems same, what has changed there?
Re: [dpdk-dev] [PATCH v3 1/8] net/hns3: support runtime config to select IO burst func
Quoted 87 lines · Ferruh Yigit
Quoted 86 lines · Min Hu (Connor)
Quoted 83 lines · Ferruh Yigit
Quoted 72 lines · Min Hu (Connor)
From: Chengwen Feng <[email protected]>
Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration.
Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function.
This patch support runtime config to select io burst function, which add two config:
rx_func_hintandtx_func_hint, both could assign vec/sve/simple/common.The driver will use the following rules to select io burst func:
a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function.
b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function.
c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function.
d. if hint equal common then use the common function.
e. if hint not set then:
e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function.
e.3. else use the common function.Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE).
In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function.
Signed-off-by Chengwen Feng <[email protected]>Signed-off-by Min Hu (Connor) <[email protected]>---
doc/guides/nics/hns3.rst | 20 +++++++++doc/guides/rel_notes/release_21_05.rst| 1 + drivers/net/hns3/hns3_ethdev.c | 77
++++++++++++++++++++++++++++++++++
drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++-------6 files changed, 157 insertions(+), 14 deletions(-)doc/guides/nics/hns3.rst +0
-0@@ -46,6 +46,26 @@ Prerequisites- Follow the DPDK :ref:
Getting Started Guide for Linux <linux_gsg>to setup the basic DPDK environment.doc/guides/nics/hns3.rst +6
-0+Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec","sve", "simple", "common".
+ When equal "vec" and meet the vector Rx usage condition then use the neon Rx function.
+ When equal "sve" and meet the sve Rx usage condition then use the sve Rx function.
+ When equal "simple" and meet the simple Rx usage condition then use the simple Rx function.
+ When equal "common" then use the common Rx function.doc/guides/nics/hns3.rst +4
-0+ +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec","sve", "simple", "common".
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+ When equal "vec" and meet the vector Tx usage condition then use the neon Tx function.
+ When equal "sve" and meet the sve Tx usage condition then use the sve Tx function.
+ When equal "simple" and meet the simple Tx usage condition then use the simple Tx function.
+ When equal "common" then use the common Tx function.
+I think 'vec' & 'sve' are more self explenatory, but can you please describe what is 'common' and 'simple', and the difference of these two?
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In the Rx direction, simple indicates that the Scalar algorithm obtained from
rte_eth_rx_burst_mode_get, and common indicates that the Scalar Scattered algorithm obtained fromrte_eth_rx_burst_mode_get.In the TX direction, simple indicates that the Scalar Simple algorithm in the
rte_eth_tx_burst_mode_get, and common indicates that the Scalar algorithm obtained in therte_eth_tx_burst_mode_get.Got it, can you please document what you described above in this document?
done it, I have sent V5, please check it, thanks.
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Later, we will send a patch to modify the names obtained in
rte_eth_rx_burst_mode_get, that is, the original Scalar is renamed Scalar Simple and Scalar Scattered is renamed Scalar. The Rx and Tx are not in correspondence, which may leads to misunderstanding.Quoted 2 lines
btw, since both 'neon' and 'sve' are vector implementations, what do you think to have arguments as 'neon' & 'sve', instead of 'vec' & 'sve'?
'vec' here means the default vector type in the current
platform(In future, we will support NIC in different kinds of platform). when the DPDK run on different platform, the default vector will be different. For instance, now in ARM soc, 'vec' means 'neon', in X86 platform, 'vec' means 'SSE/AVX' or others.I see, again can you document this above, in document for 'vec' it says "use the neon", instead it can say something like "use default vector implementation, 'neon' for Arm" ...
done it, I have sent V5, please check it, thanks.
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Btw, I can see v4 sent, but there is no changelog, and documentation seems same, what has changed there?
I have added changelog, I have sent V5, please check it, thanks.
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.
PATCH v3 2/8 net/hns3: support for outer UDP cksum
In reply to Min Hu (Connor)From: Chengchang Tang <[email protected]>
Kunpeng930 support outer UDP cksum, this patch add support for it.
Signed-off-by Chengchang Tang <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-)
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_cmd.c +3 -0
@@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw,if (hns3_get_bit (caps,HNS3_CAPS_RXD_ADV_LAYOUT_B ))hns3_set_bit (hw->capability,HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B ,1 ); +if (hns3_get_bit (caps,HNS3_CAPS_UDP_TUNNEL_CSUM_B )) +hns3_set_bit (hw->capability, +HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B ,1 ); } static uint32_t
drivers/net/hns3/hns3_ethdev.c +3 -0
@@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); +if (hns3_dev_outer_udp_cksum_supported (hw)) + info->tx_offload_capa |=DEV_TX_OFFLOAD_OUTER_UDP_CKSUM ; +if (hns3_dev_indep_txrx_supported (hw)) info->dev_capa =RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP ;
drivers/net/hns3/hns3_ethdev.h +4 -0
@@ -798,6 +798,7 @@ enum {#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6#define HNS3_DEV_SUPPORT_STASH_B 0x7#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA#define hns3_dev_dcb_supported (hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
@@ -831,6 +832,9 @@ enum {#define hns3_dev_rxd_adv_layout_supported (hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported (hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) +#define HNS3_DEV_PRIVATE_TO_HW (adapter) \ (&((struct hns3_adapter *)adapter)->hw)#define HNS3_DEV_PRIVATE_TO_PF (adapter) \
drivers/net/hns3/hns3_ethdev_vf.c +3 -0
@@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); +if (hns3_dev_outer_udp_cksum_supported (hw)) + info->tx_offload_capa |=DEV_TX_OFFLOAD_OUTER_UDP_CKSUM ; +if (hns3_dev_indep_txrx_supported (hw)) info->dev_capa =RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP ;
drivers/net/hns3/hns3_rxtx.c +69 -16
149 lines not on this page · raw message
drivers/net/hns3/hns3_rxtx.h +3 -1
@@ -149,6 +149,7 @@#define HNS3_TXD_MSS_S 0#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22#define HNS3_L2_LEN_UNIT 1UL#define HNS3_L3_LEN_UNIT 2UL#define HNS3_L4_LEN_UNIT 2UL
@@ -234,7 +235,7 @@ struct hns3_desc { }; }; -uint32_t paylen; +uint32_t paylen_fd_dop_ol4cs;uint16_t tp_fe_sc_vld_ra_ri;uint16_t mss; } tx;
@@ -503,6 +504,7 @@ struct hns3_queue_info { };#define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \
drivers/net/hns3/hns3_rxtx_vec_sve.c +3 -2
@@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0));/* save offset 24~31byte of every BD */ -svst1_scatter_u64offset_u64 (pg, (uint64_t *)&txdp->tx.paylen, - offsets,svdup_n_u64 (valid_bit)); +svst1_scatter_u64offset_u64 (pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets,svdup_n_u64 (valid_bit));/* Increment bytes counter */ uint32_t idx;
Signature · 1 line
2.7.4
PATCH v3 3/8 net/hns3: adjust the format of RAS related structures
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
Adjust the format of hns3 RAS related structures to resolve the static check warnings.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-)
drivers/net/hns3/hns3_intr.c +1224 -902
@@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { };static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk =BIT (0 ), - .msg ="egu_cge_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (1 ), - .msg ="egu_cge_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="egu_lge_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (3 ), - .msg ="egu_lge_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="cge_igu_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="cge_igu_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="lge_igu_afifo_ecc_1bit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="lge_igu_afifo_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="cge_igu_afifo_overflow_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="lge_igu_afifo_overflow_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="egu_cge_afifo_underrun_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="egu_lge_afifo_underrun_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="egu_ge_afifo_underrun_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="ge_igu_afifo_overflow_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="egu_cge_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (1 ), + .msg ="egu_cge_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="egu_lge_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (3 ), + .msg ="egu_lge_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="cge_igu_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="cge_igu_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="lge_igu_afifo_ecc_1bit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="lge_igu_afifo_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="cge_igu_afifo_overflow_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="lge_igu_afifo_overflow_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="egu_cge_afifo_underrun_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="egu_lge_afifo_underrun_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="egu_ge_afifo_underrun_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="ge_igu_afifo_overflow_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk =0xFFFFFFFF , - .msg ="rpu_rx_pkt_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =0xFFFFFFFF , + .msg ="rpu_rx_pkt_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk =BIT (13 ), - .msg ="rpu_rx_pkt_bit32_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="rpu_rx_pkt_bit33_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="rpu_rx_pkt_bit34_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="rpu_rx_pkt_bit35_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="rcb_tx_ring_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="rcb_rx_ring_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="rcb_tx_fbd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="rcb_rx_ebd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="rcb_tso_info_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="rcb_tx_int_info_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="rcb_rx_int_info_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (24 ), - .msg ="tpu_tx_pkt_0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (25 ), - .msg ="tpu_tx_pkt_1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (26 ), - .msg ="rd_bus_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (27 ), - .msg ="wr_bus_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (30 ), - .msg ="ooo_ecc_err_detect" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (31 ), - .msg ="ooo_ecc_err_multpl" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (13 ), + .msg ="rpu_rx_pkt_bit32_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="rpu_rx_pkt_bit33_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="rpu_rx_pkt_bit34_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="rpu_rx_pkt_bit35_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="rcb_tx_ring_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="rcb_rx_ring_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="rcb_tx_fbd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="rcb_rx_ebd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="rcb_tso_info_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="rcb_tx_int_info_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="rcb_rx_int_info_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (24 ), + .msg ="tpu_tx_pkt_0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (25 ), + .msg ="tpu_tx_pkt_1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (26 ), + .msg ="rd_bus_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (27 ), + .msg ="wr_bus_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (30 ), + .msg ="ooo_ecc_err_detect" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (31 ), + .msg ="ooo_ecc_err_multpl" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk =BIT (29 ), - .msg ="rx_q_search_miss" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (29 ), + .msg ="rx_q_search_miss" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk =BIT (0 ), - .msg ="roc_pkt_without_key_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="low_water_line_err_port" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="roc_pkt_without_key_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="low_water_line_err_port" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk =BIT (0 ), - .msg ="tx_vlan_tag_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (1 ), - .msg ="rss_list_tc_unassigned_queue_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="tx_vlan_tag_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (1 ), + .msg ="rss_list_tc_unassigned_queue_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk =BIT (3 ), - .msg ="tx_rd_fbd_poison" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =BIT (4 ), - .msg ="rx_rd_ebd_poison" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (3 ), + .msg ="tx_rd_fbd_poison" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =BIT (4 ), + .msg ="rx_rd_ebd_poison" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk =BIT (0 ), - .msg ="over_8bd_no_fe" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =BIT (1 ), - .msg ="tso_mss_cmp_min_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (2 ), - .msg ="tso_mss_cmp_max_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="buf_wait_timeout" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="over_8bd_no_fe" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =BIT (1 ), + .msg ="tso_mss_cmp_min_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (2 ), + .msg ="tso_mss_cmp_max_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="buf_wait_timeout" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="imp_itcm0_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (3 ), - .msg ="imp_itcm1_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="imp_itcm2_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="imp_itcm3_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (9 ), - .msg ="imp_dtcm0_mem0_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (11 ), - .msg ="imp_dtcm0_mem1_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (13 ), - .msg ="imp_dtcm1_mem0_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (15 ), - .msg ="imp_dtcm1_mem1_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (17 ), - .msg ="imp_itcm4_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="imp_itcm0_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (3 ), + .msg ="imp_itcm1_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="imp_itcm2_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="imp_itcm3_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (9 ), + .msg ="imp_dtcm0_mem0_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (11 ), + .msg ="imp_dtcm0_mem1_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (13 ), + .msg ="imp_dtcm1_mem0_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (15 ), + .msg ="imp_dtcm1_mem1_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (17 ), + .msg ="imp_itcm4_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="cmdq_nic_rx_depth_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (3 ), - .msg ="cmdq_nic_tx_depth_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (5 ), - .msg ="cmdq_nic_rx_tail_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="cmdq_nic_tx_tail_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (9 ), - .msg ="cmdq_nic_rx_head_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (11 ), - .msg ="cmdq_nic_tx_head_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (13 ), - .msg ="cmdq_nic_rx_addr_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (15 ), - .msg ="cmdq_nic_tx_addr_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="cmdq_nic_rx_depth_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (3 ), + .msg ="cmdq_nic_tx_depth_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (5 ), + .msg ="cmdq_nic_rx_tail_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="cmdq_nic_tx_tail_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (9 ), + .msg ="cmdq_nic_rx_head_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (11 ), + .msg ="cmdq_nic_tx_head_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (13 ), + .msg ="cmdq_nic_rx_addr_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (15 ), + .msg ="cmdq_nic_tx_addr_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk =BIT (6 ), - .msg ="tqp_int_cfg_even_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (7 ), - .msg ="tqp_int_cfg_odd_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (8 ), - .msg ="tqp_int_ctrl_even_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (9 ), - .msg ="tqp_int_ctrl_odd_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (10 ), - .msg ="tx_queue_scan_int_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (11 ), - .msg ="rx_queue_scan_int_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (6 ), + .msg ="tqp_int_cfg_even_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tqp_int_cfg_odd_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (8 ), + .msg ="tqp_int_ctrl_even_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (9 ), + .msg ="tqp_int_ctrl_odd_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (10 ), + .msg ="tx_queue_scan_int_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (11 ), + .msg ="rx_queue_scan_int_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk =BIT (0 ), - .msg ="imp_rd_poison_int" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="imp_rd_poison_int" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };#define HNS3_SSU_MEM_ECC_ERR (x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +}static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = {HNS3_SSU_MEM_ECC_ERR (0 ),
@@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { };static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk =BIT (0 ), - .msg ="ssu_mem32_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="ssu_mem32_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk =BIT (0 ), - .msg ="buf_sum_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (1 ), - .msg ="ppp_mb_num_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =BIT (2 ), - .msg ="ppp_mbid_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="ppp_rlt_mac_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="ppp_rlt_host_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="cks_edit_position_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="cks_edit_condition_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="vlan_edit_condition_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="vlan_num_ot_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="vlan_num_in_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="buf_sum_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (1 ), + .msg ="ppp_mb_num_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =BIT (2 ), + .msg ="ppp_mbid_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="ppp_rlt_mac_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="ppp_rlt_host_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="cks_edit_position_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="cks_edit_condition_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="vlan_edit_condition_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="vlan_num_ot_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="vlan_num_in_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error igu_int[] = { - { .int_msk =BIT (0 ), - .msg ="igu_rx_buf0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="igu_rx_buf1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="igu_rx_buf0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="igu_rx_buf1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="msix_nic_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="msix_nic_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk =BIT (0 ), - .msg ="vf_vlan_ad_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="umv_mcast_group_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="umv_key_mem0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="umv_key_mem1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="umv_key_mem2_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="umv_key_mem3_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="umv_ad_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="rss_tc_mode_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="rss_idt_mem0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="rss_idt_mem1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="rss_idt_mem2_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="rss_idt_mem3_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="rss_idt_mem4_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="rss_idt_mem5_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="rss_idt_mem6_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="rss_idt_mem7_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="rss_idt_mem8_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="rss_idt_mem9_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="rss_idt_mem10_ecc_m1bit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="rss_idt_mem11_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="rss_idt_mem12_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="rss_idt_mem13_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="rss_idt_mem14_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="rss_idt_mem15_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (24 ), - .msg ="port_vlan_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (25 ), - .msg ="mcast_linear_table_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (26 ), - .msg ="mcast_result_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (27 ), - .msg ="flow_director_ad_mem0_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (28 ), - .msg ="flow_director_ad_mem1_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (29 ), - .msg ="rx_vlan_tag_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (30 ), - .msg ="Tx_UP_mapping_config_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="vf_vlan_ad_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="umv_mcast_group_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="umv_key_mem0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="umv_key_mem1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="umv_key_mem2_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="umv_key_mem3_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="umv_ad_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="rss_tc_mode_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="rss_idt_mem0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="rss_idt_mem1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="rss_idt_mem2_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="rss_idt_mem3_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="rss_idt_mem4_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="rss_idt_mem5_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="rss_idt_mem6_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="rss_idt_mem7_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="rss_idt_mem8_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="rss_idt_mem9_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="rss_idt_mem10_ecc_m1bit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="rss_idt_mem11_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="rss_idt_mem12_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="rss_idt_mem13_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="rss_idt_mem14_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="rss_idt_mem15_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (24 ), + .msg ="port_vlan_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (25 ), + .msg ="mcast_linear_table_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (26 ), + .msg ="mcast_result_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (27 ), + .msg ="flow_director_ad_mem0_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (28 ), + .msg ="flow_director_ad_mem1_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (29 ), + .msg ="rx_vlan_tag_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (30 ), + .msg ="Tx_UP_mapping_config_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk =BIT (0 ), - .msg ="hfs_fifo_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="rslt_descr_fifo_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="tx_vlan_tag_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="FD_CN0_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="FD_CN1_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="GRO_AD_memory_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="hfs_fifo_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="rslt_descr_fifo_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="tx_vlan_tag_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="FD_CN0_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="FD_CN1_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="GRO_AD_memory_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk =BIT (4 ), - .msg ="gro_bd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="gro_context_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="rx_stash_cfg_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="axi_rd_fbd_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (4 ), + .msg ="gro_bd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="gro_context_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="rx_stash_cfg_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="axi_rd_fbd_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk =BIT (1 ), - .msg ="tm_sch_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="tm_sch_port_shap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="tm_sch_port_shap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="tm_sch_pg_pshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="tm_sch_pg_pshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="tm_sch_pg_cshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="tm_sch_pg_cshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="tm_sch_pri_pshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="tm_sch_pri_pshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="tm_sch_pri_cshap_sub_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="tm_sch_pri_cshap_sub_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="tm_sch_port_shap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="tm_sch_port_shap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="tm_sch_pg_pshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="tm_sch_pg_pshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="tm_sch_pg_cshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="tm_sch_pg_cshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="tm_sch_pri_pshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="tm_sch_pri_pshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="tm_sch_pri_cshap_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="tm_sch_pri_cshap_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="tm_sch_rq_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="tm_sch_rq_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (24 ), - .msg ="tm_sch_nq_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (25 ), - .msg ="tm_sch_nq_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (26 ), - .msg ="tm_sch_roce_up_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (27 ), - .msg ="tm_sch_roce_up_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (28 ), - .msg ="tm_sch_rcb_byte_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (29 ), - .msg ="tm_sch_rcb_byte_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (30 ), - .msg ="tm_sch_ssu_byte_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (31 ), - .msg ="tm_sch_ssu_byte_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="tm_sch_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="tm_sch_port_shap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="tm_sch_port_shap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="tm_sch_pg_pshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="tm_sch_pg_pshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="tm_sch_pg_cshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tm_sch_pg_cshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="tm_sch_pri_pshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="tm_sch_pri_pshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="tm_sch_pri_cshap_sub_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="tm_sch_pri_cshap_sub_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="tm_sch_port_shap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="tm_sch_port_shap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="tm_sch_pg_pshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="tm_sch_pg_pshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="tm_sch_pg_cshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="tm_sch_pg_cshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="tm_sch_pri_pshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="tm_sch_pri_pshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="tm_sch_pri_cshap_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="tm_sch_pri_cshap_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="tm_sch_rq_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="tm_sch_rq_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (24 ), + .msg ="tm_sch_nq_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (25 ), + .msg ="tm_sch_nq_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (26 ), + .msg ="tm_sch_roce_up_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (27 ), + .msg ="tm_sch_roce_up_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (28 ), + .msg ="tm_sch_rcb_byte_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (29 ), + .msg ="tm_sch_rcb_byte_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (30 ), + .msg ="tm_sch_ssu_byte_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (31 ), + .msg ="tm_sch_ssu_byte_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk =BIT (0 ), - .msg ="qcn_shap_gp0_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="qcn_shap_gp0_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="qcn_shap_gp1_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="qcn_shap_gp1_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="qcn_shap_gp2_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="qcn_shap_gp2_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="qcn_shap_gp3_sch_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="qcn_shap_gp3_sch_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="qcn_shap_gp0_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="qcn_shap_gp0_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="qcn_shap_gp1_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="qcn_shap_gp1_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="qcn_shap_gp2_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="qcn_shap_gp2_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="qcn_shap_gp3_offset_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="qcn_shap_gp3_offset_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="qcn_byte_info_fifo_rd_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="qcn_byte_info_fifo_wr_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="qcn_shap_gp0_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="qcn_shap_gp0_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="qcn_shap_gp1_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="qcn_shap_gp1_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="qcn_shap_gp2_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="qcn_shap_gp2_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="qcn_shap_gp3_sch_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="qcn_shap_gp3_sch_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="qcn_shap_gp0_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="qcn_shap_gp0_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="qcn_shap_gp1_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="qcn_shap_gp1_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="qcn_shap_gp2_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="qcn_shap_gp2_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="qcn_shap_gp3_offset_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="qcn_shap_gp3_offset_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="qcn_byte_info_fifo_rd_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="qcn_byte_info_fifo_wr_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="qcn_byte_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="qcn_time_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="qcn_fb_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="qcn_link_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="qcn_rate_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="qcn_tmplt_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="qcn_shap_cfg_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="qcn_gp0_barrel_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="qcn_gp1_barrel_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="qcn_gp2_barrel_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="qcn_gp3_barral_mem_ecc_mbit_err" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="qcn_byte_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="qcn_time_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="qcn_fb_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="qcn_link_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="qcn_rate_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="qcn_tmplt_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="qcn_shap_cfg_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="qcn_gp0_barrel_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="qcn_gp1_barrel_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="qcn_gp2_barrel_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="qcn_gp3_barral_mem_ecc_mbit_err" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk =BIT (1 ), - .msg ="ncsi_tx_ecc_mbit_err" , - .reset_level =HNS3_NONE_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (1 ), + .msg ="ncsi_tx_ecc_mbit_err" , + .reset_level =HNS3_NONE_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk =BIT (0 ), - .msg ="ig_mac_inf_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="ig_host_inf_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="ig_roc_buf_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="ig_host_data_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="ig_host_key_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="tx_qcn_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="rx_qcn_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="tx_pf_rd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="rx_pf_rd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (9 ), - .msg ="qm_eof_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (10 ), - .msg ="mb_rlt_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="dup_uncopy_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="dup_cnt_rd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="dup_cnt_drop_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="dup_cnt_wrb_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (15 ), - .msg ="host_cmd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (16 ), - .msg ="mac_cmd_fifo_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (17 ), - .msg ="host_cmd_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (18 ), - .msg ="mac_cmd_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (19 ), - .msg ="dup_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (20 ), - .msg ="out_queue_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (21 ), - .msg ="bank2_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (22 ), - .msg ="bank1_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (23 ), - .msg ="bank0_bitmap_empty_int" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="ig_mac_inf_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="ig_host_inf_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="ig_roc_buf_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="ig_host_data_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="ig_host_key_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="tx_qcn_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="rx_qcn_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tx_pf_rd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="rx_pf_rd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (9 ), + .msg ="qm_eof_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (10 ), + .msg ="mb_rlt_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="dup_uncopy_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="dup_cnt_rd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="dup_cnt_drop_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="dup_cnt_wrb_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (15 ), + .msg ="host_cmd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (16 ), + .msg ="mac_cmd_fifo_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (17 ), + .msg ="host_cmd_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (18 ), + .msg ="mac_cmd_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (19 ), + .msg ="dup_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (20 ), + .msg ="out_queue_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (21 ), + .msg ="bank2_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (22 ), + .msg ="bank1_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (23 ), + .msg ="bank0_bitmap_empty_int" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk =BIT (0 ), - .msg ="ets_rd_int_rx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="ets_wr_int_rx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="ets_rd_int_tx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="ets_wr_int_tx_tcg" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="ets_rd_int_rx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="ets_wr_int_rx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="ets_rd_int_tx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="ets_wr_int_tx_tcg" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk =BIT (0 ), - .msg ="rx_buf_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (1 ), - .msg ="rx_stp_fifo_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="rx_stp_fifo_underflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="tx_buf_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="tx_buf_underrun" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="rx_stp_buf_overflow" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="rx_buf_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (1 ), + .msg ="rx_stp_fifo_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="rx_stp_fifo_underflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="tx_buf_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="tx_buf_underrun" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="rx_stp_buf_overflow" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk =BIT (0 ), - .msg ="roc_pkt_without_key_port" , - .reset_level =HNS3_FUNC_RESET }, - { .int_msk =BIT (1 ), - .msg ="tpu_pkt_without_key_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (2 ), - .msg ="igu_pkt_without_key_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (3 ), - .msg ="roc_eof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (4 ), - .msg ="tpu_eof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (5 ), - .msg ="igu_eof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (6 ), - .msg ="roc_sof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (7 ), - .msg ="tpu_sof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (8 ), - .msg ="igu_sof_mis_match_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (11 ), - .msg ="ets_rd_int_rx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (12 ), - .msg ="ets_wr_int_rx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (13 ), - .msg ="ets_rd_int_tx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =BIT (14 ), - .msg ="ets_wr_int_tx_port" , - .reset_level =HNS3_GLOBAL_RESET }, - { .int_msk =0 , - .msg =NULL , - .reset_level =HNS3_NONE_RESET } + { + .int_msk =BIT (0 ), + .msg ="roc_pkt_without_key_port" , + .reset_level =HNS3_FUNC_RESET + }, { + .int_msk =BIT (1 ), + .msg ="tpu_pkt_without_key_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (2 ), + .msg ="igu_pkt_without_key_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (3 ), + .msg ="roc_eof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (4 ), + .msg ="tpu_eof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (5 ), + .msg ="igu_eof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (6 ), + .msg ="roc_sof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (7 ), + .msg ="tpu_sof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (8 ), + .msg ="igu_sof_mis_match_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (11 ), + .msg ="ets_rd_int_rx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (12 ), + .msg ="ets_wr_int_rx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (13 ), + .msg ="ets_rd_int_tx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =BIT (14 ), + .msg ="ets_wr_int_tx_port" , + .reset_level =HNS3_GLOBAL_RESET + }, { + .int_msk =0 , + .msg =NULL , + .reset_level =HNS3_NONE_RESET + } };static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset =0 , - .data_offset =0 , - .msg ="IMP_TCM_ECC_INT_STS" , - .hw_err = imp_tcm_ecc_int }, - { .desc_offset =0 , - .data_offset =1 , - .msg ="CMDQ_MEM_ECC_INT_STS" , - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset =0 , - .data_offset =2 , - .msg ="IMP_RD_POISON_INT_STS" , - .hw_err = imp_rd_poison_int }, - { .desc_offset =0 , - .data_offset =3 , - .msg ="TQP_INT_ECC_INT_STS" , - .hw_err = tqp_int_ecc_int }, - { .desc_offset =0 , - .data_offset =4 , - .msg ="MSIX_ECC_INT_STS" , - .hw_err = msix_ecc_int }, - { .desc_offset =2 , - .data_offset =2 , - .msg ="SSU_ECC_MULTI_BIT_INT_0" , - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset =2 , - .data_offset =3 , - .msg ="SSU_ECC_MULTI_BIT_INT_1" , - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset =2 , - .data_offset =4 , - .msg ="SSU_COMMON_ERR_INT" , - .hw_err = ssu_common_ecc_int }, - { .desc_offset =3 , - .data_offset =0 , - .msg ="IGU_INT_STS" , - .hw_err = igu_int }, - { .desc_offset =4 , - .data_offset =1 , - .msg ="PPP_MPF_ABNORMAL_INT_ST1" , - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset =4 , - .data_offset =3 , - .msg ="PPP_MPF_ABNORMAL_INT_ST3" , - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset =5 , - .data_offset =1 , - .msg ="PPU_MPF_ABNORMAL_INT_ST1" , - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset =5 , - .data_offset =2 , - .msg ="PPU_MPF_ABNORMAL_INT_ST2_RAS" , - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset =5 , - .data_offset =3 , - .msg ="PPU_MPF_ABNORMAL_INT_ST3" , - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset =6 , - .data_offset =0 , - .msg ="TM_SCH_RINT" , - .hw_err = tm_sch_int }, - { .desc_offset =7 , - .data_offset =0 , - .msg ="QCN_FIFO_RINT" , - .hw_err = qcn_fifo_int }, - { .desc_offset =7 , - .data_offset =1 , - .msg ="QCN_ECC_RINT" , - .hw_err = qcn_ecc_int }, - { .desc_offset =9 , - .data_offset =0 , - .msg ="NCSI_ECC_INT_RPT" , - .hw_err = ncsi_ecc_int }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =0 , + .data_offset =0 , + .msg ="IMP_TCM_ECC_INT_STS" , + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset =0 , + .data_offset =1 , + .msg ="CMDQ_MEM_ECC_INT_STS" , + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset =0 , + .data_offset =2 , + .msg ="IMP_RD_POISON_INT_STS" , + .hw_err = imp_rd_poison_int + }, { + .desc_offset =0 , + .data_offset =3 , + .msg ="TQP_INT_ECC_INT_STS" , + .hw_err = tqp_int_ecc_int + }, { + .desc_offset =0 , + .data_offset =4 , + .msg ="MSIX_ECC_INT_STS" , + .hw_err = msix_ecc_int + }, { + .desc_offset =2 , + .data_offset =2 , + .msg ="SSU_ECC_MULTI_BIT_INT_0" , + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset =2 , + .data_offset =3 , + .msg ="SSU_ECC_MULTI_BIT_INT_1" , + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset =2 , + .data_offset =4 , + .msg ="SSU_COMMON_ERR_INT" , + .hw_err = ssu_common_ecc_int + }, { + .desc_offset =3 , + .data_offset =0 , + .msg ="IGU_INT_STS" , + .hw_err = igu_int + }, { + .desc_offset =4 , + .data_offset =1 , + .msg ="PPP_MPF_ABNORMAL_INT_ST1" , + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset =4 , + .data_offset =3 , + .msg ="PPP_MPF_ABNORMAL_INT_ST3" , + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset =5 , + .data_offset =1 , + .msg ="PPU_MPF_ABNORMAL_INT_ST1" , + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset =5 , + .data_offset =2 , + .msg ="PPU_MPF_ABNORMAL_INT_ST2_RAS" , + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset =5 , + .data_offset =3 , + .msg ="PPU_MPF_ABNORMAL_INT_ST3" , + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset =6 , + .data_offset =0 , + .msg ="TM_SCH_RINT" , + .hw_err = tm_sch_int + }, { + .desc_offset =7 , + .data_offset =0 , + .msg ="QCN_FIFO_RINT" , + .hw_err = qcn_fifo_int + }, { + .desc_offset =7 , + .data_offset =1 , + .msg ="QCN_ECC_RINT" , + .hw_err = qcn_ecc_int + }, { + .desc_offset =9 , + .data_offset =0 , + .msg ="NCSI_ECC_INT_RPT" , + .hw_err = ncsi_ecc_int + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset =0 , - .data_offset =0 , - .msg ="SSU_PORT_BASED_ERR_INT_RAS" , - .hw_err = ssu_port_based_err_int }, - { .desc_offset =0 , - .data_offset =1 , - .msg ="SSU_FIFO_OVERFLOW_INT" , - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset =0 , - .data_offset =2 , - .msg ="SSU_ETS_TCG_INT" , - .hw_err = ssu_ets_tcg_int }, - { .desc_offset =1 , - .data_offset =0 , - .msg ="IGU_EGU_TNL_INT_STS" , - .hw_err = igu_egu_tnl_int }, - { .desc_offset =3 , - .data_offset =0 , - .msg ="PPU_PF_ABNORMAL_INT_ST_RAS" , - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =0 , + .data_offset =0 , + .msg ="SSU_PORT_BASED_ERR_INT_RAS" , + .hw_err = ssu_port_based_err_int + }, { + .desc_offset =0 , + .data_offset =1 , + .msg ="SSU_FIFO_OVERFLOW_INT" , + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset =0 , + .data_offset =2 , + .msg ="SSU_ETS_TCG_INT" , + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset =1 , + .data_offset =0 , + .msg ="IGU_EGU_TNL_INT_STS" , + .hw_err = igu_egu_tnl_int + }, { + .desc_offset =3 , + .data_offset =0 , + .msg ="PPU_PF_ABNORMAL_INT_ST_RAS" , + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset =1 , - .data_offset =0 , - .msg ="MAC_AFIFO_TNL_INT_R" , - .hw_err = mac_afifo_tnl_int }, - { .desc_offset =5 , - .data_offset =2 , - .msg ="PPU_MPF_ABNORMAL_INT_ST2_MSIX" , - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =1 , + .data_offset =0 , + .msg ="MAC_AFIFO_TNL_INT_R" , + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset =5 , + .data_offset =2 , + .msg ="PPU_MPF_ABNORMAL_INT_ST2_MSIX" , + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset =0 , - .data_offset =0 , - .msg ="SSU_PORT_BASED_ERR_INT_MSIX" , - .hw_err = ssu_port_based_pf_int }, - { .desc_offset =2 , - .data_offset =0 , - .msg ="PPP_PF_ABNORMAL_INT_ST0" , - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset =3 , - .data_offset =0 , - .msg ="PPU_PF_ABNORMAL_INT_ST_MSIX" , - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset =0 , - .data_offset =0 , - .msg =NULL , - .hw_err =NULL } + { + .desc_offset =0 , + .data_offset =0 , + .msg ="SSU_PORT_BASED_ERR_INT_MSIX" , + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset =2 , + .data_offset =0 , + .msg ="PPP_PF_ABNORMAL_INT_ST0" , + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset =3 , + .data_offset =0 , + .msg ="PPU_PF_ABNORMAL_INT_ST_MSIX" , + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset =0 , + .data_offset =0 , + .msg =NULL , + .hw_err =NULL + } };enum hns3_hw_err_type {
Signature · 1 line
2.7.4
PATCH v3 4/8 net/hns3: delete redundant xstats RAS statistics
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-)
drivers/net/hns3/hns3_ethdev.c +0 -2
@@ -5768,14 +5768,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val =hns3_read_dev (hw,HNS3_VECTOR0_OTER_EN_REG );if (hns3_get_bit (reg_val,HNS3_VECTOR0_IMP_RD_POISON_B )) {hns3_warn (hw,"Detected IMP RD poison!" ); -hns3_error_int_stats_add (hns,"IMP_RD_POISON_INT_STS" );hns3_set_bit (reg_val,HNS3_VECTOR0_IMP_RD_POISON_B ,0 );hns3_write_dev (hw,HNS3_VECTOR0_OTER_EN_REG , reg_val); }if (hns3_get_bit (reg_val,HNS3_VECTOR0_IMP_CMDQ_ERR_B )) {hns3_warn (hw,"Detected IMP CMDQ error!" ); -hns3_error_int_stats_add (hns,"CMDQ_MEM_ECC_INT_STS" );hns3_set_bit (reg_val,HNS3_VECTOR0_IMP_CMDQ_ERR_B ,0 );hns3_write_dev (hw,HNS3_VECTOR0_OTER_EN_REG , reg_val); }
drivers/net/hns3/hns3_ethdev.h +0 -35
@@ -561,38 +561,6 @@ struct hns3_hw {#define HNS3_FLAG_TC_BASE_SCH_MODE 1#define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { -uint64_t mac_afifo_tnl_int_cnt; -uint64_t ppu_mpf_abn_int_st2_msix_cnt; -uint64_t ssu_port_based_pf_int_cnt; -uint64_t ppp_pf_abnormal_int_cnt; -uint64_t ppu_pf_abnormal_int_msix_cnt; - -uint64_t imp_tcm_ecc_int_cnt; -uint64_t cmdq_mem_ecc_int_cnt; -uint64_t imp_rd_poison_int_cnt; -uint64_t tqp_int_ecc_int_cnt; -uint64_t msix_ecc_int_cnt; -uint64_t ssu_ecc_multi_bit_int_0_cnt; -uint64_t ssu_ecc_multi_bit_int_1_cnt; -uint64_t ssu_common_ecc_int_cnt; -uint64_t igu_int_cnt; -uint64_t ppp_mpf_abnormal_int_st1_cnt; -uint64_t ppp_mpf_abnormal_int_st3_cnt; -uint64_t ppu_mpf_abnormal_int_st1_cnt; -uint64_t ppu_mpf_abn_int_st2_ras_cnt; -uint64_t ppu_mpf_abnormal_int_st3_cnt; -uint64_t tm_sch_int_cnt; -uint64_t qcn_fifo_int_cnt; -uint64_t qcn_ecc_int_cnt; -uint64_t ncsi_ecc_int_cnt; -uint64_t ssu_port_based_err_int_cnt; -uint64_t ssu_fifo_overflow_int_cnt; -uint64_t ssu_ets_tcg_int_cnt; -uint64_t igu_egu_tnl_int_cnt; -uint64_t ppu_pf_abnormal_int_ras_cnt; -}; -/* vlan entry information. */ struct hns3_user_vlan_table {LIST_ENTRY (hns3_user_vlan_table) next;
@@ -738,9 +706,6 @@ struct hns3_pf {uint16_t max_umv_size;uint16_t used_umv_size; -/* Statistics information for abnormal interrupt */ -struct hns3_err_msix_intr_stats abn_int_stats; -bool support_sfp_query;uint32_t fec_mode;/* current FEC mode for ethdev */
drivers/net/hns3/hns3_intr.c +0 -1
@@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } -hns3_error_int_stats_add (hns, reg); } err++; }
drivers/net/hns3/hns3_stats.c +1 -99
154 lines not on this page · raw message
drivers/net/hns3/hns3_stats.h +0 -1
@@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,const uint64_t *ids, uint32_t size);int hns3_stats_reset (struct rte_eth_dev *dev); -void hns3_error_int_stats_add (struct hns3_adapter *hns,const char *err);int hns3_tqp_stats_init (struct hns3_hw *hw);void hns3_tqp_stats_uninit (struct hns3_hw *hw);int hns3_update_imissed_stats (struct hns3_hw *hw,bool is_clear);
Signature · 1 line
2.7.4
PATCH v3 5/8 net/hns3: support imissed stats for PF/VF
In reply to Min Hu (Connor)This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF.
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_cmd.h | 14 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 233 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-)
drivers/net/hns3/hns3_cmd.h +14 -0
@@ -111,6 +111,8 @@ enum hns3_opcode_type {HNS3_OPC_QUERY_DEV_SPECS =0x0050 , +HNS3_OPC_SSU_DROP_REG =0x0065 , +/* MAC command */ HNS3_OPC_CONFIG_MAC_MODE =0x0301 , HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
@@ -957,6 +959,18 @@ struct hns3_query_rpu_cmd {uint32_t rsv2[2 ]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { +uint8_t rxtx; +uint8_t rsv[3 ]; +uint32_t full_drop_cnt; +uint32_t part_drop_cnt; +uint32_t ncsi_full_drop_cnt; +uint32_t ncsi_part_drop_cnt; +uint32_t oq_glb_drop_cnt; +}; +#define HNS3_MAX_TQP_NUM_HIP08_PF 64#define HNS3_DEFAULT_TX_BUF 0x4000/* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000/* 1.03125M bytes */
drivers/net/hns3/hns3_ethdev.c +2 -0
@@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_2US ; hw->tso_mode =HNS3_TSO_SW_CAL_PSEUDO_H_CSUM ; hw->vlan_mode =HNS3_SW_SHIFT_AND_DISCARD_MODE ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE1 ; hw->min_tx_pkt_len =HNS3_HIP08_MIN_TX_PKT_LEN ; pf->tqp_config_mode =HNS3_FIXED_MAX_TQP_NUM_MODE ; hw->rss_info.ipv6_sctp_offload_supported = false;
@@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_1US ; hw->tso_mode =HNS3_TSO_HW_CAL_PSEUDO_H_CSUM ; hw->vlan_mode =HNS3_HW_SHIFT_AND_DISCARD_MODE ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE2 ; hw->min_tx_pkt_len =HNS3_HIP09_MIN_TX_PKT_LEN ; pf->tqp_config_mode =HNS3_FLEX_MAX_TQP_NUM_MODE ; hw->rss_info.ipv6_sctp_offload_supported = true;
drivers/net/hns3/hns3_ethdev.h +21 -0
@@ -426,6 +426,9 @@ struct hns3_queue_intr {#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 +struct hns3_hw {struct rte_eth_dev_data *data;void *io_base;
@@ -544,6 +547,24 @@ struct hns3_hw {* port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + +/* +* drop_stats_mode mode. +* value range: +* HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 +* +* - HNS3_PKTS_DROP_STATS_MODE1 +* This mode for kunpeng920. In this mode, port level imissed stats +* is supported. It only includes RPU drop stats. +* +* - HNS3_PKTS_DROP_STATS_MODE2 +* This mode for kunpeng930. In this mode, imissed stats and oerrors +* stats is supported. Function level imissed stats is supported. It +* includes RPU drop stats in VF, and includes both RPU drop stats +* and SSU drop stats in PF. Oerror stats is also supported in PF. +*/ +uint8_t drop_stats_mode; +uint8_t max_non_tso_bd_num;/* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg;
drivers/net/hns3/hns3_ethdev_vf.c +9 -0
@@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode =HNS3_INTR_MAPPING_VEC_RSV_ONE ; hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_2US ; hw->tso_mode =HNS3_TSO_SW_CAL_PSEUDO_H_CSUM ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE1 ; hw->min_tx_pkt_len =HNS3_HIP08_MIN_TX_PKT_LEN ; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode =HNS3_UNLIMIT_PROMISC_MODE ;
@@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode =HNS3_INTR_MAPPING_VEC_ALL ; hw->intr.gl_unit =HNS3_INTR_COALESCE_GL_UINT_1US ; hw->tso_mode =HNS3_TSO_HW_CAL_PSEUDO_H_CSUM ; + hw->drop_stats_mode =HNS3_PKTS_DROP_STATS_MODE2 ; hw->min_tx_pkt_len =HNS3_HIP09_MIN_TX_PKT_LEN ; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode =HNS3_LIMIT_PROMISC_MODE ;
@@ -1875,6 +1877,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev)if (ret) goto err_get_config; +/* Hardware statistics of imissed registers cleared. */ + ret =hns3_update_imissed_stats (hw, true); +if (ret) { +hns3_err (hw,"clear imissed stats failed, ret = %d" , ret); + goto err_set_tc_queue; + } + ret =hns3vf_set_tc_queue_mapping (hns, hw->tqps_num, hw->tqps_num);if (ret) {PMD_INIT_LOG (ERR ,"failed to set tc info, ret = %d." , ret);
drivers/net/hns3/hns3_regs.h +2 -0
@@ -36,6 +36,8 @@#define HNS3_GLOBAL_RESET_REG 0x20A00#define HNS3_FUN_RST_ING 0x20C00#define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004#define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008/* Vector0 register bits for reset */
drivers/net/hns3/hns3_stats.c +181 -52
325 lines not on this page · raw message
drivers/net/hns3/hns3_stats.h +1 -0
@@ -112,6 +112,7 @@ struct hns3_mac_stats {struct hns3_rx_missed_stats {uint64_t rpu_rx_drop_cnt; +uint64_t ssu_rx_drop_cnt; };/* store statistics names and its offset in stats structure */
Signature · 1 line
2.7.4
PATCH v3 6/8 net/hns3: support oerrors stats in PF
In reply to Min Hu (Connor)This patch added oerrors stats for PF in kunpeng930.
Signed-off-by Min Hu (Connor) <[email protected]>
--- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 61 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+)
drivers/net/hns3/hns3_ethdev.h +1 -0
@@ -443,6 +443,7 @@ struct hns3_hw {/* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats;struct hns3_rx_missed_stats imissed_stats; +uint64_t oerror_stats;uint32_t fw_version;uint16_t num_msi;
drivers/net/hns3/hns3_stats.c +61 -0
85 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v3 7/8 net/hns3: support query Tx descriptor status
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+)
doc/guides/nics/features/hns3.ini +1 -0
@@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y
doc/guides/nics/features/hns3_vf.ini +1 -0
@@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +1 -0
@@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; + eth_dev->tx_descriptor_status =NULL ;rte_free (eth_dev->process_private); eth_dev->process_private =NULL ;return ret;
drivers/net/hns3/hns3_ethdev_vf.c +1 -0
@@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; + eth_dev->tx_descriptor_status =NULL ;rte_free (eth_dev->process_private); eth_dev->process_private =NULL ;
drivers/net/hns3/hns3_rxtx.c +28 -0
@@ -4044,6 +4044,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst =hns3_get_rx_function (eth_dev); eth_dev->tx_pkt_burst =hns3_get_tx_function (eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; }else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
@@ -4256,6 +4257,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt)return -ENOTSUP ; } +int +hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset) +{ +volatile struct hns3_desc *txdp; +struct hns3_tx_queue *txq; +struct rte_eth_dev *dev; +uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; +if (offset >= txq->nb_tx_desc) +return -EINVAL ; + + dev = &rte_eth_devices[txq->port_id]; +if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) +return RTE_ETH_TX_DESC_UNAVAIL ; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; +if (txdp->tx.tp_fe_sc_vld_ra_ri &rte_cpu_to_le_16 (BIT (HNS3_TXD_VLD_B ))) +return RTE_ETH_TX_DESC_FULL ; +else +return RTE_ETH_TX_DESC_DONE ; +} +uint32_t hns3_rx_queue_count (struct rte_eth_dev *dev,uint16_t rx_queue_id) {
drivers/net/hns3/hns3_rxtx.h +1 -0
@@ -720,5 +720,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev);void hns3_restore_tqp_enable_state (struct hns3_hw *hw);int hns3_tx_done_cleanup (void *txq,uint32_t free_cnt);void hns3_enable_rxd_adv_layout (struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset);#endif /* _HNS3_RXTX_H_ */
Signature · 1 line
2.7.4
PATCH v3 8/8 net/hns3: support query Rx descriptor status
In reply to Min Hu (Connor)From: Hongbo Zheng <[email protected]>
Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor.
Signed-off-by Hongbo Zheng <[email protected]>
Signed-off-by Min Hu (Connor) <[email protected]>
--- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+)
doc/guides/nics/features/hns3.ini +1 -0
@@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y
doc/guides/nics/features/hns3_vf.ini +1 -0
@@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y
doc/guides/rel_notes/release_21_05.rst +1 -0
@@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.**
drivers/net/hns3/hns3_ethdev.c +1 -0
@@ -6772,6 +6772,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops =NULL ; eth_dev->rx_pkt_burst =NULL ; + eth_dev->rx_descriptor_status =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; eth_dev->tx_descriptor_status =NULL ;
drivers/net/hns3/hns3_ethdev_vf.c +1 -0
@@ -2915,6 +2915,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops =NULL ; eth_dev->rx_pkt_burst =NULL ; + eth_dev->rx_descriptor_status =NULL ; eth_dev->tx_pkt_burst =NULL ; eth_dev->tx_pkt_prepare =NULL ; eth_dev->tx_descriptor_status =NULL ;
drivers/net/hns3/hns3_rxtx.c +36 -0
@@ -4042,6 +4042,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)if (hns->hw.adapter_state ==HNS3_NIC_STARTED &&__atomic_load_n (&hns->hw.reset.resetting, __ATOMIC_RELAXED) ==0 ) { eth_dev->rx_pkt_burst =hns3_get_rx_function (eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst =hns3_get_tx_function (eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status;
@@ -4258,6 +4259,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) }int +hns3_dev_rx_descriptor_status (void *rx_queue,uint16_t offset) +{ +volatile struct hns3_desc *rxdp; +struct hns3_rx_queue *rxq; +struct rte_eth_dev *dev; +uint32_t bd_base_info; +uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; +if (offset >= rxq->nb_rx_desc) +return -EINVAL ; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info =rte_le_to_cpu_32 (rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; +if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { +if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) +return RTE_ETH_RX_DESC_UNAVAIL ; + }else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ +if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) +return RTE_ETH_RX_DESC_UNAVAIL ; + }else { +return RTE_ETH_RX_DESC_UNAVAIL ; + } + +if (!(bd_base_info &BIT (HNS3_RXD_VLD_B ))) +return RTE_ETH_RX_DESC_AVAIL ; +else +return RTE_ETH_RX_DESC_DONE ; +} + +int hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset) {volatile struct hns3_desc *txdp;
drivers/net/hns3/hns3_rxtx.h +1 -0
@@ -720,6 +720,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev);void hns3_restore_tqp_enable_state (struct hns3_hw *hw);int hns3_tx_done_cleanup (void *txq,uint32_t free_cnt);void hns3_enable_rxd_adv_layout (struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status (void *rx_queue,uint16_t offset);int hns3_dev_tx_descriptor_status (void *tx_queue,uint16_t offset);#endif /* _HNS3_RXTX_H_ */
Signature · 1 line
2.7.4