perf/x86/intel: Add Emerald Rapids
Subsystems (2)
PATCH 1/4 perf/x86/intel: Add Emerald Rapids
From: Kan Liang <[email protected]>
From core PMU's perspective, Emerald Rapids is the same as the Sapphire Rapids. The only difference is the event list, which will be supported in the perf tool later.
--- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/core.c +1 -0
@@ -6487,6 +6487,7 @@ __init int intel_pmu_init(void)break ;case INTEL_FAM6_SAPPHIRERAPIDS_X : +case INTEL_FAM6_EMERALDRAPIDS_X : pmem = true; x86_pmu.late_ack = true;memcpy (hw_cache_event_ids, spr_hw_cache_event_ids,sizeof (hw_cache_event_ids));
Signature · 1 line
2.35.1
PATCH 2/4 perf/x86/intel/cstate: Add Emerald Rapids
From: Kan Liang <[email protected]>
From the perspective of Intel cstate residency counters, Emerald Rapids is the same as the Sapphire Rapids and Ice Lake. Add Emerald Rapids model.
--- arch/x86/events/intel/cstate.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/cstate.c +1 -0
@@ -677,6 +677,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {X86_MATCH_INTEL_FAM6_MODEL (ICELAKE_X , &icx_cstates),X86_MATCH_INTEL_FAM6_MODEL (ICELAKE_D , &icx_cstates),X86_MATCH_INTEL_FAM6_MODEL (SAPPHIRERAPIDS_X , &icx_cstates), +X86_MATCH_INTEL_FAM6_MODEL (EMERALDRAPIDS_X , &icx_cstates),X86_MATCH_INTEL_FAM6_MODEL (TIGERLAKE_L , &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates),
Signature · 1 line
2.35.1
[tip: perf/urgent] perf/x86/intel/cstate: Add Emerald Rapids
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 5a8a05f165fb18d37526062419774d9088c2a9b9 Gitweb: https://git.kernel.org/tip/5a8a05f165fb18d37526062419774d9088c2a9b9 Author: Kan Liang <[email protected]> AuthorDate: Fri, 06 Jan 2023 08:04:47 -08:00 Committer: Ingo Molnar <[email protected]> CommitterDate: Wed, 18 Jan 2023 12:42:49 +01:00
perf/x86/intel/cstate: Add Emerald Rapids
Quoted 1 line
From the perspective of Intel cstate residency counters,
Emerald Rapids is the same as the Sapphire Rapids and Ice Lake. Add Emerald Rapids model.
--- arch/x86/events/intel/cstate.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/cstate.c +1 -0
@@ -677,6 +677,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {X86_MATCH_INTEL_FAM6_MODEL (ICELAKE_X , &icx_cstates),X86_MATCH_INTEL_FAM6_MODEL (ICELAKE_D , &icx_cstates),X86_MATCH_INTEL_FAM6_MODEL (SAPPHIRERAPIDS_X , &icx_cstates), +X86_MATCH_INTEL_FAM6_MODEL (EMERALDRAPIDS_X , &icx_cstates),X86_MATCH_INTEL_FAM6_MODEL (TIGERLAKE_L , &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates),
PATCH 3/4 perf/x86/msr: Add Emerald Rapids
In reply to [email protected]From: Kan Liang <[email protected]>
The same as Sapphire Rapids, the SMI_COUNT MSR is also supported on Emerald Rapids. Add Emerald Rapids model.
--- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/msr.c +1 -0
@@ -69,6 +69,7 @@ static bool test_intel(int idx, void *data)case INTEL_FAM6_BROADWELL_G :case INTEL_FAM6_BROADWELL_X :case INTEL_FAM6_SAPPHIRERAPIDS_X : +case INTEL_FAM6_EMERALDRAPIDS_X :case INTEL_FAM6_ATOM_SILVERMONT :case INTEL_FAM6_ATOM_SILVERMONT_D :
Signature · 1 line
2.35.1
[tip: perf/urgent] perf/x86/msr: Add Emerald Rapids
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 69ced4160969025821f2999ff92163ed26568f1c Gitweb: https://git.kernel.org/tip/69ced4160969025821f2999ff92163ed26568f1c Author: Kan Liang <[email protected]> AuthorDate: Fri, 06 Jan 2023 08:04:48 -08:00 Committer: Ingo Molnar <[email protected]> CommitterDate: Mon, 09 Jan 2023 12:00:52 +01:00
perf/x86/msr: Add Emerald Rapids
The same as Sapphire Rapids, the SMI_COUNT MSR is also supported on Emerald Rapids. Add Emerald Rapids model.
--- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/msr.c +1 -0
@@ -69,6 +69,7 @@ static bool test_intel(int idx, void *data)case INTEL_FAM6_BROADWELL_G :case INTEL_FAM6_BROADWELL_X :case INTEL_FAM6_SAPPHIRERAPIDS_X : +case INTEL_FAM6_EMERALDRAPIDS_X :case INTEL_FAM6_ATOM_SILVERMONT :case INTEL_FAM6_ATOM_SILVERMONT_D :
PATCH 4/4 perf/x86/intel/uncore: Add Emerald Rapids
In reply to [email protected]From: Kan Liang <[email protected]>
From the perspective of the uncore PMU, the new Emerald Rapids is the same as the Sapphire Rapids. The only difference is the event list, which will be supported in the perf tool later.
--- arch/x86/events/intel/uncore.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/uncore.c +1 -0
@@ -1833,6 +1833,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_P , &adl_uncore_init),X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_S , &adl_uncore_init),X86_MATCH_INTEL_FAM6_MODEL (SAPPHIRERAPIDS_X , &spr_uncore_init), +X86_MATCH_INTEL_FAM6_MODEL (EMERALDRAPIDS_X , &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init), {}, };
Signature · 1 line
2.35.1
[tip: perf/urgent] perf/x86/intel/uncore: Add Emerald Rapids
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 5268a2842066c227e6ccd94bac562f1e1000244f Gitweb: https://git.kernel.org/tip/5268a2842066c227e6ccd94bac562f1e1000244f Author: Kan Liang <[email protected]> AuthorDate: Fri, 06 Jan 2023 08:04:49 -08:00 Committer: Ingo Molnar <[email protected]> CommitterDate: Mon, 09 Jan 2023 12:00:58 +01:00
perf/x86/intel/uncore: Add Emerald Rapids
Quoted 1 line
From the perspective of the uncore PMU, the new Emerald Rapids is the
same as the Sapphire Rapids. The only difference is the event list, which will be supported in the perf tool later.
--- arch/x86/events/intel/uncore.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/uncore.c +1 -0
@@ -1833,6 +1833,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_P , &adl_uncore_init),X86_MATCH_INTEL_FAM6_MODEL (RAPTORLAKE_S , &adl_uncore_init),X86_MATCH_INTEL_FAM6_MODEL (SAPPHIRERAPIDS_X , &spr_uncore_init), +X86_MATCH_INTEL_FAM6_MODEL (EMERALDRAPIDS_X , &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init), {}, };
Hi Ingo,
It seems that only the last two patches of the series are merged into the tip.git perf/urgent branch.
Could you please take the first two patches as well? They similarly add the CPU model number for perf core driver and perf cstate driver.
Please let me know if you have any questions regarding the first two patches. If you want me to resend the patches, please let me know as well.
Thanks,
Kan
Quoted 23 lines · On 2023-01-06 11:04 a.m., [email protected] wrote:
From: Kan Liang <[email protected]>
From core PMU's perspective, Emerald Rapids is the same as the Sapphire Rapids. The only difference is the event list, which will be supported in the perf tool later.
Signed-off-by Kan Liang <[email protected]>--- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+)arch/x86/events/intel/core.c +1
-0@@ -6487,6 +6487,7 @@ __init int intel_pmu_init(void)break ;case INTEL_FAM6_SAPPHIRERAPIDS_X : +case INTEL_FAM6_EMERALDRAPIDS_X : pmem = true; x86_pmu.late_ack = true;memcpy (hw_cache_event_ids, spr_hw_cache_event_ids,sizeof (hw_cache_event_ids));
Quoted 7 lines · Liang, Kan
Hi Ingo,
It seems that only the last two patches of the series are merged into the tip.git perf/urgent branch.
Could you please take the first two patches as well? They similarly add the CPU model number for perf core driver and perf cstate driver.
Ok, done!
Thanks,
Ingo
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 6795e558e9cc6123c24e2100a2ebe88e58a792bc Gitweb: https://git.kernel.org/tip/6795e558e9cc6123c24e2100a2ebe88e58a792bc Author: Kan Liang <[email protected]> AuthorDate: Fri, 06 Jan 2023 08:04:46 -08:00 Committer: Ingo Molnar <[email protected]> CommitterDate: Wed, 18 Jan 2023 12:42:49 +01:00
perf/x86/intel: Add Emerald Rapids
Quoted 1 line
From core PMU's perspective, Emerald Rapids is the same as the Sapphire
Rapids. The only difference is the event list, which will be supported in the perf tool later.
--- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/events/intel/core.c +1 -0
@@ -6339,6 +6339,7 @@ __init int intel_pmu_init(void)break ;case INTEL_FAM6_SAPPHIRERAPIDS_X : +case INTEL_FAM6_EMERALDRAPIDS_X : pmem = true; x86_pmu.late_ack = true;memcpy (hw_cache_event_ids, spr_hw_cache_event_ids,sizeof (hw_cache_event_ids));