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arm64: dts: juno: Correct PCI IO window

PATCH New Jeremy Linton 5 participants 6 messages Nov 29, 2016 – Dec 1, 2016

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Jeremy Linton

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#0 lore raw

PATCH 1/1 arm64: dts: juno: Correct PCI IO window

The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.

Signed-off-by Jeremy Linton <[email protected]>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/arm/juno-base.dtsi +1 -1
index 334271a..7d3a2ac 100644
@@ -393,7 +393,7 @@
 		#address-cells = <3>;
 		#size-cells = <2>;
 		dma-coherent;
-		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
 			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 		#interrupt-cells = <1>;
Signature · 1 line
2.5.5
maintainer
#1 lore raw

PATCH 1/1 arm64: dts: juno: Correct PCI IO window

Quoted 6 lines · Jeremy Linton

The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.

Signed-off-by Jeremy Linton <[email protected]>

With the U-Boot patch that I have sent to the ML:

Tested-by Liviu Dudau <[email protected]>

also

Acked-by Liviu Dudau <[email protected]>

Best regards,
Liviu

Quoted 20 lines
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/arm/juno-base.dtsi +1 -1
index 334271a..7d3a2ac 100644
@@ -393,7 +393,7 @@
 		#address-cells = <3>;
 		#size-cells = <2>;
 		dma-coherent;
-		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
 			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 		#interrupt-cells = <1>;
Signature · 1 line
2.5.5
Signature · 8 lines
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
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#2 lore raw

PATCH 1/1 arm64: dts: juno: Correct PCI IO window

In reply to Jeremy Linton
Quoted 9 lines · Jeremy Linton

The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.

Signed-off-by Jeremy Linton <[email protected]>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by Lorenzo Pieralisi <[email protected]>
Quoted 16 lines
arch/arm64/boot/dts/arm/juno-base.dtsi +1 -1
index 334271a..7d3a2ac 100644
@@ -393,7 +393,7 @@
 		#address-cells = <3>;
 		#size-cells = <2>;
 		dma-coherent;
-		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
 			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 		#interrupt-cells = <1>;
Signature · 1 line
2.5.5
#3 lore raw

PATCH 1/1 arm64: dts: juno: Correct PCI IO window

In reply to Jeremy Linton

Hi Jeremy,

Quoted 5 lines · Jeremy Linton

The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.

I have another DT fix that I have asked ARM-SoC guys to pick up directly from the list. If that doesn't happen, I will send PR including both.

If that happens then we need to send this to them to be picked directly. At this point I want to wait for couple of days to avoid confusion.

Signature · 2 lines
Regards,
Sudeep
#4 lore raw

PATCH 1/1 arm64: dts: juno: Correct PCI IO window

Quoted 9 lines · CET Sudeep Holla

Hi Jeremy,

Quoted 5 lines · Jeremy Linton

The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.

Quoted 5 lines

I have another DT fix that I have asked ARM-SoC guys to pick up directly from the list. If that doesn't happen, I will send PR including both.

If that happens then we need to send this to them to be picked directly. At this point I want to wait for couple of days to avoid confusion.

I ended up taking the other one for v4.10, but this one seems more important so I applied it for v4.9.

Let me know if you disagree with the priorities, as I plan to send out the last 4.9 fixes pull request to Linus tomorrow.

Arnd

#5 lore raw

PATCH 1/1 arm64: dts: juno: Correct PCI IO window

Quoted 13 lines · Arnd Bergmann
Quoted 12 lines · CET Sudeep Holla

Hi Jeremy,

Quoted 5 lines · Jeremy Linton

The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.

I have another DT fix that I have asked ARM-SoC guys to pick up directly from the list. If that doesn't happen, I will send PR including both.

Quoted 9 lines
Quoted 2 lines

If that happens then we need to send this to them to be picked directly. At this point I want to wait for couple of days to avoid confusion.

I ended up taking the other one for v4.10, but this one seems more important so I applied it for v4.9.

Let me know if you disagree with the priorities, as I plan to send out the last 4.9 fixes pull request to Linus tomorrow.

No that's fine.

Signature · 2 lines
Regards,
Sudeep