iommu/io-pgtable-arm: Add support to use system cache
Subsystems (6)
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH v4 1/6 iommu/io-pgtable-arm: Add support to use system cache
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache.
--- drivers/iommu/io-pgtable-arm.c | 7 ++++++- include/linux/io-pgtable.h | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-)
drivers/iommu/io-pgtable-arm.c +6 -1
@@ -789,7 +789,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |IO_PGTABLE_QUIRK_NON_STRICT | -IO_PGTABLE_QUIRK_ARM_TTBR1 )) +IO_PGTABLE_QUIRK_ARM_TTBR1 | +IO_PGTABLE_QUIRK_SYS_CACHE ))return NULL ; data =arm_lpae_alloc_pgtable (cfg);
@@ -801,6 +802,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) tcr->sh =ARM_LPAE_TCR_SH_IS ; tcr->irgn =ARM_LPAE_TCR_RGN_WBWA ; tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; + }else if (cfg->quirks &IO_PGTABLE_QUIRK_SYS_CACHE ) { + tcr->sh =ARM_LPAE_TCR_SH_OS ; + tcr->irgn =ARM_LPAE_TCR_RGN_NC ; + tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; }else { tcr->sh =ARM_LPAE_TCR_SH_OS ; tcr->irgn =ARM_LPAE_TCR_RGN_NC ;
include/linux/io-pgtable.h +4 -0
@@ -86,6 +86,9 @@ struct io_pgtable_cfg {* * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table * for use in the upper half of a split address space. +* +* IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for +* the page table walker when using system cache. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
@@ -93,6 +96,7 @@ struct io_pgtable_cfg {#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) +#define IO_PGTABLE_QUIRK_SYS_CACHE BIT(6)unsigned long quirks;unsigned long pgsize_bitmap;unsigned int ias;
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
PATCH v4 1/6 iommu/io-pgtable-arm: Add support to use system cache
In reply to a message not in the archiveAdd a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache.
--- drivers/iommu/io-pgtable-arm.c | 7 ++++++- include/linux/io-pgtable.h | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-)
drivers/iommu/io-pgtable-arm.c +6 -1
@@ -789,7 +789,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |IO_PGTABLE_QUIRK_NON_STRICT | -IO_PGTABLE_QUIRK_ARM_TTBR1 )) +IO_PGTABLE_QUIRK_ARM_TTBR1 | +IO_PGTABLE_QUIRK_SYS_CACHE ))return NULL ; data =arm_lpae_alloc_pgtable (cfg);
@@ -801,6 +802,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) tcr->sh =ARM_LPAE_TCR_SH_IS ; tcr->irgn =ARM_LPAE_TCR_RGN_WBWA ; tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; + }else if (cfg->quirks &IO_PGTABLE_QUIRK_SYS_CACHE ) { + tcr->sh =ARM_LPAE_TCR_SH_OS ; + tcr->irgn =ARM_LPAE_TCR_RGN_NC ; + tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; }else { tcr->sh =ARM_LPAE_TCR_SH_OS ; tcr->irgn =ARM_LPAE_TCR_RGN_NC ;
include/linux/io-pgtable.h +4 -0
@@ -86,6 +86,9 @@ struct io_pgtable_cfg {* * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table * for use in the upper half of a split address space. +* +* IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for +* the page table walker when using system cache. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
@@ -93,6 +96,7 @@ struct io_pgtable_cfg {#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) +#define IO_PGTABLE_QUIRK_SYS_CACHE BIT(6)unsigned long quirks;unsigned long pgsize_bitmap;unsigned int ias;
Signature · 8 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v4 1/6 iommu/io-pgtable-arm: Add support to use system cache
In reply to a message not in the archiveAdd a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache.
--- drivers/iommu/io-pgtable-arm.c | 7 ++++++- include/linux/io-pgtable.h | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-)
drivers/iommu/io-pgtable-arm.c +6 -1
@@ -789,7 +789,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |IO_PGTABLE_QUIRK_NON_STRICT | -IO_PGTABLE_QUIRK_ARM_TTBR1 )) +IO_PGTABLE_QUIRK_ARM_TTBR1 | +IO_PGTABLE_QUIRK_SYS_CACHE ))return NULL ; data =arm_lpae_alloc_pgtable (cfg);
@@ -801,6 +802,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) tcr->sh =ARM_LPAE_TCR_SH_IS ; tcr->irgn =ARM_LPAE_TCR_RGN_WBWA ; tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; + }else if (cfg->quirks &IO_PGTABLE_QUIRK_SYS_CACHE ) { + tcr->sh =ARM_LPAE_TCR_SH_OS ; + tcr->irgn =ARM_LPAE_TCR_RGN_NC ; + tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; }else { tcr->sh =ARM_LPAE_TCR_SH_OS ; tcr->irgn =ARM_LPAE_TCR_RGN_NC ;
include/linux/io-pgtable.h +4 -0
@@ -86,6 +86,9 @@ struct io_pgtable_cfg {* * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table * for use in the upper half of a split address space. +* +* IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for +* the page table walker when using system cache. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
@@ -93,6 +96,7 @@ struct io_pgtable_cfg {#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) +#define IO_PGTABLE_QUIRK_SYS_CACHE BIT(6)unsigned long quirks;unsigned long pgsize_bitmap;unsigned int ias;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 1/6 iommu/io-pgtable-arm: Add support to use system cache
In reply to a message not in the archiveAdd a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the attributes set in TCR for the page table walker when using system cache.
--- drivers/iommu/io-pgtable-arm.c | 7 ++++++- include/linux/io-pgtable.h | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-)
drivers/iommu/io-pgtable-arm.c +6 -1
@@ -789,7 +789,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |IO_PGTABLE_QUIRK_NON_STRICT | -IO_PGTABLE_QUIRK_ARM_TTBR1 )) +IO_PGTABLE_QUIRK_ARM_TTBR1 | +IO_PGTABLE_QUIRK_SYS_CACHE ))return NULL ; data =arm_lpae_alloc_pgtable (cfg);
@@ -801,6 +802,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) tcr->sh =ARM_LPAE_TCR_SH_IS ; tcr->irgn =ARM_LPAE_TCR_RGN_WBWA ; tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; + }else if (cfg->quirks &IO_PGTABLE_QUIRK_SYS_CACHE ) { + tcr->sh =ARM_LPAE_TCR_SH_OS ; + tcr->irgn =ARM_LPAE_TCR_RGN_NC ; + tcr->orgn =ARM_LPAE_TCR_RGN_WBWA ; }else { tcr->sh =ARM_LPAE_TCR_SH_OS ; tcr->irgn =ARM_LPAE_TCR_RGN_NC ;
include/linux/io-pgtable.h +4 -0
@@ -86,6 +86,9 @@ struct io_pgtable_cfg {* * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table * for use in the upper half of a split address space. +* +* IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for +* the page table walker when using system cache. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
@@ -93,6 +96,7 @@ struct io_pgtable_cfg {#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) +#define IO_PGTABLE_QUIRK_SYS_CACHE BIT(6)unsigned long quirks;unsigned long pgsize_bitmap;unsigned int ias;
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 2/6 iommu/arm-smmu: Add domain attribute for system cache
In reply to a message not in the archiveAdd iommu domain attribute for using system cache aka last level cache by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache.
--- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + include/linux/iommu.h | 1 + 3 files changed, 19 insertions(+)
drivers/iommu/arm/arm-smmu/arm-smmu.c +17 -0
@@ -789,6 +789,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,if (smmu_domain->non_strict) pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_NON_STRICT ; +if (smmu_domain->sys_cache) + pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_SYS_CACHE ; + pgtbl_ops =alloc_io_pgtable_ops (fmt, &pgtbl_cfg, smmu_domain);if (!pgtbl_ops) { ret = -ENOMEM ;
@@ -1513,6 +1516,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE : *(int *)data = smmu_domain->non_strict;return 0 ; +case DOMAIN_ATTR_SYS_CACHE : + *((int *)data) = smmu_domain->sys_cache; +return 0 ;default :return -ENODEV ; }
@@ -1544,6 +1550,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,else smmu_domain->stage =ARM_SMMU_DOMAIN_S1 ;break ; +case DOMAIN_ATTR_SYS_CACHE : +if (smmu_domain->smmu) { + ret = -EPERM ; + goto out_unlock; + } + +if (*((int *)data)) + smmu_domain->sys_cache = true; +else + smmu_domain->sys_cache = false; +break ;default : ret = -ENODEV ; }
drivers/iommu/arm/arm-smmu/arm-smmu.h +1 -0
@@ -373,6 +373,7 @@ struct arm_smmu_domain {struct mutex init_mutex;/* Protects smmu pointer */ spinlock_t cb_lock;/* Serialises ATS1* ops and TLB syncs */ struct iommu_domain domain; +bool sys_cache; };struct arm_smmu_master_cfg {
include/linux/iommu.h +1 -0
@@ -118,6 +118,7 @@ enum iommu_attr {DOMAIN_ATTR_FSL_PAMUV1 ,DOMAIN_ATTR_NESTING ,/* two stages of translation */ DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE , +DOMAIN_ATTR_SYS_CACHE , DOMAIN_ATTR_MAX, };
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
PATCH v4 2/6 iommu/arm-smmu: Add domain attribute for system cache
In reply to a message not in the archiveAdd iommu domain attribute for using system cache aka last level cache by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache.
--- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + include/linux/iommu.h | 1 + 3 files changed, 19 insertions(+)
drivers/iommu/arm/arm-smmu/arm-smmu.c +17 -0
@@ -789,6 +789,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,if (smmu_domain->non_strict) pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_NON_STRICT ; +if (smmu_domain->sys_cache) + pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_SYS_CACHE ; + pgtbl_ops =alloc_io_pgtable_ops (fmt, &pgtbl_cfg, smmu_domain);if (!pgtbl_ops) { ret = -ENOMEM ;
@@ -1513,6 +1516,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE : *(int *)data = smmu_domain->non_strict;return 0 ; +case DOMAIN_ATTR_SYS_CACHE : + *((int *)data) = smmu_domain->sys_cache; +return 0 ;default :return -ENODEV ; }
@@ -1544,6 +1550,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,else smmu_domain->stage =ARM_SMMU_DOMAIN_S1 ;break ; +case DOMAIN_ATTR_SYS_CACHE : +if (smmu_domain->smmu) { + ret = -EPERM ; + goto out_unlock; + } + +if (*((int *)data)) + smmu_domain->sys_cache = true; +else + smmu_domain->sys_cache = false; +break ;default : ret = -ENODEV ; }
drivers/iommu/arm/arm-smmu/arm-smmu.h +1 -0
@@ -373,6 +373,7 @@ struct arm_smmu_domain {struct mutex init_mutex;/* Protects smmu pointer */ spinlock_t cb_lock;/* Serialises ATS1* ops and TLB syncs */ struct iommu_domain domain; +bool sys_cache; };struct arm_smmu_master_cfg {
include/linux/iommu.h +1 -0
@@ -118,6 +118,7 @@ enum iommu_attr {DOMAIN_ATTR_FSL_PAMUV1 ,DOMAIN_ATTR_NESTING ,/* two stages of translation */ DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE , +DOMAIN_ATTR_SYS_CACHE , DOMAIN_ATTR_MAX, };
Signature · 8 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v4 2/6 iommu/arm-smmu: Add domain attribute for system cache
In reply to a message not in the archiveAdd iommu domain attribute for using system cache aka last level cache by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache.
--- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + include/linux/iommu.h | 1 + 3 files changed, 19 insertions(+)
drivers/iommu/arm/arm-smmu/arm-smmu.c +17 -0
@@ -789,6 +789,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,if (smmu_domain->non_strict) pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_NON_STRICT ; +if (smmu_domain->sys_cache) + pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_SYS_CACHE ; + pgtbl_ops =alloc_io_pgtable_ops (fmt, &pgtbl_cfg, smmu_domain);if (!pgtbl_ops) { ret = -ENOMEM ;
@@ -1513,6 +1516,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE : *(int *)data = smmu_domain->non_strict;return 0 ; +case DOMAIN_ATTR_SYS_CACHE : + *((int *)data) = smmu_domain->sys_cache; +return 0 ;default :return -ENODEV ; }
@@ -1544,6 +1550,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,else smmu_domain->stage =ARM_SMMU_DOMAIN_S1 ;break ; +case DOMAIN_ATTR_SYS_CACHE : +if (smmu_domain->smmu) { + ret = -EPERM ; + goto out_unlock; + } + +if (*((int *)data)) + smmu_domain->sys_cache = true; +else + smmu_domain->sys_cache = false; +break ;default : ret = -ENODEV ; }
drivers/iommu/arm/arm-smmu/arm-smmu.h +1 -0
@@ -373,6 +373,7 @@ struct arm_smmu_domain {struct mutex init_mutex;/* Protects smmu pointer */ spinlock_t cb_lock;/* Serialises ATS1* ops and TLB syncs */ struct iommu_domain domain; +bool sys_cache; };struct arm_smmu_master_cfg {
include/linux/iommu.h +1 -0
@@ -118,6 +118,7 @@ enum iommu_attr {DOMAIN_ATTR_FSL_PAMUV1 ,DOMAIN_ATTR_NESTING ,/* two stages of translation */ DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE , +DOMAIN_ATTR_SYS_CACHE , DOMAIN_ATTR_MAX, };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 2/6 iommu/arm-smmu: Add domain attribute for system cache
In reply to a message not in the archiveAdd iommu domain attribute for using system cache aka last level cache by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache.
--- drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + include/linux/iommu.h | 1 + 3 files changed, 19 insertions(+)
drivers/iommu/arm/arm-smmu/arm-smmu.c +17 -0
@@ -789,6 +789,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,if (smmu_domain->non_strict) pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_NON_STRICT ; +if (smmu_domain->sys_cache) + pgtbl_cfg.quirks |=IO_PGTABLE_QUIRK_SYS_CACHE ; + pgtbl_ops =alloc_io_pgtable_ops (fmt, &pgtbl_cfg, smmu_domain);if (!pgtbl_ops) { ret = -ENOMEM ;
@@ -1513,6 +1516,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE : *(int *)data = smmu_domain->non_strict;return 0 ; +case DOMAIN_ATTR_SYS_CACHE : + *((int *)data) = smmu_domain->sys_cache; +return 0 ;default :return -ENODEV ; }
@@ -1544,6 +1550,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,else smmu_domain->stage =ARM_SMMU_DOMAIN_S1 ;break ; +case DOMAIN_ATTR_SYS_CACHE : +if (smmu_domain->smmu) { + ret = -EPERM ; + goto out_unlock; + } + +if (*((int *)data)) + smmu_domain->sys_cache = true; +else + smmu_domain->sys_cache = false; +break ;default : ret = -ENODEV ; }
drivers/iommu/arm/arm-smmu/arm-smmu.h +1 -0
@@ -373,6 +373,7 @@ struct arm_smmu_domain {struct mutex init_mutex;/* Protects smmu pointer */ spinlock_t cb_lock;/* Serialises ATS1* ops and TLB syncs */ struct iommu_domain domain; +bool sys_cache; };struct arm_smmu_master_cfg {
include/linux/iommu.h +1 -0
@@ -118,6 +118,7 @@ enum iommu_attr {DOMAIN_ATTR_FSL_PAMUV1 ,DOMAIN_ATTR_NESTING ,/* two stages of translation */ DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE , +DOMAIN_ATTR_SYS_CACHE , DOMAIN_ATTR_MAX, };
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 3/6 drm/msm: rearrange the gpu_rmw() function
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function.
--- drivers/gpu/drm/msm/msm_drv.c | 8 ++++++++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.h | 5 +---- 3 files changed, 10 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/msm_drv.c +8 -0
@@ -180,6 +180,14 @@ u32 msm_readl(const void __iomem *addr)return val; } +void msm_rmw (void __iomem *addr,u32 mask,u32 or) +{ +u32 val =msm_readl (addr); + + val &= ~mask; +msm_writel (val | or, addr); +} +struct msm_vblank_work {struct work_struct work;int crtc_id;
drivers/gpu/drm/msm/msm_drv.h +1 -0
@@ -419,6 +419,7 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, const char *dbgname);void msm_writel (u32 data,void __iomem *addr);u32 msm_readl (const void __iomem *addr); +void msm_rmw (void __iomem *addr,u32 mask,u32 or);struct msm_gpu_submitqueue ;int msm_submitqueue_init (struct drm_device *drm,struct msm_file_private *ctx);
drivers/gpu/drm/msm/msm_gpu.h +1 -4
@@ -245,10 +245,7 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)static inline void gpu_rmw (struct msm_gpu *gpu,u32 reg,u32 mask,u32 or) { -uint32_t val =gpu_read (gpu, reg); - - val &= ~mask; -gpu_write (gpu, reg, val | or); +msm_rmw (gpu->mmio + (reg <<2 ), mask, or); }static inline u64 gpu_read64 (struct msm_gpu *gpu,u32 lo,u32 hi)
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
PATCH v4 3/6 drm/msm: rearrange the gpu_rmw() function
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function.
--- drivers/gpu/drm/msm/msm_drv.c | 8 ++++++++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.h | 5 +---- 3 files changed, 10 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/msm_drv.c +8 -0
@@ -180,6 +180,14 @@ u32 msm_readl(const void __iomem *addr)return val; } +void msm_rmw (void __iomem *addr,u32 mask,u32 or) +{ +u32 val =msm_readl (addr); + + val &= ~mask; +msm_writel (val | or, addr); +} +struct msm_vblank_work {struct work_struct work;int crtc_id;
drivers/gpu/drm/msm/msm_drv.h +1 -0
@@ -419,6 +419,7 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, const char *dbgname);void msm_writel (u32 data,void __iomem *addr);u32 msm_readl (const void __iomem *addr); +void msm_rmw (void __iomem *addr,u32 mask,u32 or);struct msm_gpu_submitqueue ;int msm_submitqueue_init (struct drm_device *drm,struct msm_file_private *ctx);
drivers/gpu/drm/msm/msm_gpu.h +1 -4
@@ -245,10 +245,7 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)static inline void gpu_rmw (struct msm_gpu *gpu,u32 reg,u32 mask,u32 or) { -uint32_t val =gpu_read (gpu, reg); - - val &= ~mask; -gpu_write (gpu, reg, val | or); +msm_rmw (gpu->mmio + (reg <<2 ), mask, or); }static inline u64 gpu_read64 (struct msm_gpu *gpu,u32 lo,u32 hi)
Signature · 8 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v4 3/6 drm/msm: rearrange the gpu_rmw() function
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function.
--- drivers/gpu/drm/msm/msm_drv.c | 8 ++++++++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.h | 5 +---- 3 files changed, 10 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/msm_drv.c +8 -0
@@ -180,6 +180,14 @@ u32 msm_readl(const void __iomem *addr)return val; } +void msm_rmw (void __iomem *addr,u32 mask,u32 or) +{ +u32 val =msm_readl (addr); + + val &= ~mask; +msm_writel (val | or, addr); +} +struct msm_vblank_work {struct work_struct work;int crtc_id;
drivers/gpu/drm/msm/msm_drv.h +1 -0
@@ -419,6 +419,7 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, const char *dbgname);void msm_writel (u32 data,void __iomem *addr);u32 msm_readl (const void __iomem *addr); +void msm_rmw (void __iomem *addr,u32 mask,u32 or);struct msm_gpu_submitqueue ;int msm_submitqueue_init (struct drm_device *drm,struct msm_file_private *ctx);
drivers/gpu/drm/msm/msm_gpu.h +1 -4
@@ -245,10 +245,7 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)static inline void gpu_rmw (struct msm_gpu *gpu,u32 reg,u32 mask,u32 or) { -uint32_t val =gpu_read (gpu, reg); - - val &= ~mask; -gpu_write (gpu, reg, val | or); +msm_rmw (gpu->mmio + (reg <<2 ), mask, or); }static inline u64 gpu_read64 (struct msm_gpu *gpu,u32 lo,u32 hi)
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 3/6 drm/msm: rearrange the gpu_rmw() function
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function.
--- drivers/gpu/drm/msm/msm_drv.c | 8 ++++++++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.h | 5 +---- 3 files changed, 10 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/msm_drv.c +8 -0
@@ -180,6 +180,14 @@ u32 msm_readl(const void __iomem *addr)return val; } +void msm_rmw (void __iomem *addr,u32 mask,u32 or) +{ +u32 val =msm_readl (addr); + + val &= ~mask; +msm_writel (val | or, addr); +} +struct msm_vblank_work {struct work_struct work;int crtc_id;
drivers/gpu/drm/msm/msm_drv.h +1 -0
@@ -419,6 +419,7 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, const char *dbgname);void msm_writel (u32 data,void __iomem *addr);u32 msm_readl (const void __iomem *addr); +void msm_rmw (void __iomem *addr,u32 mask,u32 or);struct msm_gpu_submitqueue ;int msm_submitqueue_init (struct drm_device *drm,struct msm_file_private *ctx);
drivers/gpu/drm/msm/msm_gpu.h +1 -4
@@ -245,10 +245,7 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)static inline void gpu_rmw (struct msm_gpu *gpu,u32 reg,u32 mask,u32 or) { -uint32_t val =gpu_read (gpu, reg); - - val &= ~mask; -gpu_write (gpu, reg, val | or); +msm_rmw (gpu->mmio + (reg <<2 ), mask, or); }static inline u64 gpu_read64 (struct msm_gpu *gpu,u32 lo,u32 hi)
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 4/6 drm/msm/a6xx: Add support for using system cache(LLC)
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This talks to the core system cache driver to acquire the slice handles, configure the SCID's to those slices and activates and deactivates the slices upon GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use of the system cache to set the right TCR attributes. GPU then has the ability to override a few cacheability parameters which it does to override write-allocate to write-no-allocate as the GPU hardware does not benefit much from it.
DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache.
(saiprakash.ranjan: fix to set attr before device attach to iommu and rebase)
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++- 3 files changed, 107 insertions(+), 1 deletion(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +83 -0
@@ -9,6 +9,8 @@#include "a6xx_gmu.xml.h" #include <linux/devfreq.h> +#include <linux/bitfield.h> +#include <linux/soc/qcom/llcc-qcom.h> #define GPU_PAS_ID 13
@@ -969,6 +971,79 @@ static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL), }; +static void a6xx_llc_rmw (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 mask,u32 or) +{ +return msm_rmw (a6xx_gpu->llc_mmio + (reg <<2 ), mask, or); +} + +static void a6xx_llc_write (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 value) +{ +return msm_writel (value, a6xx_gpu->llc_mmio + (reg <<2 )); +} + +static void a6xx_llc_deactivate (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_deactivate (a6xx_gpu->llc_slice); +llcc_slice_deactivate (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_activate (struct a6xx_gpu *a6xx_gpu) +{ +u32 cntl1_regval =0 ; + +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + +if (!llcc_slice_activate (a6xx_gpu->llc_slice)) { +u32 gpu_scid =llcc_get_slice_id (a6xx_gpu->llc_slice); + + gpu_scid &=0x1f ; + cntl1_regval = (gpu_scid <<0 ) | (gpu_scid <<5 ) | (gpu_scid <<10 ) | + (gpu_scid <<15 ) | (gpu_scid <<20 ); + } + +if (!llcc_slice_activate (a6xx_gpu->htw_llc_slice)) { +u32 gpuhtw_scid =llcc_get_slice_id (a6xx_gpu->htw_llc_slice); + + gpuhtw_scid &=0x1f ; + cntl1_regval |=FIELD_PREP (GENMASK (29 ,25 ), gpuhtw_scid); + } + +if (cntl1_regval) { +/* +* Program the slice IDs for the various GPU blocks and GPU MMU +* pagetables +*/ +a6xx_llc_write (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 , cntl1_regval); + +/* +* Program cacheability overrides to not allocate cache lines on +* a write miss +*/ +a6xx_llc_rmw (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 ,0xF ,0x03 ); + } +} + +static void a6xx_llc_slices_destroy (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_putd (a6xx_gpu->llc_slice); +llcc_slice_putd (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_slices_init (struct platform_device *pdev, +struct a6xx_gpu *a6xx_gpu) +{ + a6xx_gpu->llc_mmio =msm_ioremap (pdev,"cx_mem" ,"gpu_cx" ); +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + + a6xx_gpu->llc_slice =llcc_slice_getd (LLCC_GPU ); + a6xx_gpu->htw_llc_slice =llcc_slice_getd (LLCC_GPUHTW ); + +if (IS_ERR (a6xx_gpu->llc_slice) &&IS_ERR (a6xx_gpu->htw_llc_slice)) + a6xx_gpu->llc_mmio =ERR_PTR (-EINVAL ); +} +static int a6xx_pm_resume (struct msm_gpu *gpu) {struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu);
@@ -985,6 +1060,8 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)msm_gpu_resume_devfreq (gpu); +a6xx_llc_activate (a6xx_gpu); +return 0 ; }
@@ -995,6 +1072,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)trace_msm_gpu_suspend (0 ); +a6xx_llc_deactivate (a6xx_gpu); +devfreq_suspend_device (gpu->devfreq.devfreq);return a6xx_gmu_stop (a6xx_gpu);
@@ -1033,6 +1112,8 @@ static void a6xx_destroy(struct msm_gpu *gpu)drm_gem_object_put (a6xx_gpu->sqe_bo); } +a6xx_llc_slices_destroy (a6xx_gpu); +a6xx_gmu_remove (a6xx_gpu);adreno_gpu_cleanup (adreno_gpu);
@@ -1132,6 +1213,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)if (adreno_is_a650 (adreno_gpu)) adreno_gpu->base.hw_apriv = true; +a6xx_llc_slices_init (pdev, a6xx_gpu); + ret =adreno_gpu_init (dev, pdev, adreno_gpu, &funcs,1 );if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));
drivers/gpu/drm/msm/adreno/a6xx_gpu.h +4 -0
@@ -22,6 +22,10 @@ struct a6xx_gpu {struct msm_file_private *cur_ctx;struct a6xx_gmu gmu; + +void __iomem *llc_mmio; +void *llc_slice; +void *htw_llc_slice; };#define to_a6xx_gpu (x) container_of(x, struct a6xx_gpu, base)
drivers/gpu/drm/msm/adreno/adreno_gpu.c +20 -1
@@ -16,6 +16,7 @@#include <linux/soc/qcom/mdt_loader.h> #include <soc/qcom/ocmem.h> #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "msm_gem.h" #include "msm_mmu.h"
@@ -190,10 +191,28 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) {struct iommu_domain *iommu =iommu_domain_alloc (&platform_bus_type); -struct msm_mmu *mmu =msm_iommu_new (&pdev->dev, iommu); +struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu); +struct a6xx_gpu *a6xx_gpu =to_a6xx_gpu (adreno_gpu);struct msm_gem_address_space *aspace; +struct msm_mmu *mmu;u64 start, size; +/* +* This allows GPU to set the bus attributes required to use system +* cache on behalf of the iommu page table walker. +*/ +if (!IS_ERR (a6xx_gpu->htw_llc_slice)) { +int gpu_htw_llc =1 ; + +iommu_domain_set_attr (iommu,DOMAIN_ATTR_SYS_CACHE , &gpu_htw_llc); + } + + mmu =msm_iommu_new (&pdev->dev, iommu); +if (IS_ERR (mmu)) { +iommu_domain_free (iommu); +return ERR_CAST (mmu); + } +/* * Use the aperture start or SZ_16M, whichever is greater. This will * ensure that we align with the allocated pagetable range while still
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
PATCH v4 4/6 drm/msm/a6xx: Add support for using system cache(LLC)
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This talks to the core system cache driver to acquire the slice handles, configure the SCID's to those slices and activates and deactivates the slices upon GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use of the system cache to set the right TCR attributes. GPU then has the ability to override a few cacheability parameters which it does to override write-allocate to write-no-allocate as the GPU hardware does not benefit much from it.
DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache.
(saiprakash.ranjan: fix to set attr before device attach to iommu and rebase)
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++- 3 files changed, 107 insertions(+), 1 deletion(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +83 -0
@@ -9,6 +9,8 @@#include "a6xx_gmu.xml.h" #include <linux/devfreq.h> +#include <linux/bitfield.h> +#include <linux/soc/qcom/llcc-qcom.h> #define GPU_PAS_ID 13
@@ -969,6 +971,79 @@ static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL), }; +static void a6xx_llc_rmw (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 mask,u32 or) +{ +return msm_rmw (a6xx_gpu->llc_mmio + (reg <<2 ), mask, or); +} + +static void a6xx_llc_write (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 value) +{ +return msm_writel (value, a6xx_gpu->llc_mmio + (reg <<2 )); +} + +static void a6xx_llc_deactivate (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_deactivate (a6xx_gpu->llc_slice); +llcc_slice_deactivate (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_activate (struct a6xx_gpu *a6xx_gpu) +{ +u32 cntl1_regval =0 ; + +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + +if (!llcc_slice_activate (a6xx_gpu->llc_slice)) { +u32 gpu_scid =llcc_get_slice_id (a6xx_gpu->llc_slice); + + gpu_scid &=0x1f ; + cntl1_regval = (gpu_scid <<0 ) | (gpu_scid <<5 ) | (gpu_scid <<10 ) | + (gpu_scid <<15 ) | (gpu_scid <<20 ); + } + +if (!llcc_slice_activate (a6xx_gpu->htw_llc_slice)) { +u32 gpuhtw_scid =llcc_get_slice_id (a6xx_gpu->htw_llc_slice); + + gpuhtw_scid &=0x1f ; + cntl1_regval |=FIELD_PREP (GENMASK (29 ,25 ), gpuhtw_scid); + } + +if (cntl1_regval) { +/* +* Program the slice IDs for the various GPU blocks and GPU MMU +* pagetables +*/ +a6xx_llc_write (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 , cntl1_regval); + +/* +* Program cacheability overrides to not allocate cache lines on +* a write miss +*/ +a6xx_llc_rmw (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 ,0xF ,0x03 ); + } +} + +static void a6xx_llc_slices_destroy (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_putd (a6xx_gpu->llc_slice); +llcc_slice_putd (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_slices_init (struct platform_device *pdev, +struct a6xx_gpu *a6xx_gpu) +{ + a6xx_gpu->llc_mmio =msm_ioremap (pdev,"cx_mem" ,"gpu_cx" ); +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + + a6xx_gpu->llc_slice =llcc_slice_getd (LLCC_GPU ); + a6xx_gpu->htw_llc_slice =llcc_slice_getd (LLCC_GPUHTW ); + +if (IS_ERR (a6xx_gpu->llc_slice) &&IS_ERR (a6xx_gpu->htw_llc_slice)) + a6xx_gpu->llc_mmio =ERR_PTR (-EINVAL ); +} +static int a6xx_pm_resume (struct msm_gpu *gpu) {struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu);
@@ -985,6 +1060,8 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)msm_gpu_resume_devfreq (gpu); +a6xx_llc_activate (a6xx_gpu); +return 0 ; }
@@ -995,6 +1072,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)trace_msm_gpu_suspend (0 ); +a6xx_llc_deactivate (a6xx_gpu); +devfreq_suspend_device (gpu->devfreq.devfreq);return a6xx_gmu_stop (a6xx_gpu);
@@ -1033,6 +1112,8 @@ static void a6xx_destroy(struct msm_gpu *gpu)drm_gem_object_put (a6xx_gpu->sqe_bo); } +a6xx_llc_slices_destroy (a6xx_gpu); +a6xx_gmu_remove (a6xx_gpu);adreno_gpu_cleanup (adreno_gpu);
@@ -1132,6 +1213,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)if (adreno_is_a650 (adreno_gpu)) adreno_gpu->base.hw_apriv = true; +a6xx_llc_slices_init (pdev, a6xx_gpu); + ret =adreno_gpu_init (dev, pdev, adreno_gpu, &funcs,1 );if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));
drivers/gpu/drm/msm/adreno/a6xx_gpu.h +4 -0
@@ -22,6 +22,10 @@ struct a6xx_gpu {struct msm_file_private *cur_ctx;struct a6xx_gmu gmu; + +void __iomem *llc_mmio; +void *llc_slice; +void *htw_llc_slice; };#define to_a6xx_gpu (x) container_of(x, struct a6xx_gpu, base)
drivers/gpu/drm/msm/adreno/adreno_gpu.c +20 -1
@@ -16,6 +16,7 @@#include <linux/soc/qcom/mdt_loader.h> #include <soc/qcom/ocmem.h> #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "msm_gem.h" #include "msm_mmu.h"
@@ -190,10 +191,28 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) {struct iommu_domain *iommu =iommu_domain_alloc (&platform_bus_type); -struct msm_mmu *mmu =msm_iommu_new (&pdev->dev, iommu); +struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu); +struct a6xx_gpu *a6xx_gpu =to_a6xx_gpu (adreno_gpu);struct msm_gem_address_space *aspace; +struct msm_mmu *mmu;u64 start, size; +/* +* This allows GPU to set the bus attributes required to use system +* cache on behalf of the iommu page table walker. +*/ +if (!IS_ERR (a6xx_gpu->htw_llc_slice)) { +int gpu_htw_llc =1 ; + +iommu_domain_set_attr (iommu,DOMAIN_ATTR_SYS_CACHE , &gpu_htw_llc); + } + + mmu =msm_iommu_new (&pdev->dev, iommu); +if (IS_ERR (mmu)) { +iommu_domain_free (iommu); +return ERR_CAST (mmu); + } +/* * Use the aperture start or SZ_16M, whichever is greater. This will * ensure that we align with the allocated pagetable range while still
Signature · 8 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v4 4/6 drm/msm/a6xx: Add support for using system cache(LLC)
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This talks to the core system cache driver to acquire the slice handles, configure the SCID's to those slices and activates and deactivates the slices upon GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use of the system cache to set the right TCR attributes. GPU then has the ability to override a few cacheability parameters which it does to override write-allocate to write-no-allocate as the GPU hardware does not benefit much from it.
DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache.
(saiprakash.ranjan: fix to set attr before device attach to iommu and rebase)
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++- 3 files changed, 107 insertions(+), 1 deletion(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +83 -0
@@ -9,6 +9,8 @@#include "a6xx_gmu.xml.h" #include <linux/devfreq.h> +#include <linux/bitfield.h> +#include <linux/soc/qcom/llcc-qcom.h> #define GPU_PAS_ID 13
@@ -969,6 +971,79 @@ static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL), }; +static void a6xx_llc_rmw (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 mask,u32 or) +{ +return msm_rmw (a6xx_gpu->llc_mmio + (reg <<2 ), mask, or); +} + +static void a6xx_llc_write (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 value) +{ +return msm_writel (value, a6xx_gpu->llc_mmio + (reg <<2 )); +} + +static void a6xx_llc_deactivate (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_deactivate (a6xx_gpu->llc_slice); +llcc_slice_deactivate (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_activate (struct a6xx_gpu *a6xx_gpu) +{ +u32 cntl1_regval =0 ; + +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + +if (!llcc_slice_activate (a6xx_gpu->llc_slice)) { +u32 gpu_scid =llcc_get_slice_id (a6xx_gpu->llc_slice); + + gpu_scid &=0x1f ; + cntl1_regval = (gpu_scid <<0 ) | (gpu_scid <<5 ) | (gpu_scid <<10 ) | + (gpu_scid <<15 ) | (gpu_scid <<20 ); + } + +if (!llcc_slice_activate (a6xx_gpu->htw_llc_slice)) { +u32 gpuhtw_scid =llcc_get_slice_id (a6xx_gpu->htw_llc_slice); + + gpuhtw_scid &=0x1f ; + cntl1_regval |=FIELD_PREP (GENMASK (29 ,25 ), gpuhtw_scid); + } + +if (cntl1_regval) { +/* +* Program the slice IDs for the various GPU blocks and GPU MMU +* pagetables +*/ +a6xx_llc_write (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 , cntl1_regval); + +/* +* Program cacheability overrides to not allocate cache lines on +* a write miss +*/ +a6xx_llc_rmw (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 ,0xF ,0x03 ); + } +} + +static void a6xx_llc_slices_destroy (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_putd (a6xx_gpu->llc_slice); +llcc_slice_putd (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_slices_init (struct platform_device *pdev, +struct a6xx_gpu *a6xx_gpu) +{ + a6xx_gpu->llc_mmio =msm_ioremap (pdev,"cx_mem" ,"gpu_cx" ); +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + + a6xx_gpu->llc_slice =llcc_slice_getd (LLCC_GPU ); + a6xx_gpu->htw_llc_slice =llcc_slice_getd (LLCC_GPUHTW ); + +if (IS_ERR (a6xx_gpu->llc_slice) &&IS_ERR (a6xx_gpu->htw_llc_slice)) + a6xx_gpu->llc_mmio =ERR_PTR (-EINVAL ); +} +static int a6xx_pm_resume (struct msm_gpu *gpu) {struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu);
@@ -985,6 +1060,8 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)msm_gpu_resume_devfreq (gpu); +a6xx_llc_activate (a6xx_gpu); +return 0 ; }
@@ -995,6 +1072,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)trace_msm_gpu_suspend (0 ); +a6xx_llc_deactivate (a6xx_gpu); +devfreq_suspend_device (gpu->devfreq.devfreq);return a6xx_gmu_stop (a6xx_gpu);
@@ -1033,6 +1112,8 @@ static void a6xx_destroy(struct msm_gpu *gpu)drm_gem_object_put (a6xx_gpu->sqe_bo); } +a6xx_llc_slices_destroy (a6xx_gpu); +a6xx_gmu_remove (a6xx_gpu);adreno_gpu_cleanup (adreno_gpu);
@@ -1132,6 +1213,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)if (adreno_is_a650 (adreno_gpu)) adreno_gpu->base.hw_apriv = true; +a6xx_llc_slices_init (pdev, a6xx_gpu); + ret =adreno_gpu_init (dev, pdev, adreno_gpu, &funcs,1 );if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));
drivers/gpu/drm/msm/adreno/a6xx_gpu.h +4 -0
@@ -22,6 +22,10 @@ struct a6xx_gpu {struct msm_file_private *cur_ctx;struct a6xx_gmu gmu; + +void __iomem *llc_mmio; +void *llc_slice; +void *htw_llc_slice; };#define to_a6xx_gpu (x) container_of(x, struct a6xx_gpu, base)
drivers/gpu/drm/msm/adreno/adreno_gpu.c +20 -1
@@ -16,6 +16,7 @@#include <linux/soc/qcom/mdt_loader.h> #include <soc/qcom/ocmem.h> #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "msm_gem.h" #include "msm_mmu.h"
@@ -190,10 +191,28 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) {struct iommu_domain *iommu =iommu_domain_alloc (&platform_bus_type); -struct msm_mmu *mmu =msm_iommu_new (&pdev->dev, iommu); +struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu); +struct a6xx_gpu *a6xx_gpu =to_a6xx_gpu (adreno_gpu);struct msm_gem_address_space *aspace; +struct msm_mmu *mmu;u64 start, size; +/* +* This allows GPU to set the bus attributes required to use system +* cache on behalf of the iommu page table walker. +*/ +if (!IS_ERR (a6xx_gpu->htw_llc_slice)) { +int gpu_htw_llc =1 ; + +iommu_domain_set_attr (iommu,DOMAIN_ATTR_SYS_CACHE , &gpu_htw_llc); + } + + mmu =msm_iommu_new (&pdev->dev, iommu); +if (IS_ERR (mmu)) { +iommu_domain_free (iommu); +return ERR_CAST (mmu); + } +/* * Use the aperture start or SZ_16M, whichever is greater. This will * ensure that we align with the allocated pagetable range while still
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
A message that is not in the archive (sent off-list or not yet received): 010101747d912d9f-c8050b8d-1e81-4be0-ac35-b221f657b490-000000@us-west-2.amazonses.com
Robin Murphy
reviewerRe: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
Quoted 2 lines · Sai Prakash Ranjan
There are few places in arm-smmu-impl where there are extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to visually delineate distinct groups of definitions. I suppose it won't be to everyone's taste :/
Quoted 3 lines
and while at it fix the
checkpatch warning for space required before the open parenthesis.
That one, however, was not ;)
BTW am I supposed to have received 3 copies of everything? Because I did...
Robin.
Quoted 36 lines
Signed-off-by Sai Prakash Ranjan <[email protected]>--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +1
-3@@ -19,7 +19,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {static int arm_smmu_gr0_ns (int offset) { -switch (offset) { +switch (offset) {case ARM_SMMU_GR0_sCR0:case ARM_SMMU_GR0_sACR:case ARM_SMMU_GR0_sGFSR:@@ -54,7 +54,6 @@ static const struct arm_smmu_impl calxeda_impl = { .write_reg = arm_smmu_write_ns, }; -struct cavium_smmu {struct arm_smmu_device smmu;u32 id_base;@@ -110,7 +109,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmreturn &cs->smmu; } -#define ARM_MMU500_ACTLR_CPRE (1 << 1)#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c static const struct arm_smmu_impl mrvl_mmu500_impl = { · line 200
Quoted 7 lines
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +0
-1@@ -197,7 +195,6 @@ static const struct arm_smmu_impl mrvl_mmu500_impl = { .reset = arm_mmu500_reset, }; -struct arm_smmu_device *arm_smmu_impl_init (struct arm_smmu_device *smmu) {const struct device_node *np = smmu->dev->of_node;
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Will Deacon
maintainerRe: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Will
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Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
Robin Murphy
reviewerRe: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
Quoted 10 lines · Sai Prakash Ranjan
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Actually on closer inspection it appears to be "correct" behaviour. I'm still subscribed to LAKML and the IOMMU list on this account, but normally Office 365 deduplicates so aggressively that I have rules set up to copy list mails that I'm cc'ed on back to my inbox, in case they arrive first and cause the direct copy to get eaten - apparently there's something unique about your email setup that manages to defeat the deduplicator and make it deliver all 3 copies intact... :/
Robin.
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dri-devel mailing list
[email protected]
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Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
Quoted 12 lines · Robin Murphy
Quoted 10 lines · Sai Prakash Ranjan
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Quoted 8 lines
Actually on closer inspection it appears to be "correct" behaviour. I'm still subscribed to LAKML and the IOMMU list on this account, but normally Office 365 deduplicates so aggressively that I have rules set up to copy list mails that I'm cc'ed on back to my inbox, in case they arrive first and cause the direct copy to get eaten - apparently there's something unique about your email setup that manages to defeat the deduplicator and make it deliver all 3 copies intact... :/
No changes in my local setup atleast, but in the past we have had cases with codeaurora mail acting weird or it could be my vpn, will have to check.
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 12 lines · Robin Murphy
Quoted 10 lines · Sai Prakash Ranjan
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Quoted 8 lines
Actually on closer inspection it appears to be "correct" behaviour. I'm still subscribed to LAKML and the IOMMU list on this account, but normally Office 365 deduplicates so aggressively that I have rules set up to copy list mails that I'm cc'ed on back to my inbox, in case they arrive first and cause the direct copy to get eaten - apparently there's something unique about your email setup that manages to defeat the deduplicator and make it deliver all 3 copies intact... :/
No changes in my local setup atleast, but in the past we have had cases with codeaurora mail acting weird or it could be my vpn, will have to check.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 12 lines · Robin Murphy
Quoted 10 lines · Sai Prakash Ranjan
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Quoted 8 lines
Actually on closer inspection it appears to be "correct" behaviour. I'm still subscribed to LAKML and the IOMMU list on this account, but normally Office 365 deduplicates so aggressively that I have rules set up to copy list mails that I'm cc'ed on back to my inbox, in case they arrive first and cause the direct copy to get eaten - apparently there's something unique about your email setup that manages to defeat the deduplicator and make it deliver all 3 copies intact... :/
No changes in my local setup atleast, but in the past we have had cases with codeaurora mail acting weird or it could be my vpn, will have to check.
Thanks,
Sai
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 12 lines · Robin Murphy
Quoted 10 lines · Sai Prakash Ranjan
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Quoted 8 lines
Actually on closer inspection it appears to be "correct" behaviour. I'm still subscribed to LAKML and the IOMMU list on this account, but normally Office 365 deduplicates so aggressively that I have rules set up to copy list mails that I'm cc'ed on back to my inbox, in case they arrive first and cause the direct copy to get eaten - apparently there's something unique about your email setup that manages to defeat the deduplicator and make it deliver all 3 copies intact... :/
No changes in my local setup atleast, but in the past we have had cases with codeaurora mail acting weird or it could be my vpn, will have to check.
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
A message that is not in the archive (sent off-list or not yet received): [email protected]
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
Quoted 22 lines · Sai Prakash Ranjan
Quoted 12 lines · Robin Murphy
Quoted 10 lines · Sai Prakash Ranjan
Quoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Quoted 8 lines
Actually on closer inspection it appears to be "correct" behaviour. I'm still subscribed to LAKML and the IOMMU list on this account, but normally Office 365 deduplicates so aggressively that I have rules set up to copy list mails that I'm cc'ed on back to my inbox, in case they arrive first and cause the direct copy to get eaten - apparently there's something unique about your email setup that manages to defeat the deduplicator and make it deliver all 3 copies intact... :/
Quoted 4 lines
No changes in my local setup atleast, but in the past we have had cases with codeaurora mail acting weird or it could be my vpn, will have to check.
This was an issue with codeaurora servers and I am told that it is fixed now.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Will DeaconQuoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Will DeaconQuoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Thanks,
Sai
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Will DeaconQuoted 5 lines · Will Deacon
Quoted 1 line · Robin Murphy
BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent this once and there are no recent changes to any of my configs, I'll check it further.
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 8 lines · Robin Murphy
Quoted 2 lines · Sai Prakash Ranjan
There are few places in arm-smmu-impl where there are extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to visually delineate distinct groups of definitions. I suppose it won't be to everyone's taste :/
Ah ok, I thought it was not intentional, I can drop it.
Quoted 6 lines
Quoted 3 lines
and while at it fix the
checkpatch warning for space required before the open parenthesis.That one, however, was not ;)
I'll keep this one.
Quoted 2 lines
BTW am I supposed to have received 3 copies of everything? Because I did...
Ugh no, I just sent it once but something seems to have gone wrong. Apologies again if you receive this message also multiple times. I'll check further what's going wrong with my setup.
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 8 lines · Robin Murphy
Quoted 2 lines · Sai Prakash Ranjan
There are few places in arm-smmu-impl where there are extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to visually delineate distinct groups of definitions. I suppose it won't be to everyone's taste :/
Ah ok, I thought it was not intentional, I can drop it.
Quoted 6 lines
Quoted 3 lines
and while at it fix the
checkpatch warning for space required before the open parenthesis.That one, however, was not ;)
I'll keep this one.
Quoted 2 lines
BTW am I supposed to have received 3 copies of everything? Because I did...
Ugh no, I just sent it once but something seems to have gone wrong. Apologies again if you receive this message also multiple times. I'll check further what's going wrong with my setup.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 8 lines · Robin Murphy
Quoted 2 lines · Sai Prakash Ranjan
There are few places in arm-smmu-impl where there are extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to visually delineate distinct groups of definitions. I suppose it won't be to everyone's taste :/
Ah ok, I thought it was not intentional, I can drop it.
Quoted 6 lines
Quoted 3 lines
and while at it fix the
checkpatch warning for space required before the open parenthesis.That one, however, was not ;)
I'll keep this one.
Quoted 2 lines
BTW am I supposed to have received 3 copies of everything? Because I did...
Ugh no, I just sent it once but something seems to have gone wrong. Apologies again if you receive this message also multiple times. I'll check further what's going wrong with my setup.
Thanks,
Sai
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to Robin MurphyQuoted 8 lines · Robin Murphy
Quoted 2 lines · Sai Prakash Ranjan
There are few places in arm-smmu-impl where there are extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to visually delineate distinct groups of definitions. I suppose it won't be to everyone's taste :/
Ah ok, I thought it was not intentional, I can drop it.
Quoted 6 lines
Quoted 3 lines
and while at it fix the
checkpatch warning for space required before the open parenthesis.That one, however, was not ;)
I'll keep this one.
Quoted 2 lines
BTW am I supposed to have received 3 copies of everything? Because I did...
Ugh no, I just sent it once but something seems to have gone wrong. Apologies again if you receive this message also multiple times. I'll check further what's going wrong with my setup.
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 4/6 drm/msm/a6xx: Add support for using system cache(LLC)
In reply to a message not in the archiveFrom: Sharat Masetty <[email protected]>
The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This talks to the core system cache driver to acquire the slice handles, configure the SCID's to those slices and activates and deactivates the slices upon GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use of the system cache to set the right TCR attributes. GPU then has the ability to override a few cacheability parameters which it does to override write-allocate to write-no-allocate as the GPU hardware does not benefit much from it.
DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the IOMMU driver to set the right attributes to cache the hardware pagetables into the system cache.
(saiprakash.ranjan: fix to set attr before device attach to iommu and rebase)
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 ++++++- 3 files changed, 107 insertions(+), 1 deletion(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +83 -0
@@ -9,6 +9,8 @@#include "a6xx_gmu.xml.h" #include <linux/devfreq.h> +#include <linux/bitfield.h> +#include <linux/soc/qcom/llcc-qcom.h> #define GPU_PAS_ID 13
@@ -969,6 +971,79 @@ static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL), }; +static void a6xx_llc_rmw (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 mask,u32 or) +{ +return msm_rmw (a6xx_gpu->llc_mmio + (reg <<2 ), mask, or); +} + +static void a6xx_llc_write (struct a6xx_gpu *a6xx_gpu,u32 reg,u32 value) +{ +return msm_writel (value, a6xx_gpu->llc_mmio + (reg <<2 )); +} + +static void a6xx_llc_deactivate (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_deactivate (a6xx_gpu->llc_slice); +llcc_slice_deactivate (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_activate (struct a6xx_gpu *a6xx_gpu) +{ +u32 cntl1_regval =0 ; + +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + +if (!llcc_slice_activate (a6xx_gpu->llc_slice)) { +u32 gpu_scid =llcc_get_slice_id (a6xx_gpu->llc_slice); + + gpu_scid &=0x1f ; + cntl1_regval = (gpu_scid <<0 ) | (gpu_scid <<5 ) | (gpu_scid <<10 ) | + (gpu_scid <<15 ) | (gpu_scid <<20 ); + } + +if (!llcc_slice_activate (a6xx_gpu->htw_llc_slice)) { +u32 gpuhtw_scid =llcc_get_slice_id (a6xx_gpu->htw_llc_slice); + + gpuhtw_scid &=0x1f ; + cntl1_regval |=FIELD_PREP (GENMASK (29 ,25 ), gpuhtw_scid); + } + +if (cntl1_regval) { +/* +* Program the slice IDs for the various GPU blocks and GPU MMU +* pagetables +*/ +a6xx_llc_write (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 , cntl1_regval); + +/* +* Program cacheability overrides to not allocate cache lines on +* a write miss +*/ +a6xx_llc_rmw (a6xx_gpu,REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 ,0xF ,0x03 ); + } +} + +static void a6xx_llc_slices_destroy (struct a6xx_gpu *a6xx_gpu) +{ +llcc_slice_putd (a6xx_gpu->llc_slice); +llcc_slice_putd (a6xx_gpu->htw_llc_slice); +} + +static void a6xx_llc_slices_init (struct platform_device *pdev, +struct a6xx_gpu *a6xx_gpu) +{ + a6xx_gpu->llc_mmio =msm_ioremap (pdev,"cx_mem" ,"gpu_cx" ); +if (IS_ERR (a6xx_gpu->llc_mmio)) +return ; + + a6xx_gpu->llc_slice =llcc_slice_getd (LLCC_GPU ); + a6xx_gpu->htw_llc_slice =llcc_slice_getd (LLCC_GPUHTW ); + +if (IS_ERR (a6xx_gpu->llc_slice) &&IS_ERR (a6xx_gpu->htw_llc_slice)) + a6xx_gpu->llc_mmio =ERR_PTR (-EINVAL ); +} +static int a6xx_pm_resume (struct msm_gpu *gpu) {struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu);
@@ -985,6 +1060,8 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)msm_gpu_resume_devfreq (gpu); +a6xx_llc_activate (a6xx_gpu); +return 0 ; }
@@ -995,6 +1072,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)trace_msm_gpu_suspend (0 ); +a6xx_llc_deactivate (a6xx_gpu); +devfreq_suspend_device (gpu->devfreq.devfreq);return a6xx_gmu_stop (a6xx_gpu);
@@ -1033,6 +1112,8 @@ static void a6xx_destroy(struct msm_gpu *gpu)drm_gem_object_put (a6xx_gpu->sqe_bo); } +a6xx_llc_slices_destroy (a6xx_gpu); +a6xx_gmu_remove (a6xx_gpu);adreno_gpu_cleanup (adreno_gpu);
@@ -1132,6 +1213,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)if (adreno_is_a650 (adreno_gpu)) adreno_gpu->base.hw_apriv = true; +a6xx_llc_slices_init (pdev, a6xx_gpu); + ret =adreno_gpu_init (dev, pdev, adreno_gpu, &funcs,1 );if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));
drivers/gpu/drm/msm/adreno/a6xx_gpu.h +4 -0
@@ -22,6 +22,10 @@ struct a6xx_gpu {struct msm_file_private *cur_ctx;struct a6xx_gmu gmu; + +void __iomem *llc_mmio; +void *llc_slice; +void *htw_llc_slice; };#define to_a6xx_gpu (x) container_of(x, struct a6xx_gpu, base)
drivers/gpu/drm/msm/adreno/adreno_gpu.c +20 -1
@@ -16,6 +16,7 @@#include <linux/soc/qcom/mdt_loader.h> #include <soc/qcom/ocmem.h> #include "adreno_gpu.h" +#include "a6xx_gpu.h" #include "msm_gem.h" #include "msm_mmu.h"
@@ -190,10 +191,28 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) {struct iommu_domain *iommu =iommu_domain_alloc (&platform_bus_type); -struct msm_mmu *mmu =msm_iommu_new (&pdev->dev, iommu); +struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu); +struct a6xx_gpu *a6xx_gpu =to_a6xx_gpu (adreno_gpu);struct msm_gem_address_space *aspace; +struct msm_mmu *mmu;u64 start, size; +/* +* This allows GPU to set the bus attributes required to use system +* cache on behalf of the iommu page table walker. +*/ +if (!IS_ERR (a6xx_gpu->htw_llc_slice)) { +int gpu_htw_llc =1 ; + +iommu_domain_set_attr (iommu,DOMAIN_ATTR_SYS_CACHE , &gpu_htw_llc); + } + + mmu =msm_iommu_new (&pdev->dev, iommu); +if (IS_ERR (mmu)) { +iommu_domain_free (iommu); +return ERR_CAST (mmu); + } +/* * Use the aperture start or SZ_16M, whichever is greater. This will * ensure that we align with the allocated pagetable range while still
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 5/6 iommu: arm-smmu-impl: Use table to list QCOM implementations
In reply to a message not in the archiveUse table and of_match_node() to match qcom implementation instead of multiple of_device_compatible() calls for each QCOM SMMU implementation.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +8 -4
@@ -9,6 +9,13 @@#include "arm-smmu.h" +static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { + { .compatible ="qcom,sc7180-smmu-500" }, + { .compatible ="qcom,sdm845-smmu-500" }, + { .compatible ="qcom,sm8150-smmu-500" }, + { .compatible ="qcom,sm8250-smmu-500" }, + { } +};static int arm_smmu_gr0_ns (int offset) {
@@ -217,10 +224,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)if (of_device_is_compatible (np,"nvidia,tegra194-smmu" ))return nvidia_smmu_impl_init (smmu); -if (of_device_is_compatible (np,"qcom,sdm845-smmu-500" ) || -of_device_is_compatible (np,"qcom,sc7180-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8150-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8250-smmu-500" )) +if (of_match_node (qcom_smmu_impl_of_match, np))return qcom_smmu_impl_init (smmu);if (of_device_is_compatible (smmu->dev->of_node,"qcom,adreno-smmu" ))
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
PATCH v4 5/6 iommu: arm-smmu-impl: Use table to list QCOM implementations
In reply to a message not in the archiveUse table and of_match_node() to match qcom implementation instead of multiple of_device_compatible() calls for each QCOM SMMU implementation.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +8 -4
@@ -9,6 +9,13 @@#include "arm-smmu.h" +static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { + { .compatible ="qcom,sc7180-smmu-500" }, + { .compatible ="qcom,sdm845-smmu-500" }, + { .compatible ="qcom,sm8150-smmu-500" }, + { .compatible ="qcom,sm8250-smmu-500" }, + { } +};static int arm_smmu_gr0_ns (int offset) {
@@ -217,10 +224,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)if (of_device_is_compatible (np,"nvidia,tegra194-smmu" ))return nvidia_smmu_impl_init (smmu); -if (of_device_is_compatible (np,"qcom,sdm845-smmu-500" ) || -of_device_is_compatible (np,"qcom,sc7180-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8150-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8250-smmu-500" )) +if (of_match_node (qcom_smmu_impl_of_match, np))return qcom_smmu_impl_init (smmu);if (of_device_is_compatible (smmu->dev->of_node,"qcom,adreno-smmu" ))
Signature · 8 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v4 5/6 iommu: arm-smmu-impl: Use table to list QCOM implementations
In reply to a message not in the archiveUse table and of_match_node() to match qcom implementation instead of multiple of_device_compatible() calls for each QCOM SMMU implementation.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +8 -4
@@ -9,6 +9,13 @@#include "arm-smmu.h" +static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { + { .compatible ="qcom,sc7180-smmu-500" }, + { .compatible ="qcom,sdm845-smmu-500" }, + { .compatible ="qcom,sm8150-smmu-500" }, + { .compatible ="qcom,sm8250-smmu-500" }, + { } +};static int arm_smmu_gr0_ns (int offset) {
@@ -217,10 +224,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)if (of_device_is_compatible (np,"nvidia,tegra194-smmu" ))return nvidia_smmu_impl_init (smmu); -if (of_device_is_compatible (np,"qcom,sdm845-smmu-500" ) || -of_device_is_compatible (np,"qcom,sc7180-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8150-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8250-smmu-500" )) +if (of_match_node (qcom_smmu_impl_of_match, np))return qcom_smmu_impl_init (smmu);if (of_device_is_compatible (smmu->dev->of_node,"qcom,adreno-smmu" ))
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 5/6 iommu: arm-smmu-impl: Use table to list QCOM implementations
In reply to a message not in the archiveUse table and of_match_node() to match qcom implementation instead of multiple of_device_compatible() calls for each QCOM SMMU implementation.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +8 -4
@@ -9,6 +9,13 @@#include "arm-smmu.h" +static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { + { .compatible ="qcom,sc7180-smmu-500" }, + { .compatible ="qcom,sdm845-smmu-500" }, + { .compatible ="qcom,sm8150-smmu-500" }, + { .compatible ="qcom,sm8250-smmu-500" }, + { } +};static int arm_smmu_gr0_ns (int offset) {
@@ -217,10 +224,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)if (of_device_is_compatible (np,"nvidia,tegra194-smmu" ))return nvidia_smmu_impl_init (smmu); -if (of_device_is_compatible (np,"qcom,sdm845-smmu-500" ) || -of_device_is_compatible (np,"qcom,sc7180-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8150-smmu-500" ) || -of_device_is_compatible (np,"qcom,sm8250-smmu-500" )) +if (of_match_node (qcom_smmu_impl_of_match, np))return qcom_smmu_impl_init (smmu);if (of_device_is_compatible (smmu->dev->of_node,"qcom,adreno-smmu" ))
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v4 6/6 iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to a message not in the archiveThere are few places in arm-smmu-impl where there are extra blank lines, remove them and while at it fix the checkpatch warning for space required before the open parenthesis.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +1 -4
@@ -19,7 +19,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {static int arm_smmu_gr0_ns (int offset) { -switch (offset) { +switch (offset) {case ARM_SMMU_GR0_sCR0:case ARM_SMMU_GR0_sACR:case ARM_SMMU_GR0_sGFSR:
@@ -54,7 +54,6 @@ static const struct arm_smmu_impl calxeda_impl = { .write_reg = arm_smmu_write_ns, }; -struct cavium_smmu {struct arm_smmu_device smmu;u32 id_base;
@@ -110,7 +109,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmreturn &cs->smmu; } -#define ARM_MMU500_ACTLR_CPRE (1 << 1)#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
@@ -197,7 +195,6 @@ static const struct arm_smmu_impl mrvl_mmu500_impl = { .reset = arm_mmu500_reset, }; -struct arm_smmu_device *arm_smmu_impl_init (struct arm_smmu_device *smmu) {const struct device_node *np = smmu->dev->of_node;
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
PATCH v4 6/6 iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to a message not in the archiveThere are few places in arm-smmu-impl where there are extra blank lines, remove them and while at it fix the checkpatch warning for space required before the open parenthesis.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +1 -4
@@ -19,7 +19,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {static int arm_smmu_gr0_ns (int offset) { -switch (offset) { +switch (offset) {case ARM_SMMU_GR0_sCR0:case ARM_SMMU_GR0_sACR:case ARM_SMMU_GR0_sGFSR:
@@ -54,7 +54,6 @@ static const struct arm_smmu_impl calxeda_impl = { .write_reg = arm_smmu_write_ns, }; -struct cavium_smmu {struct arm_smmu_device smmu;u32 id_base;
@@ -110,7 +109,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmreturn &cs->smmu; } -#define ARM_MMU500_ACTLR_CPRE (1 << 1)#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
@@ -197,7 +195,6 @@ static const struct arm_smmu_impl mrvl_mmu500_impl = { .reset = arm_mmu500_reset, }; -struct arm_smmu_device *arm_smmu_impl_init (struct arm_smmu_device *smmu) {const struct device_node *np = smmu->dev->of_node;
Signature · 8 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v4 6/6 iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to a message not in the archiveThere are few places in arm-smmu-impl where there are extra blank lines, remove them and while at it fix the checkpatch warning for space required before the open parenthesis.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +1 -4
@@ -19,7 +19,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {static int arm_smmu_gr0_ns (int offset) { -switch (offset) { +switch (offset) {case ARM_SMMU_GR0_sCR0:case ARM_SMMU_GR0_sACR:case ARM_SMMU_GR0_sGFSR:
@@ -54,7 +54,6 @@ static const struct arm_smmu_impl calxeda_impl = { .write_reg = arm_smmu_write_ns, }; -struct cavium_smmu {struct arm_smmu_device smmu;u32 id_base;
@@ -110,7 +109,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmreturn &cs->smmu; } -#define ARM_MMU500_ACTLR_CPRE (1 << 1)#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
@@ -197,7 +195,6 @@ static const struct arm_smmu_impl mrvl_mmu500_impl = { .reset = arm_mmu500_reset, }; -struct arm_smmu_device *arm_smmu_impl_init (struct arm_smmu_device *smmu) {const struct device_node *np = smmu->dev->of_node;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 6/6 iommu: arm-smmu-impl: Remove unwanted extra blank lines
In reply to a message not in the archiveThere are few places in arm-smmu-impl where there are extra blank lines, remove them and while at it fix the checkpatch warning for space required before the open parenthesis.
--- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +1 -4
@@ -19,7 +19,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {static int arm_smmu_gr0_ns (int offset) { -switch (offset) { +switch (offset) {case ARM_SMMU_GR0_sCR0:case ARM_SMMU_GR0_sACR:case ARM_SMMU_GR0_sGFSR:
@@ -54,7 +54,6 @@ static const struct arm_smmu_impl calxeda_impl = { .write_reg = arm_smmu_write_ns, }; -struct cavium_smmu {struct arm_smmu_device smmu;u32 id_base;
@@ -110,7 +109,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmreturn &cs->smmu; } -#define ARM_MMU500_ACTLR_CPRE (1 << 1)#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
@@ -197,7 +195,6 @@ static const struct arm_smmu_impl mrvl_mmu500_impl = { .reset = arm_mmu500_reset, }; -struct arm_smmu_device *arm_smmu_impl_init (struct arm_smmu_device *smmu) {const struct device_node *np = smmu->dev->of_node;
Signature · 7 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
A message that is not in the archive (sent off-list or not yet received): 3b1beb6cf6a34a44b0ecff9ec5a2105b5ff91bd4.1599832685.git.saiprakash.ranjan@codeaurora.org
Will Deacon
maintainerQuoted 3 lines · Sai Prakash Ranjan
Add a quirk
IO_PGTABLE_QUIRK_SYS_CACHEto override the attributes set in TCR for the page table walker when using system cache.
I wonder if the panfrost folks can reuse this for the issue discussed over at:
https://lore.kernel.org/r/[email protected]
However, Sai, your email setup went wrong when you posted this so you probably need to repost now that you have that fixed.
Will
Robin Murphy
reviewerQuoted 9 lines · Will Deacon
Quoted 3 lines · Sai Prakash Ranjan
Add a quirk
IO_PGTABLE_QUIRK_SYS_CACHEto override the attributes set in TCR for the page table walker when using system cache.I wonder if the panfrost folks can reuse this for the issue discussed over at:
Isn't this all hinged around the outer cacheability attribute, rather than shareability (since these are nominally NC mappings and thus already properly Osh)? The Panfrost issue is just about shareability domains being a bit wonky; the cacheability attributes there are actually reasonably normal (other than not having a non-cacheable type at all, only a choice of allocation policies...)
Robin.
Quoted 9 lines
However, Sai, your email setup went wrong when you posted this so you probably need to repost now that you have that fixed.
Will
_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu
Will Deacon
maintainerQuoted 9 lines · Robin Murphy
Quoted 8 lines · Will Deacon
Quoted 3 lines · Sai Prakash Ranjan
Add a quirk
IO_PGTABLE_QUIRK_SYS_CACHEto override the attributes set in TCR for the page table walker when using system cache.I wonder if the panfrost folks can reuse this for the issue discussed over at:
Quoted 8 lines
Quoted 1 line
Isn't this all hinged around the outer cacheability attribute, rather than shareability (since these are nominally NC mappings and thus already properly Osh)? The Panfrost issue is just about shareability domains being a bit wonky; the cacheability attributes there are actually reasonably normal (other than not having a non-cacheable type at all, only a choice of allocation policies...)
Hmm, yes, this quirk _also_ changes the cacheability settings which isn't what we need. It's a bit grotty having two different ways to configure these TCR bits (i.e. a quirk and a format), but at least the mali format rejects all of the quirks so I suppose it's not the end of the world.
Will
Hi Will,
Quoted 5 lines · Will Deacon
Quoted 3 lines · Sai Prakash Ranjan
Add a quirk
IO_PGTABLE_QUIRK_SYS_CACHEto override the attributes set in TCR for the page table walker when using system cache.
Quoted 8 lines
I wonder if the panfrost folks can reuse this for the issue discussed over at:
https://lore.kernel.org/r/[email protected]
However, Sai, your email setup went wrong when you posted this so you probably need to repost now that you have that fixed.
I have sent a v5 [1] now since I had to drop cleanup of blank lines as Robin said it was intentional and also had to rebase over new gpu changes since it moves pretty fast.
[1] https://lore.kernel.org/patchwork/cover/1310000/
Thanks,
Sai
Signature · 6 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu