pinctrl: meson: add support for the Meson8m2 SoC

The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b (such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins get an additional function. Four of these are Ethernet RXD2, RXD3, TXD2 and TXD3 (GPIOZ_0..GPIOZ_3) which are required when the board uses an RGMII PHY. GPIODV_24 and GPIODV_25 provide "VGA" support on Meson8, which doesn't seem to be supported on Meson8m2 anymore.
The other 4 are GPIOH_9 (reg 3 bit 19), CARD_4 (reg 8 bit 8), CARD_5 (reg 8 bit 7) and GPIOY_3 (reg 3 bit 11). Their function is currently unknown.

The AOBUS pins seem to be identical on Meson8 and Meson8m2. However, since there's no official documentation I decided to add a new compatible string.

Martin Blumenstingl (3):
dt-bindings: pinctrl: meson: add support for the Meson8m2 SoC
pinctrl: meson: meson8: add support for the Meson8m2 SoC
pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals

 .../bindings/pinctrl/meson,pinctrl.txt        |  2 ++
 drivers/pinctrl/meson/pinctrl-meson8.c        | 23 +++++++++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

2.17.0

The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b (such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins get an additional function (four of these are Ethernet RXD2, RXD3, TXD2 and TXD3 which are required when the board uses an RGMII PHY). The AOBUS pins seem to be identical on Meson8 and Meson8m2.

---
 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 ++
 1 file changed, 2 insertions(+)

index 2c12f9789116..54ecb8ab7788 100644
@@ -3,8 +3,10 @@
 Required properties for the root node:
  - compatible: one of "amlogic,meson8-cbus-pinctrl"
 		      "amlogic,meson8b-cbus-pinctrl"
+		      "amlogic,meson8m2-cbus-pinctrl"
 		      "amlogic,meson8-aobus-pinctrl"
 		      "amlogic,meson8b-aobus-pinctrl"
+		      "amlogic,meson8m2-aobus-pinctrl"
 		      "amlogic,meson-gxbb-periphs-pinctrl"
 		      "amlogic,meson-gxbb-aobus-pinctrl"
 		      "amlogic,meson-gxl-periphs-pinctrl"

2.17.0

Patch applied with Rob's and Kevin's ACKs.

Yours,
Linus Walleij

Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins, no other differences were found so far).
Add the new compatible strings for Meson8m2 to the existing Meson8 driver so we don't have to duplicate the whole driver.

---
 drivers/pinctrl/meson/pinctrl-meson8.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

index 49c7ce03547b..086082aeb796 100644
@@ -1,5 +1,5 @@
 /*
- * Pin controller and GPIO driver for Amlogic Meson8.
+ * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
  *
  * Copyright (C) 2014 Beniamino Galvani <[email protected]>
  *

@@ -1080,6 +1080,14 @@ static const struct of_device_id meson8_pinctrl_dt_match[] = {
 		.compatible = "amlogic,meson8-aobus-pinctrl",
 		.data = &meson8_aobus_pinctrl_data,
 	},
+	{
+		.compatible = "amlogic,meson8m2-cbus-pinctrl",
+		.data = &meson8_cbus_pinctrl_data,
+	},
+	{
+		.compatible = "amlogic,meson8m2-aobus-pinctrl",
+		.data = &meson8_aobus_pinctrl_data,
+	},
 	{ },
 };
 

2.17.0

Patch applied with Kevin's ACK.

Yours,
Linus Walleij

These are only available on the Meson8m2 SoC (which uses the same DesignWare Ethernet MAC as Meson8b).
The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII PHYs or the RGMII TX clock (as far as we know the frequency is controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP block).

---
 drivers/pinctrl/meson/pinctrl-meson8.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

index 086082aeb796..c6d79315218f 100644
@@ -299,6 +299,10 @@ static const unsigned int spi_mosi_1_pins[]	= { GPIOZ_12 };
 static const unsigned int spi_miso_1_pins[]	= { GPIOZ_13 };
 static const unsigned int spi_ss2_1_pins[]	= { GPIOZ_14 };
 
+static const unsigned int eth_txd3_pins[]	= { GPIOZ_0 };
+static const unsigned int eth_txd2_pins[]	= { GPIOZ_1 };
+static const unsigned int eth_rxd3_pins[]	= { GPIOZ_2 };
+static const unsigned int eth_rxd2_pins[]	= { GPIOZ_3 };
 static const unsigned int eth_tx_clk_50m_pins[]	= { GPIOZ_4 };
 static const unsigned int eth_tx_en_pins[]	= { GPIOZ_5 };
 static const unsigned int eth_txd1_pins[]	= { GPIOZ_6 };

@@ -650,6 +654,12 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
 	GROUP(eth_mdio,		6,	6),
 	GROUP(eth_mdc,		6,	5),
 
+	/* NOTE: the following four groups are only available on Meson8m2: */
+	GROUP(eth_rxd2,		6,	3),
+	GROUP(eth_rxd3,		6,	2),
+	GROUP(eth_txd2,		6,	1),
+	GROUP(eth_txd3,		6,	0),
+
 	GROUP(i2c_sda_a0,	5,	31),
 	GROUP(i2c_sck_a0,	5,	30),
 

@@ -877,7 +887,8 @@ static const char * const spi_groups[] = {
 static const char * const ethernet_groups[] = {
 	"eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
 	"eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
-	"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
+	"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
+	"eth_rxd3", "eth_txd2", "eth_txd3"
 };
 
 static const char * const i2c_a_groups[] = {

2.17.0

Patch applied with Kevin's ACK.

Yours,
Linus Walleij