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ARM: shmobile: rcar-gen2: Add CPG Clock Domain

PATCH Superseded Geert Uytterhoeven 7 participants 15 messages Mar 18, 2015 – Apr 1, 2015

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

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Geert Uytterhoeven

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#0 lore raw

cover ARM: shmobile: rcar-gen2: Add CPG Clock Domain

	Hi,

This RFC patch series adds Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock are tagged in DT with a proper "power-domains" property. Drivers for devices with multiple clocks (notably du and rcar-sound) still have to manage their (multiple module) clocks themselves.

Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c is disabled when running on an R-Car Gen2 SoC with genpd support.

Compared to the legacy default PM domain hack, the CPG Clock Domain has several advantages:
- It only affects on-SoC devices, not all platform devices,
- It only affects the on-SoC devices we want, as specified in DT,
- Allmost all module clocks of all on-SoC devices (barring devices needed for wake-up[*]) are now gated during s2ram, saving more power.

Here's a list of all devices in the CPG Clock Domain on r8a7791:

root at koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
cpg_clocks on

    /devices/platform/e61c0000.interrupt-controller     active
    /devices/platform/e60b0000.i2c                      suspended
    /devices/platform/ffca0000.timer                    suspended
    /devices/platform/e6050000.gpio                     active
    /devices/platform/e6051000.gpio                     active
    /devices/platform/e6052000.gpio                     active
    /devices/platform/e6053000.gpio                     active
    /devices/platform/e6054000.gpio                     active
    /devices/platform/e6055000.gpio                     active
    /devices/platform/e6055400.gpio                     active
    /devices/platform/e6055800.gpio                     active
    /devices/platform/ee090000.pci                      active
    /devices/platform/ee0d0000.pci                      active
    /devices/platform/fe000000.pcie                     unsupported
    /devices/platform/e6700000.dma-controller           active
    /devices/platform/e6720000.dma-controller           active
    /devices/platform/ec700000.dma-controller           active
    /devices/platform/ec720000.dma-controller           suspended
    /devices/platform/e6e60000.serial                   active
    /devices/platform/e6e68000.serial                   active
    /devices/platform/ee300000.sata                     unsupported
    /devices/platform/e6b10000.spi                      suspended
    /devices/platform/e6e20000.spi                      suspended
    /devices/platform/ee700000.ethernet                 active
    /devices/platform/e6530000.i2c                      suspended
    /devices/platform/e6ef1000.video                    suspended
    /devices/platform/e61f0000.thermal                  active
    /devices/platform/ee100000.sd                       active
    /devices/platform/ee140000.sd                       active
    /devices/platform/ee160000.sd                       active

root at koelsch:~#

Logically, the CPG Clock Domain operates on the SoC CPG/MSTP block. As there's no single device node in DT representing this block (there are separate device nodes for the CPG and for the individual MSTP clocks), I bound the logic to the CPG device node.
Perhaps this is something we should change for future SoCs?

As usual when involving clocks and/or PM Domains, the DTS changes depend stricly on the driver change. The final patch must be applied last.

The DTS changes also depend on the series "[PATCH 0/5] ARM: shmobile:
Add INTC-SYS clock to device tree" I've just sent.

This was tested on r8a7791/koelsch.

Thanks for your comments!

[*] GPIO wake-up requires "[PATCH 0/3] gpio: rcar: Fix wake up using gpio-keys with PM domain").

Geert Uytterhoeven (5):
[RFC] clk: shmobile: rcar-gen2: Add CPG Clock Domain support [RFC] ARM: shmobile: r8a7790 dtsi: Add CPG Clock Domain [RFC] ARM: shmobile: r8a7791 dtsi: Add CPG Clock Domain [RFC] ARM: shmobile: r8a7794 dtsi: Add CPG Clock Domain
drivers: sh: Disable PM runtime for multi-platform R-Car Gen2 with
genpd

 .../clock/renesas,rcar-gen2-cpg-clocks.txt         | 26 ++++++-
 arch/arm/boot/dts/r8a7790.dtsi                     | 77 +++++++++++++++++++--
 arch/arm/boot/dts/r8a7791.dtsi                     | 80 ++++++++++++++++++++--
 arch/arm/boot/dts/r8a7794.dtsi                     | 29 ++++++++
 arch/arm/mach-shmobile/Kconfig                     |  1 +
 drivers/clk/shmobile/clk-rcar-gen2.c               | 63 +++++++++++++++++
 drivers/sh/pm_runtime.c                            | 10 +--
 7 files changed, 268 insertions(+), 18 deletions(-)
Signature · 12 lines
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds
author maintainer
#1 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>
---
 .../clock/renesas,rcar-gen2-cpg-clocks.txt         | 26 ++++++++-
 arch/arm/mach-shmobile/Kconfig                     |  1 +
 drivers/clk/shmobile/clk-rcar-gen2.c               | 63 ++++++++++++++++++++++
 3 files changed, 88 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +24 -2
index b02944fba9de4f86..fc013f225a348929 100644
@@ -2,6 +2,8 @@
 
 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
 and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 

@@ -20,10 +22,18 @@ Required Properties:
   - clock-output-names: The names of the clocks. Supported clocks are "main",
     "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
     "adsp"
+  - #power-domain-cells: Must be 0
 
+SoC devices that are part of the CPG Clock Domain and can be power-managed
+through their primary clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
 
-Example
--------
+
+Examples
+--------
+
+  - CPG device node:
 
 	cpg_clocks: cpg_clocks at e6150000 {
 		compatible = "renesas,r8a7790-cpg-clocks",

@@ -34,4 +44,16 @@ Example
 		clock-output-names = "main", "pll0, "pll1", "pll3",
 				     "lb", "qspi", "sdh", "sd0", "sd1", "z",
 				     "rcan", "adsp";
+		#power-domain-cells = <0>;
+	};
+
+
+  - CPG Clock Domain member node:
+
+	thermal at e61f0000 {
+		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+		power-domains = <&cpg_clocks>;
 	};
arch/arm/mach-shmobile/Kconfig +1 -0
index 0fb484221c90e0eb..048101a3253c52de 100644
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
 
 config PM_RCAR
 	bool
+	select PM_GENERIC_DOMAINS
 
 config PM_RMOBILE
 	bool
drivers/clk/shmobile/clk-rcar-gen2.c +63 -0

81 lines not on this page · raw message

Signature · 1 line
1.9.1
#2 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Quoting Geert Uytterhoeven (2015-03-18 12:46:53)

Quoted 10 lines

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>

Looks good to me. Which tree do you want this patch to go through?

Regards,
Mike

Quoted 160 lines
---
 .../clock/renesas,rcar-gen2-cpg-clocks.txt         | 26 ++++++++-
 arch/arm/mach-shmobile/Kconfig                     |  1 +
 drivers/clk/shmobile/clk-rcar-gen2.c               | 63 ++++++++++++++++++++++
 3 files changed, 88 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +24 -2
index b02944fba9de4f86..fc013f225a348929 100644
@@ -2,6 +2,8 @@
 
 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
 and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 

@@ -20,10 +22,18 @@ Required Properties:
   - clock-output-names: The names of the clocks. Supported clocks are "main",
     "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
     "adsp"
+  - #power-domain-cells: Must be 0
 
+SoC devices that are part of the CPG Clock Domain and can be power-managed
+through their primary clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
 
-Example
--------
+
+Examples
+--------
+
+  - CPG device node:
 
        cpg_clocks: cpg_clocks at e6150000 {
                compatible = "renesas,r8a7790-cpg-clocks",

@@ -34,4 +44,16 @@ Example
                clock-output-names = "main", "pll0, "pll1", "pll3",
                                     "lb", "qspi", "sdh", "sd0", "sd1", "z",
                                     "rcan", "adsp";
+               #power-domain-cells = <0>;
+       };
+
+
+  - CPG Clock Domain member node:
+
+       thermal at e61f0000 {
+               compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+               reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+               interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+               power-domains = <&cpg_clocks>;
        };
arch/arm/mach-shmobile/Kconfig +1 -0
index 0fb484221c90e0eb..048101a3253c52de 100644
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
 
 config PM_RCAR
        bool
+       select PM_GENERIC_DOMAINS
 
 config PM_RMOBILE
        bool
drivers/clk/shmobile/clk-rcar-gen2.c +63 -0
index acfb6d7dbd6bc049..b54439d3722a13ad 100644
@@ -18,6 +18,8 @@
 #include <linux/math64.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
 #include <linux/spinlock.h>
 
 struct rcar_gen2_cpg {

@@ -364,6 +366,65 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
                                                 4, 0, table, &cpg->lock);
 }
 
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+static int cpg_pd_attach_dev(struct generic_pm_domain *domain,
+                            struct device *dev)
+{
+       int error;
+
+       error = pm_clk_create(dev);
+       if (error) {
+               dev_err(dev, "pm_clk_create failed %d\n", error);
+               return error;
+       }
+
+       error = pm_clk_add(dev, NULL);
+       if (error) {
+               dev_err(dev, "pm_clk_add failed %d\n", error);
+               goto fail;
+       }
+
+       return 0;
+
+fail:
+       pm_clk_destroy(dev);
+       return error;
+}
+
+static void cpg_pd_detach_dev(struct generic_pm_domain *domain,
+                             struct device *dev)
+{
+       pm_clk_destroy(dev);
+}
+
+static void __init rcar_gen2_cpg_add_pm_domain(struct device_node *np)
+{
+       struct generic_pm_domain *pd;
+       u32 ncells;
+
+       if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+               pr_warn("%s lacks #power-domain-cells. Clocks may fail.\n",
+                       np->full_name);
+               return;
+       }
+
+       pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+       if (!pd)
+               return;
+
+       pd->name = np->name;
+
+       pd->flags = GENPD_FLAG_PM_CLK;
+       pm_genpd_init(pd, &simple_qos_governor, false);
+       pd->attach_dev = cpg_pd_attach_dev;
+       pd->detach_dev = cpg_pd_detach_dev;
+
+       of_genpd_add_provider_simple(np, pd);
+}
+#else /* !CONFIG_PM_GENERIC_DOMAINS_OF */
+static inline void rcar_gen2_cpg_add_pm_domain(struct device_node *np) {}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
+
 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
 {
        const struct cpg_pll_config *config;

@@ -415,6 +476,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
        }
 
        of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+       rcar_gen2_cpg_add_pm_domain(np);
 }
 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
               rcar_gen2_cpg_clocks_init);
Signature · 1 line
1.9.1
#3 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Hi Mike,

Quoted 6 lines · Michael Turquette

Quoting Geert Uytterhoeven (2015-03-18 12:46:53)

Quoted 5 lines

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

Quoted 7 lines
Quoted 5 lines

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>

Looks good to me. Which tree do you want this patch to go through?

My tree seems reasonable from my point of view. Though at this point it would be targeted at v4.2.

#4 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Quoted 11 lines · Simon Horman
Quoted 10 lines · Michael Turquette

Quoting Geert Uytterhoeven (2015-03-18 12:46:53)

Quoted 9 lines

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Geert Uytterhoeven <[email protected]>

Looks good to me. Which tree do you want this patch to go through?

My tree seems reasonable from my point of view. Though at this point it would be targeted at v4.2.

Definitely. Please give Laurent some time to comment.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#5 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Quoted 12 lines · Geert Uytterhoeven
Quoted 11 lines · Simon Horman
Quoted 10 lines · Michael Turquette

Quoting Geert Uytterhoeven (2015-03-18 12:46:53)

Quoted 9 lines

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Geert Uytterhoeven <[email protected]>

Looks good to me. Which tree do you want this patch to go through?

My tree seems reasonable from my point of view. Though at this point it would be targeted at v4.2.

Definitely. Please give Laurent some time to comment.

Sure, please post as a non-RFC once you think it is ready.

#6 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

In reply to Geert Uytterhoeven

Hi Geert,

Thank you for the patch.

Quoted 10 lines · On Wednesday 18 March 2015 20:46:53 Geert Uytterhoeven wrote:

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>

There's one thing that bothers me: the implementation is tied to the CPG driver, but the code is quite generic. That feels a bit wrong, it would be nice to come up with a generic implementation. On the other hand, the platform-dependent part is the list of clocks to manage, specified implicitly through the "pm_clk_add(dev, NULL)" call. That list needs to be specified somewhere, and adding it to the CPG driver is likely the best solution we can have at the moment.

I'm slightly worried that adding the power-domains property to the DT node will introduce backward compatibility issues if we later switch to a different way to specify the clocks to manage automatically. I have no specific example though.

For those reasons,

Acked-by Laurent Pinchart <[email protected]>
Quoted 162 lines
---
 .../clock/renesas,rcar-gen2-cpg-clocks.txt         | 26 ++++++++-
 arch/arm/mach-shmobile/Kconfig                     |  1 +
 drivers/clk/shmobile/clk-rcar-gen2.c               | 63 +++++++++++++++++++
 3 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index b02944fba9de4f86..fc013f225a348929 100644
---
a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++
b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

(quoted diff) +0 -0
@@ -2,6 +2,8 @@
 
 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three

PLLs and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the +CPG Module Stop (MSTP) Clocks.

Required Properties:

(quoted diff) +0 -0
@@ -20,10 +22,18 @@ Required Properties:
   - clock-output-names: The names of the clocks. Supported clocks are
 "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z",

"rcan", and "adsp"

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +4 -0
+  - #power-domain-cells: Must be 0
 
+SoC devices that are part of the CPG Clock Domain and can be power-managed
+through their primary clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings

in +Documentation/devicetree/bindings/power/power_domain.txt.

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +17 -2
-Example
--------
+
+Examples
+--------
+
+  - CPG device node:
 
 	cpg_clocks: cpg_clocks at e6150000 {
 		compatible = "renesas,r8a7790-cpg-clocks",

@@ -34,4 +44,16 @@ Example
 		clock-output-names = "main", "pll0, "pll1", "pll3",
 				     "lb", "qspi", "sdh", "sd0", "sd1", "z",
 				     "rcan", "adsp";
+		#power-domain-cells = <0>;
+	};
+
+
+  - CPG Clock Domain member node:
+
+	thermal at e61f0000 {
+		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+		power-domains = <&cpg_clocks>;
 	};
arch/arm/mach-shmobile/Kconfig +1 -0
index 0fb484221c90e0eb..048101a3253c52de 100644
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
 
 config PM_RCAR
 	bool
+	select PM_GENERIC_DOMAINS
 
 config PM_RMOBILE
 	bool
(quoted diff) +0 -0

b/drivers/clk/shmobile/clk-rcar-gen2.c index
acfb6d7dbd6bc049..b54439d3722a13ad 100644

drivers/clk/shmobile/clk-rcar-gen2.c +63 -0
@@ -18,6 +18,8 @@
 #include <linux/math64.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
 #include <linux/spinlock.h>
 
 struct rcar_gen2_cpg {

@@ -364,6 +366,65 @@ rcar_gen2_cpg_register_clock(struct device_node *np,
 struct rcar_gen2_cpg *cpg, 4, 0, table, &cpg->lock);
 }
 
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+static int cpg_pd_attach_dev(struct generic_pm_domain *domain,
+			     struct device *dev)
+{
+	int error;
+
+	error = pm_clk_create(dev);
+	if (error) {
+		dev_err(dev, "pm_clk_create failed %d\n", error);
+		return error;
+	}
+
+	error = pm_clk_add(dev, NULL);
+	if (error) {
+		dev_err(dev, "pm_clk_add failed %d\n", error);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	pm_clk_destroy(dev);
+	return error;
+}
+
+static void cpg_pd_detach_dev(struct generic_pm_domain *domain,
+			      struct device *dev)
+{
+	pm_clk_destroy(dev);
+}
+
+static void __init rcar_gen2_cpg_add_pm_domain(struct device_node *np)
+{
+	struct generic_pm_domain *pd;
+	u32 ncells;
+
+	if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+		pr_warn("%s lacks #power-domain-cells. Clocks may fail.\n",
+			np->full_name);
+		return;
+	}
+
+	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return;
+
+	pd->name = np->name;
+
+	pd->flags = GENPD_FLAG_PM_CLK;
+	pm_genpd_init(pd, &simple_qos_governor, false);
+	pd->attach_dev = cpg_pd_attach_dev;
+	pd->detach_dev = cpg_pd_detach_dev;
+
+	of_genpd_add_provider_simple(np, pd);
+}
+#else /* !CONFIG_PM_GENERIC_DOMAINS_OF */
+static inline void rcar_gen2_cpg_add_pm_domain(struct device_node *np) {}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
+
 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
 {
 	const struct cpg_pll_config *config;

@@ -415,6 +476,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct
 device_node *np) }
 
 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+	rcar_gen2_cpg_add_pm_domain(np);
 }
 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
 	       rcar_gen2_cpg_clocks_init);
Signature · 3 lines
Regards,

Laurent Pinchart
#7 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Hi Laurent,

Quoted 12 lines · Laurent Pinchart
Quoted 10 lines · On Wednesday 18 March 2015 20:46:53 Geert Uytterhoeven wrote:

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>
Quoted 7 lines

There's one thing that bothers me: the implementation is tied to the CPG driver, but the code is quite generic. That feels a bit wrong, it would be nice to come up with a generic implementation. On the other hand, the platform-dependent part is the list of clocks to manage, specified implicitly through the "pm_clk_add(dev, NULL)" call. That list needs to be specified somewhere, and adding it to the CPG driver is likely the best solution we can have at the moment.

This clock management code is identical to the one in pm-rmobile.c. We may consolidate in the future, if we have more PM Domain support (e.g. for R-Car Gen2 SYSC). Let's see...

Quoted 4 lines

I'm slightly worried that adding the power-domains property to the DT node will introduce backward compatibility issues if we later switch to a different way to specify the clocks to manage automatically. I have no specific example though.

Specifying the clocks is indeed the hard part. I use the primary clocks, as that is compatible with what we did in the past in drivers/sh/pm_runtime.c. I thought about using a special clock name instead, but that may conflict with an existing driver-specific DT binding for clk-names, and may cause problems if you have to specify the same clock twice with different clk-names.

Quoted 3 lines

For those reasons,

Acked-by Laurent Pinchart <[email protected]>

Thanks!

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#8 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

Hi Geert,

Quoted 30 lines · On Wednesday 01 April 2015 14:13:12 Geert Uytterhoeven wrote:
Quoted 12 lines · Laurent Pinchart
Quoted 10 lines · On Wednesday 18 March 2015 20:46:53 Geert Uytterhoeven wrote:

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>
Quoted 7 lines

There's one thing that bothers me: the implementation is tied to the CPG driver, but the code is quite generic. That feels a bit wrong, it would be nice to come up with a generic implementation. On the other hand, the platform-dependent part is the list of clocks to manage, specified implicitly through the "pm_clk_add(dev, NULL)" call. That list needs to be specified somewhere, and adding it to the CPG driver is likely the best solution we can have at the moment.

This clock management code is identical to the one in pm-rmobile.c. We may consolidate in the future, if we have more PM Domain support (e.g. for R-Car Gen2 SYSC). Let's see...

Quoted 4 lines

I'm slightly worried that adding the power-domains property to the DT node will introduce backward compatibility issues if we later switch to a different way to specify the clocks to manage automatically. I have no specific example though.

Quoted 6 lines

Specifying the clocks is indeed the hard part. I use the primary clocks, as that is compatible with what we did in the past in drivers/sh/pm_runtime.c. I thought about using a special clock name instead, but that may conflict with an existing driver-specific DT binding for clk-names, and may cause problems if you have to specify the same clock twice with different clk-names.

But we're free to set the rules here, as we're dealing with new code. We could for instance mandate that all Renesas IP cores specify their functional clock as "fck" in DT, and enforce that rule in new drivers. As we're not dealing with external platform devices we should be in full control.

If future IP cores require more than one clock to be automatically managed we'll need to come up with a naming scheme anyway, and backward compatibility will need to be taken into account, regardless of whether we use the NULL clock or a named clock today.

Quoted 5 lines
Quoted 3 lines

For those reasons,

Acked-by Laurent Pinchart <[email protected]>

Thanks!

Signature · 3 lines
Regards,

Laurent Pinchart
#9 lore raw

PATCH 1/5 clk: shmobile: rcar-gen2: Add CPG Clock Domain support

In reply to Geert Uytterhoeven
Quoted 10 lines · Geert Uytterhoeven

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock should be tagged in DT with a proper "power-domains" property.

Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Kevin Hilman <[email protected]>
author maintainer
#10 lore raw

PATCH 2/5 ARM: shmobile: r8a7790 dtsi: Add CPG Clock Domain

In reply to Geert Uytterhoeven

Add an appropriate "#power-domain-cells" property to the cpg_clocks device node, to create the CPG Clock Domain.

Add "power-domains" properties to all device nodes for devices that are part of the CPG Clock Domain and can be power-managed through their primary clock. This includes most on-SoC devices. Notable exceptions are:
- du, which references 3 or 5 clocks; I assume the driver manages all of them itself?
- rcar_sound, which references lots of clock; idem?

Signed-off-by Geert Uytterhoeven <[email protected]>
---
 arch/arm/boot/dts/r8a7790.dtsi | 77 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 71 insertions(+), 6 deletions(-)
arch/arm/boot/dts/r8a7790.dtsi +71 -6
index d4210f5b692a42b5..3c1f3b27dfdf506f 100644
@@ -123,6 +123,7 @@
 			<0 0xf1006000 0 0x2000>;
 		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio0: gpio at e6050000 {

@@ -135,6 +136,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio1: gpio at e6051000 {

@@ -147,6 +149,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio2: gpio at e6052000 {

@@ -159,6 +162,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio3: gpio at e6053000 {

@@ -171,6 +175,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio4: gpio at e6054000 {

@@ -183,6 +188,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio5: gpio at e6055000 {

@@ -195,6 +201,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	thermal at e61f0000 {

@@ -202,6 +209,7 @@
 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	timer {

@@ -219,6 +227,7 @@
 			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0x60>;
 

@@ -238,6 +247,7 @@
 			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0xff>;
 

@@ -254,6 +264,7 @@
 			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
 			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	dmac0: dma-controller at e6700000 {

@@ -282,6 +293,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};

@@ -312,6 +324,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};

@@ -340,6 +353,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};

@@ -368,6 +382,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};

@@ -379,6 +394,7 @@
 		reg = <0 0xe6508000 0 0x40>;
 		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -389,6 +405,7 @@
 		reg = <0 0xe6518000 0 0x40>;
 		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -399,6 +416,7 @@
 		reg = <0 0xe6530000 0 0x40>;
 		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -409,6 +427,7 @@
 		reg = <0 0xe6540000 0 0x40>;
 		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -419,6 +438,7 @@
 		reg = <0 0xe6500000 0 0x425>;
 		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -431,6 +451,7 @@
 		reg = <0 0xe6510000 0 0x425>;
 		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -443,6 +464,7 @@
 		reg = <0 0xe6520000 0 0x425>;
 		interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -455,6 +477,7 @@
 		reg = <0 0xe60b0000 0 0x425>;
 		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -465,6 +488,7 @@
 		reg = <0 0xee200000 0 0x80>;
 		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 		dma-names = "tx", "rx";
 		reg-io-width = <4>;

@@ -476,6 +500,7 @@
 		reg = <0 0xee220000 0 0x80>;
 		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
 		dma-names = "tx", "rx";
 		reg-io-width = <4>;

@@ -492,6 +517,7 @@
 		reg = <0 0xee100000 0 0x328>;
 		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -502,6 +528,7 @@
 		reg = <0 0xee120000 0 0x328>;
 		interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -512,6 +539,7 @@
 		reg = <0 0xee140000 0 0x100>;
 		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -522,6 +550,7 @@
 		reg = <0 0xee160000 0 0x100>;
 		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
+		power-domains = <&cpg_clocks>;
 		dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 		dma-names = "tx", "rx";
 		status = "disabled";

@@ -533,6 +562,7 @@
 		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -542,6 +572,7 @@
 		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -551,6 +582,7 @@
 		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -560,6 +592,7 @@
 		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -569,6 +602,7 @@
 		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -578,6 +612,7 @@
 		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -587,6 +622,7 @@
 		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -596,6 +632,7 @@
 		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -605,6 +642,7 @@
 		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -614,6 +652,7 @@
 		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -622,6 +661,7 @@
 		reg = <0 0xee700000 0 0x400>;
 		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -633,6 +673,7 @@
 		reg = <0 0xee300000 0 0x2000>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -641,6 +682,7 @@
 		reg = <0 0xee500000 0 0x2000>;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -649,6 +691,7 @@
 		reg = <0 0xe6590000 0 0x100>;
 		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+		power-domains = <&cpg_clocks>;
 		renesas,buswait = <4>;
 		phys = <&usb0 1>;
 		phy-names = "usb";

@@ -662,6 +705,7 @@
 		#size-cells = <0>;
 		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 		clock-names = "usbhs";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 
 		usb0: usb-channel at 0 {

@@ -676,33 +720,37 @@
 
 	vin0: video at e6ef0000 {
 		compatible = "renesas,vin-r8a7790";
-		clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 		reg = <0 0xe6ef0000 0 0x1000>;
 		interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	vin1: video at e6ef1000 {
 		compatible = "renesas,vin-r8a7790";
-		clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 		reg = <0 0xe6ef1000 0 0x1000>;
 		interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	vin2: video at e6ef2000 {
 		compatible = "renesas,vin-r8a7790";
-		clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 		reg = <0 0xe6ef2000 0 0x1000>;
 		interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	vin3: video at e6ef3000 {
 		compatible = "renesas,vin-r8a7790";
-		clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 		reg = <0 0xe6ef3000 0 0x1000>;
 		interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -711,6 +759,7 @@
 		reg = <0 0xfe920000 0 0x8000>;
 		interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-sru;
 		renesas,#rpf = <5>;

@@ -723,6 +772,7 @@
 		reg = <0 0xfe928000 0 0x8000>;
 		interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-lut;
 		renesas,has-sru;

@@ -736,6 +786,7 @@
 		reg = <0 0xfe930000 0 0x8000>;
 		interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-lif;
 		renesas,has-lut;

@@ -749,6 +800,7 @@
 		reg = <0 0xfe938000 0 0x8000>;
 		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-lif;
 		renesas,has-lut;

@@ -803,6 +855,7 @@
 		clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
 			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -813,6 +866,7 @@
 		clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
 			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -890,6 +944,7 @@
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "sd1",
 					     "z", "rcan", "adsp";
+			#power-domain-cells = <0>;
 		};
 
 		/* Variable factor clocks */

@@ -1275,6 +1330,7 @@
 		clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -1288,6 +1344,7 @@
 		clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 		dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1300,6 +1357,7 @@
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
 		dmas = <&dmac0 0x55>, <&dmac0 0x56>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1312,6 +1370,7 @@
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
 		dmas = <&dmac0 0x41>, <&dmac0 0x42>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1324,6 +1383,7 @@
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
 		dmas = <&dmac0 0x45>, <&dmac0 0x46>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1334,6 +1394,7 @@
 		reg = <0 0xee000000 0 0xc00>;
 		interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+		power-domains = <&cpg_clocks>;
 		phys = <&usb2 1>;
 		phy-names = "usb";
 		status = "disabled";

@@ -1342,10 +1403,11 @@
 	pci0: pci at ee090000 {
 		compatible = "renesas,pci-r8a7790";
 		device_type = "pci";
-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
 		reg = <0 0xee090000 0 0xc00>,
 		      <0 0xee080000 0 0x1100>;
 		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 
 		bus-range = <0 0>;

@@ -1376,10 +1438,11 @@
 	pci1: pci at ee0b0000 {
 		compatible = "renesas,pci-r8a7790";
 		device_type = "pci";
-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
 		reg = <0 0xee0b0000 0 0xc00>,
 		      <0 0xee0a0000 0 0x1100>;
 		interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 
 		bus-range = <1 1>;

@@ -1397,6 +1460,7 @@
 		compatible = "renesas,pci-r8a7790";
 		device_type = "pci";
 		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+		power-domains = <&cpg_clocks>;
 		reg = <0 0xee0d0000 0 0xc00>,
 		      <0 0xee0c0000 0 0x1100>;
 		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;

@@ -1449,6 +1513,7 @@
 		interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
 		clock-names = "pcie", "pcie_bus";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
Signature · 1 line
1.9.1
author maintainer
#11 lore raw

PATCH 3/5 ARM: shmobile: r8a7791 dtsi: Add CPG Clock Domain

In reply to Geert Uytterhoeven

Add an appropriate "#power-domain-cells" property to the cpg_clocks device node, to create the CPG Clock Domain.

Add "power-domains" properties to all device nodes for devices that are part of the CPG Clock Domain and can be power-managed through their primary clock. This includes most on-SoC devices. Notable exceptions are:
- du, which references 3 or 5 clocks; I assume the driver manages all of them itself?
- rcar_sound, which references lots of clock; idem?

Signed-off-by Geert Uytterhoeven <[email protected]>
---
 arch/arm/boot/dts/r8a7791.dtsi | 80 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 75 insertions(+), 5 deletions(-)
arch/arm/boot/dts/r8a7791.dtsi +75 -5
index 9191acce98a6eeb2..cd11c6dd75021edb 100644
@@ -80,6 +80,7 @@
 			<0 0xf1006000 0 0x2000>;
 		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio0: gpio at e6050000 {

@@ -92,6 +93,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio1: gpio at e6051000 {

@@ -104,6 +106,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio2: gpio at e6052000 {

@@ -116,6 +119,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio3: gpio at e6053000 {

@@ -128,6 +132,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio4: gpio at e6054000 {

@@ -140,6 +145,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio5: gpio at e6055000 {

@@ -152,6 +158,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio6: gpio at e6055400 {

@@ -164,6 +171,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	gpio7: gpio at e6055800 {

@@ -176,6 +184,7 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	thermal at e61f0000 {

@@ -183,6 +192,7 @@
 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	timer {

@@ -200,6 +210,7 @@
 			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0x60>;
 

@@ -219,6 +230,7 @@
 			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0xff>;
 

@@ -241,6 +253,7 @@
 			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
 			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	dmac0: dma-controller at e6700000 {

@@ -269,6 +282,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};

@@ -299,6 +313,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};

@@ -327,6 +342,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};

@@ -355,6 +371,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};

@@ -367,6 +384,7 @@
 		reg = <0 0xe6508000 0 0x40>;
 		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -377,6 +395,7 @@
 		reg = <0 0xe6518000 0 0x40>;
 		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -387,6 +406,7 @@
 		reg = <0 0xe6530000 0 0x40>;
 		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -397,6 +417,7 @@
 		reg = <0 0xe6540000 0 0x40>;
 		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -407,6 +428,7 @@
 		reg = <0 0xe6520000 0 0x40>;
 		interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -418,6 +440,7 @@
 		reg = <0 0xe6528000 0 0x40>;
 		interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -431,6 +454,7 @@
 		clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 		dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -443,6 +467,7 @@
 		clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -455,6 +480,7 @@
 		clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -471,6 +497,7 @@
 		clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		reg-io-width = <4>;
 		status = "disabled";
 	};

@@ -482,6 +509,7 @@
 		clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 		dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -492,6 +520,7 @@
 		clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 		dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -502,6 +531,7 @@
 		clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 		dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -511,6 +541,7 @@
 		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -520,6 +551,7 @@
 		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -529,6 +561,7 @@
 		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -538,6 +571,7 @@
 		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -547,6 +581,7 @@
 		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -556,6 +591,7 @@
 		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -565,6 +601,7 @@
 		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -574,6 +611,7 @@
 		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -583,6 +621,7 @@
 		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -592,6 +631,7 @@
 		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -601,6 +641,7 @@
 		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -610,6 +651,7 @@
 		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -619,6 +661,7 @@
 		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -628,6 +671,7 @@
 		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -637,6 +681,7 @@
 		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -646,6 +691,7 @@
 		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -655,6 +701,7 @@
 		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -664,6 +711,7 @@
 		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -672,6 +720,7 @@
 		reg = <0 0xee700000 0 0x400>;
 		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -683,6 +732,7 @@
 		reg = <0 0xee300000 0 0x2000>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -691,6 +741,7 @@
 		reg = <0 0xee500000 0 0x2000>;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -699,6 +750,7 @@
 		reg = <0 0xe6590000 0 0x100>;
 		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
+		power-domains = <&cpg_clocks>;
 		renesas,buswait = <4>;
 		phys = <&usb0 1>;
 		phy-names = "usb";

@@ -712,6 +764,7 @@
 		#size-cells = <0>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 		clock-names = "usbhs";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 
 		usb0: usb-channel at 0 {

@@ -726,25 +779,28 @@
 
 	vin0: video at e6ef0000 {
 		compatible = "renesas,vin-r8a7791";
-		clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 		reg = <0 0xe6ef0000 0 0x1000>;
 		interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	vin1: video at e6ef1000 {
 		compatible = "renesas,vin-r8a7791";
-		clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 		reg = <0 0xe6ef1000 0 0x1000>;
 		interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	vin2: video at e6ef2000 {
 		compatible = "renesas,vin-r8a7791";
-		clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 		reg = <0 0xe6ef2000 0 0x1000>;
 		interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -753,6 +809,7 @@
 		reg = <0 0xfe928000 0 0x8000>;
 		interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-lut;
 		renesas,has-sru;

@@ -766,6 +823,7 @@
 		reg = <0 0xfe930000 0 0x8000>;
 		interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-lif;
 		renesas,has-lut;

@@ -779,6 +837,7 @@
 		reg = <0 0xfe938000 0 0x8000>;
 		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
+		power-domains = <&cpg_clocks>;
 
 		renesas,has-lif;
 		renesas,has-lut;

@@ -824,6 +883,7 @@
 		clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
 			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -834,6 +894,7 @@
 		clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
 			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -911,6 +972,7 @@
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z",
 					     "rcan", "adsp";
+			#power-domain-cells = <0>;
 		};
 
 		/* Variable factor clocks */

@@ -1290,6 +1352,7 @@
 		clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -1303,6 +1366,7 @@
 		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 		dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1315,6 +1379,7 @@
 		clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 		dmas = <&dmac0 0x55>, <&dmac0 0x56>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1327,6 +1392,7 @@
 		clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 		dmas = <&dmac0 0x41>, <&dmac0 0x42>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";

@@ -1337,6 +1403,7 @@
 		reg = <0 0xee000000 0 0xc00>;
 		interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+		power-domains = <&cpg_clocks>;
 		phys = <&usb2 1>;
 		phy-names = "usb";
 		status = "disabled";

@@ -1345,10 +1412,11 @@
 	pci0: pci at ee090000 {
 		compatible = "renesas,pci-r8a7791";
 		device_type = "pci";
-		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
 		reg = <0 0xee090000 0 0xc00>,
 		      <0 0xee080000 0 0x1100>;
 		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 
 		bus-range = <0 0>;

@@ -1379,10 +1447,11 @@
 	pci1: pci at ee0d0000 {
 		compatible = "renesas,pci-r8a7791";
 		device_type = "pci";
-		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
 		reg = <0 0xee0d0000 0 0xc00>,
 		      <0 0xee0c0000 0 0x1100>;
 		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 
 		bus-range = <1 1>;

@@ -1432,6 +1501,7 @@
 		interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
 		clock-names = "pcie", "pcie_bus";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
Signature · 1 line
1.9.1
author maintainer
#12 lore raw

PATCH 4/5 ARM: shmobile: r8a7794 dtsi: Add CPG Clock Domain

In reply to Geert Uytterhoeven

Add an appropriate "#power-domain-cells" property to the cpg_clocks device node, to create the CPG Clock Domain.

Add "power-domains" properties to all device nodes for devices that are part of the CPG Clock Domain and can be power-managed through their primary clock. This includes most present on-SoC devices.

Signed-off-by Geert Uytterhoeven <[email protected]>
---
 arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/arm/boot/dts/r8a7794.dtsi +29 -0
index 5667d284a3f0af92..2d0d5b20f98c16fa 100644
@@ -49,6 +49,7 @@
 			<0 0xf1006000 0 0x2000>;
 		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	cmt0: timer at ffca0000 {

@@ -58,6 +59,7 @@
 			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0x60>;
 

@@ -77,6 +79,7 @@
 			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0xff>;
 

@@ -107,6 +110,7 @@
 			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
 			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	dmac0: dma-controller at e6700000 {

@@ -135,6 +139,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};

@@ -165,6 +170,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};

@@ -175,6 +181,7 @@
 		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -184,6 +191,7 @@
 		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -193,6 +201,7 @@
 		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -202,6 +211,7 @@
 		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -211,6 +221,7 @@
 		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -220,6 +231,7 @@
 		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -229,6 +241,7 @@
 		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -238,6 +251,7 @@
 		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -247,6 +261,7 @@
 		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -256,6 +271,7 @@
 		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -265,6 +281,7 @@
 		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -274,6 +291,7 @@
 		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -283,6 +301,7 @@
 		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -292,6 +311,7 @@
 		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -301,6 +321,7 @@
 		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -310,6 +331,7 @@
 		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -319,6 +341,7 @@
 		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -328,6 +351,7 @@
 		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -336,6 +360,7 @@
 		reg = <0 0xee700000 0 0x400>;
 		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -347,6 +372,7 @@
 		reg = <0 0xee100000 0 0x200>;
 		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -355,6 +381,7 @@
 		reg = <0 0xee140000 0 0x100>;
 		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -363,6 +390,7 @@
 		reg = <0 0xee160000 0 0x100>;
 		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 

@@ -389,6 +417,7 @@
 			#clock-cells = <1>;
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z";
+			#power-domain-cells = <0>;
 		};
 		/* Variable factor clocks */
 		sd2_clk: sd2_clk at e6150078 {
Signature · 1 line
1.9.1
author maintainer
#13 lore raw

PATCH 5/5 drivers: sh: Disable PM runtime for multi-platform R-Car Gen2 with genpd

In reply to Geert Uytterhoeven

Now we have an R-Car Gen2 CPG Clock Domain driver using the generic PM domain to take care of PM runtime management of the module clocks, we no longer need the legacy default PM domain hack, which also prevents registering the real PM domain.

Hence do not enable it when running a multi-platform kernel with genpd support on an R-Car Gen2 SoC.

The default PM domain is still needed:
- for platforms without genpd support,
- for the legacy (non-DT) case, where genpd may take over later,
- if genpd is not enabled.

Signed-off-by Geert Uytterhoeven <[email protected]>
---
 drivers/sh/pm_runtime.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
drivers/sh/pm_runtime.c +5 -5
index fe8875f0d7be1155..97d5738f21ae8f04 100644
@@ -83,15 +83,15 @@ static int __init sh_pm_runtime_init(void)
 #ifndef CONFIG_PM_GENERIC_DOMAINS_OF
 		    !of_machine_is_compatible("renesas,r8a73a4") &&
 		    !of_machine_is_compatible("renesas,r8a7740") &&
-		    !of_machine_is_compatible("renesas,sh73a0") &&
-#endif
-		    !of_machine_is_compatible("renesas,r8a7778") &&
-		    !of_machine_is_compatible("renesas,r8a7779") &&
 		    !of_machine_is_compatible("renesas,r8a7790") &&
 		    !of_machine_is_compatible("renesas,r8a7791") &&
 		    !of_machine_is_compatible("renesas,r8a7792") &&
 		    !of_machine_is_compatible("renesas,r8a7793") &&
-		    !of_machine_is_compatible("renesas,r8a7794"))
+		    !of_machine_is_compatible("renesas,r8a7794") &&
+		    !of_machine_is_compatible("renesas,sh73a0") &&
+#endif
+		    !of_machine_is_compatible("renesas,r8a7778") &&
+		    !of_machine_is_compatible("renesas,r8a7779"))
 			return 0;
 	}
Signature · 1 line
1.9.1
#14 lore raw

cover ARM: shmobile: rcar-gen2: Add CPG Clock Domain

In reply to Geert Uytterhoeven
Quoted 90 lines · Geert Uytterhoeven
        Hi,

This RFC patch series adds Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG Clock Domain and can be power-managed through their primary clock are tagged in DT with a proper "power-domains" property. Drivers for devices with multiple clocks (notably du and rcar-sound) still have to manage their (multiple module) clocks themselves.

Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c is disabled when running on an R-Car Gen2 SoC with genpd support.

Compared to the legacy default PM domain hack, the CPG Clock Domain has several advantages:
- It only affects on-SoC devices, not all platform devices,
- It only affects the on-SoC devices we want, as specified in DT,
- Allmost all module clocks of all on-SoC devices (barring devices needed for wake-up[*]) are now gated during s2ram, saving more power.

Here's a list of all devices in the CPG Clock Domain on r8a7791:

root at koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
cpg_clocks on

    /devices/platform/e61c0000.interrupt-controller     active
    /devices/platform/e60b0000.i2c                      suspended
    /devices/platform/ffca0000.timer                    suspended
    /devices/platform/e6050000.gpio                     active
    /devices/platform/e6051000.gpio                     active
    /devices/platform/e6052000.gpio                     active
    /devices/platform/e6053000.gpio                     active
    /devices/platform/e6054000.gpio                     active
    /devices/platform/e6055000.gpio                     active
    /devices/platform/e6055400.gpio                     active
    /devices/platform/e6055800.gpio                     active
    /devices/platform/ee090000.pci                      active
    /devices/platform/ee0d0000.pci                      active
    /devices/platform/fe000000.pcie                     unsupported
    /devices/platform/e6700000.dma-controller           active
    /devices/platform/e6720000.dma-controller           active
    /devices/platform/ec700000.dma-controller           active
    /devices/platform/ec720000.dma-controller           suspended
    /devices/platform/e6e60000.serial                   active
    /devices/platform/e6e68000.serial                   active
    /devices/platform/ee300000.sata                     unsupported
    /devices/platform/e6b10000.spi                      suspended
    /devices/platform/e6e20000.spi                      suspended
    /devices/platform/ee700000.ethernet                 active
    /devices/platform/e6530000.i2c                      suspended
    /devices/platform/e6ef1000.video                    suspended
    /devices/platform/e61f0000.thermal                  active
    /devices/platform/ee100000.sd                       active
    /devices/platform/ee140000.sd                       active
    /devices/platform/ee160000.sd                       active

root at koelsch:~#

Logically, the CPG Clock Domain operates on the SoC CPG/MSTP block. As there's no single device node in DT representing this block (there are separate device nodes for the CPG and for the individual MSTP clocks), I bound the logic to the CPG device node.
Perhaps this is something we should change for future SoCs?

As usual when involving clocks and/or PM Domains, the DTS changes depend stricly on the driver change. The final patch must be applied last.

The DTS changes also depend on the series "[PATCH 0/5] ARM: shmobile:
Add INTC-SYS clock to device tree" I've just sent.

This was tested on r8a7791/koelsch.

Thanks for your comments!

[*] GPIO wake-up requires "[PATCH 0/3] gpio: rcar: Fix wake up using gpio-keys with PM domain").

Geert Uytterhoeven (5):
[RFC] clk: shmobile: rcar-gen2: Add CPG Clock Domain support [RFC] ARM: shmobile: r8a7790 dtsi: Add CPG Clock Domain [RFC] ARM: shmobile: r8a7791 dtsi: Add CPG Clock Domain [RFC] ARM: shmobile: r8a7794 dtsi: Add CPG Clock Domain
drivers: sh: Disable PM runtime for multi-platform R-Car Gen2 with
genpd

Quoted 8 lines
 .../clock/renesas,rcar-gen2-cpg-clocks.txt         | 26 ++++++-
 arch/arm/boot/dts/r8a7790.dtsi                     | 77 +++++++++++++++++++--
 arch/arm/boot/dts/r8a7791.dtsi                     | 80 ++++++++++++++++++++--
 arch/arm/boot/dts/r8a7794.dtsi                     | 29 ++++++++
 arch/arm/mach-shmobile/Kconfig                     |  1 +
 drivers/clk/shmobile/clk-rcar-gen2.c               | 63 +++++++++++++++++
 drivers/sh/pm_runtime.c                            | 10 +--
 7 files changed, 268 insertions(+), 18 deletions(-)

For the complete patchset.

Reviewed-by Ulf Hansson <[email protected]>

Kind regards
Uffe

Quoted 14 lines

--
1.9.1

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds