add the reset controller to the Meson8b clkc

PATCH Superseded Martin Blumenstingl 5 participants 9 messages Jul 28, 2017 – Aug 3, 2017

Subsystems (5)

Device tree bindings Arm/Amlogic Meson SoC support Common clk Reset controller framework +1 more subsystems

lore

Share & tools

lore

Martin Blumenstingl

author reviewer

2017-07-28 21:13 UTC #0 lore raw

v3 cover add the reset controller to the Meson8b clkc

This registers the known (soft) reset lines provided by the clock controller's registers.

This is the first preparation step for SMP and CPU hotplug support on Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs requires asserting and de-asserting a reset line (one for each CPU core). These reset lines are provided by the clock controller.

The reset controller part of the meson8b clock controller has to be registered early (which I did through CLK_OF_DECLARE_DRIVER), because the secondary cores are started *very* early in the boot process (and meson8b_clkc_probe is invoked long after we need the reset controller to be available for booting the secondary CPU cores).

The user of the reset-controller (= the patches which enable SMP and CPU hotplug support) will follow in the next days. I decided to split this because the SMP series will probably consist of 6 patches alone (and may need to go through two separate trees).

Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to CLKC_RESET_ to clearly indicate that these are provided by the clock controller (unlike the preprocessor macros for the reset lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches

Changes since v1 at [0]:
- updated cover letter description as we are now registering more than four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that the reset identifiers are preprocessor macros in dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these macros at all)
- patch #2 (previously part of patch #1) now registers all known reset lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched

[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html

Martin Blumenstingl (3):
dt-bindings: clock: meson8b: describe the embedded reset controller
clk: meson: meson8b: register the built-in reset controller
ARM: dts: meson: mark the clock controller also as reset controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++--
 drivers/clk/meson/meson8b.h                        |   9 +-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
 7 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Signature · 1 line

2.13.3

Martin Blumenstingl

author reviewer

2017-07-28 21:13 UTC #1 lore raw

PATCH v3 1/3 dt-bindings: clock: meson8b: describe the embedded reset controller

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each reset line (to make the .dts files easier to read).

Signed-off-by Martin Blumenstingl <[email protected]>

Reviewed-by Neil Armstrong <[email protected]>

---
 .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +8 -1

index 606da38c0959..c858fd64f680 100644
@@ -16,18 +16,25 @@ Required Properties:
 	   mapped region.
 
 - #clock-cells: should be 1.
+- #reset-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
 used in device tree sources.
 
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
 Example: Clock controller node:
 
 	clkc: clock-controller at c1104000 {
-		#clock-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};

include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h new file +27 -0

new file mode 100644
index 000000000000..1f1b56e57346
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <[email protected]>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+
+#define CLKC_RESET_L2_CACHE_SOFT_RESET				0
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
+#define CLKC_RESET_SCU_SOFT_RESET				2
+#define CLKC_RESET_CPU0_SOFT_RESET				3
+#define CLKC_RESET_CPU1_SOFT_RESET				4
+#define CLKC_RESET_CPU2_SOFT_RESET				5
+#define CLKC_RESET_CPU3_SOFT_RESET				6
+#define CLKC_RESET_A5_GLOBAL_RESET				7
+#define CLKC_RESET_A5_AXI_SOFT_RESET				8
+#define CLKC_RESET_A5_ABP_SOFT_RESET				9
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET		10
+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET			11
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST		12
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE		13
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST		14
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE			15
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */

Signature · 1 line

2.13.3

Rob Herring

maintainer

2017-08-03 23:08 UTC #2 lore raw

PATCH v3 1/3 dt-bindings: clock: meson8b: describe the embedded reset controller

Quoted 8 lines · Martin Blumenstingl

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset lines. These are used for example to boot the secondary CPU cores.
This patch describes the reset controller which is embedded into the clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each reset line (to make the .dts files easier to read).

Quoted 7 lines

Signed-off-by Martin Blumenstingl <[email protected]>

Reviewed-by Neil Armstrong <[email protected]>

---
 .../bindings/clock/amlogic,meson8b-clkc.txt        |  9 +++++++-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h | 27 ++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Acked-by Rob Herring <[email protected]>

Martin Blumenstingl

author reviewer

2017-07-28 21:13 UTC #3 lore raw

PATCH v3 2/3 clk: meson: meson8b: register the built-in reset controller

In reply to Martin Blumenstingl

The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione.

Signed-off-by Martin Blumenstingl <[email protected]>

Reviewed-by Neil Armstrong <[email protected]>

---
 drivers/clk/meson/Kconfig   |   1 +
 drivers/clk/meson/meson8b.c | 159 ++++++++++++++++++++++++++++++++++++++++----
 drivers/clk/meson/meson8b.h |   9 ++-
 3 files changed, 156 insertions(+), 13 deletions(-)

drivers/clk/meson/Kconfig +1 -0

index 5588f75a8414..d2d0174a6eca 100644
@@ -6,6 +6,7 @@ config COMMON_CLK_AMLOGIC
 config COMMON_CLK_MESON8B
 	bool
 	depends on COMMON_CLK_AMLOGIC
+	select RESET_CONTROLLER
 	help
 	  Support for the clock controller on AmLogic S802 (Meson8),
 	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you

drivers/clk/meson/meson8b.c +147 ~~-12~~

204 lines not on this page · raw message

drivers/clk/meson/meson8b.h +8 -1

index a687e02547dc..9e4c597d8a79 100644
@@ -37,6 +37,9 @@
 #define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
 #define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
+#define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
+#define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */

@@ -163,7 +166,11 @@
 
 #define CLK_NR_CLKS		96
 
-/* include the CLKIDs that have been made part of the stable DT binding */
+/*
+ * include the CLKID and RESETID that have
+ * been made part of the stable DT binding
+ */
 #include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 
 #endif /* __MESON8B_H */

Signature · 1 line

2.13.3

Martin Blumenstingl

author reviewer

2017-07-28 21:13 UTC #4 lore raw

PATCH v3 3/3 ARM: dts: meson: mark the clock controller also as reset controller

In reply to Martin Blumenstingl

The clock controller provides a few reset lines as well. Add the corresponding CPU cores.

Signed-off-by Martin Blumenstingl <[email protected]>

Reviewed-by Neil Armstrong <[email protected]>

---
 arch/arm/boot/dts/meson8.dtsi  | 1 +
 arch/arm/boot/dts/meson8b.dtsi | 1 +
 2 files changed, 2 insertions(+)

arch/arm/boot/dts/meson8.dtsi +1 -0

index 6fe6a159e960..b98d44fde6b6 100644
@@ -168,6 +168,7 @@
 &cbus {
 	clkc: clock-controller at 4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};

arch/arm/boot/dts/meson8b.dtsi +1 -0

index 8fce13844b0c..bc278da7df0d 100644
@@ -119,6 +119,7 @@
 &cbus {
 	clkc: clock-controller at 4000 {
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 		compatible = "amlogic,meson8b-clkc";
 		reg = <0x8000 0x4>, <0x4000 0x460>;
 	};

Signature · 1 line

2.13.3

Jerome Brunet

maintainer

2017-07-31 08:27 UTC #5 lore raw

v3 cover add the reset controller to the Meson8b clkc

In reply to Martin Blumenstingl

Quoted 58 lines · Martin Blumenstingl

This registers the known (soft) reset lines provided by the clock controller's registers.
This is the first preparation step for SMP and CPU hotplug support on Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs requires asserting and de-asserting a reset line (one for each CPU core). These reset lines are provided by the clock controller.
The reset controller part of the meson8b clock controller has to be registered early (which I did through CLK_OF_DECLARE_DRIVER), because the secondary cores are started *very* early in the boot process (and meson8b_clkc_probe is invoked long after we need the reset controller to be available for booting the secondary CPU cores).
The user of the reset-controller (= the patches which enable SMP and CPU hotplug support) will follow in the next days. I decided to split this because the SMP series will probably consist of 6 patches alone (and may need to go through two separate trees).
Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file ? (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to ? CLKC_RESET_ to clearly indicate that these are provided by the ? clock controller (unlike the preprocessor macros for the reset ? lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches
Changes since v1 at [0]:
- updated cover letter description as we are now registering more than ? four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that ? the reset identifiers are preprocessor macros in
? dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these ? macros at all)
- patch #2 (previously part of patch #1) now registers all known reset ? lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
Martin Blumenstingl (3):
? dt-bindings: clock: meson8b: describe the embedded reset controller ? clk: meson: meson8b: register the built-in reset controller ? ARM: dts: meson: mark the clock controller also as reset controller
?.../bindings/clock/amlogic,meson8b-clkc.txt????????|???9 +-
?arch/arm/boot/dts/meson8.dtsi??????????????????????|???1 +
?arch/arm/boot/dts/meson8b.dtsi?????????????????????|???1 +
?drivers/clk/meson/Kconfig??????????????????????????|???1 +
?drivers/clk/meson/meson8b.c????????????????????????| 159 +++++++++++++++++++-

Quoted 6 lines

-
?drivers/clk/meson/meson8b.h????????????????????????|???9 +- ?.../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |??27 ++++ ?7 files changed, 193 insertions(+), 14 deletions(-)
?create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Series looks good to me overall.

Acked-by Jerome Brunet <[email protected]>

Just one thing, which is not an issue really, I wonder if the dt-bindings documentation and the bindings them-self should be in separate patches ?

Neil Armstrong

2017-07-31 11:59 UTC #6 lore raw

v3 cover add the reset controller to the Meson8b clkc

Quoted 66 lines · Jerome Brunet

Quoted 53 lines · Martin Blumenstingl
This registers the known (soft) reset lines provided by the clock controller's registers.
This is the first preparation step for SMP and CPU hotplug support on Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs requires asserting and de-asserting a reset line (one for each CPU core). These reset lines are provided by the clock controller.
The reset controller part of the meson8b clock controller has to be registered early (which I did through CLK_OF_DECLARE_DRIVER), because the secondary cores are started *very* early in the boot process (and meson8b_clkc_probe is invoked long after we need the reset controller to be available for booting the secondary CPU cores).
The user of the reset-controller (= the patches which enable SMP and CPU hotplug support) will follow in the next days. I decided to split this because the SMP series will probably consist of 6 patches alone (and may need to go through two separate trees).
Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to CLKC_RESET_ to clearly indicate that these are provided by the clock controller (unlike the preprocessor macros for the reset lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches
Changes since v1 at [0]:
- updated cover letter description as we are now registering more than four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that the reset identifiers are preprocessor macros in dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these macros at all)
- patch #2 (previously part of patch #1) now registers all known reset lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
Martin Blumenstingl (3):
dt-bindings: clock: meson8b: describe the embedded reset controller
clk: meson: meson8b: register the built-in reset controller
ARM: dts: meson: mark the clock controller also as reset controller
Quoted 11 lines
 .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
-
 drivers/clk/meson/meson8b.h                        |   9 +-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
 7 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

Quoted 7 lines

Series looks good to me overall.
Acked-by Jerome Brunet <[email protected]>
Just one thing, which is not an issue really, I wonder if the dt-bindings documentation and the bindings them-self should be in separate patches ?

Hi Martin,

Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.

Kevin, patch 3 is all yours !

Thanks,
Neil

Martin Blumenstingl

author reviewer

2017-08-01 18:53 UTC #7 lore raw

v3 cover add the reset controller to the Meson8b clkc

Hi Neil,

Quoted 71 lines · Neil Armstrong

Quoted 70 lines · Jerome Brunet
Quoted 53 lines · Martin Blumenstingl
This registers the known (soft) reset lines provided by the clock controller's registers.
This is the first preparation step for SMP and CPU hotplug support on Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs requires asserting and de-asserting a reset line (one for each CPU core). These reset lines are provided by the clock controller.
The reset controller part of the meson8b clock controller has to be registered early (which I did through CLK_OF_DECLARE_DRIVER), because the secondary cores are started *very* early in the boot process (and meson8b_clkc_probe is invoked long after we need the reset controller to be available for booting the secondary CPU cores).
The user of the reset-controller (= the patches which enable SMP and CPU hotplug support) will follow in the next days. I decided to split this because the SMP series will probably consist of 6 patches alone (and may need to go through two separate trees).
Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to CLKC_RESET_ to clearly indicate that these are provided by the clock controller (unlike the preprocessor macros for the reset lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches
Changes since v1 at [0]:
- updated cover letter description as we are now registering more than four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that the reset identifiers are preprocessor macros in dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these macros at all)
- patch #2 (previously part of patch #1) now registers all known reset lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
Martin Blumenstingl (3):
dt-bindings: clock: meson8b: describe the embedded reset controller
clk: meson: meson8b: register the built-in reset controller
ARM: dts: meson: mark the clock controller also as reset controller
Quoted 11 lines
 .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
-
 drivers/clk/meson/meson8b.h                        |   9 +-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
 7 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
Series looks good to me overall.
Acked-by Jerome Brunet <[email protected]>

Quoted 7 lines

Quoted 3 lines
Just one thing, which is not an issue really, I wonder if the dt-bindings documentation and the bindings them-self should be in separate patches ?
Hi Martin,
Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.

thank you!
I'm also fine with either way - I chose to include it in the dt-bindings patch due to two reasons:
- my SMP series depends on this header file
- we typically send header updates with a dt-bindings patch (see your AO CEC clock for example)
with these I thought it makes sense to combine the documentation and the header in the dt-bindings patch - if it's an issue I can simply change it

may be the DT-maintainers can comment on this?

anyway, thanks for taking care!

Quoted 4 lines

Kevin, patch 3 is all yours !
Thanks,
Neil

Martin

Kevin Hilman

maintainer Applied

2017-08-01 19:34 UTC #8 lore raw

v3 cover add the reset controller to the Meson8b clkc

Quoted 91 lines · Martin Blumenstingl

Hi Neil,
Quoted 71 lines · Neil Armstrong
Quoted 70 lines · Jerome Brunet
Quoted 53 lines · Martin Blumenstingl
This registers the known (soft) reset lines provided by the clock controller's registers.
This is the first preparation step for SMP and CPU hotplug support on Meson8/Meson8b/Meson8m2. Booting the secondary cores on these SoCs requires asserting and de-asserting a reset line (one for each CPU core). These reset lines are provided by the clock controller.
The reset controller part of the meson8b clock controller has to be registered early (which I did through CLK_OF_DECLARE_DRIVER), because the secondary cores are started *very* early in the boot process (and meson8b_clkc_probe is invoked long after we need the reset controller to be available for booting the secondary CPU cores).
The user of the reset-controller (= the patches which enable SMP and CPU hotplug support) will follow in the next days. I decided to split this because the SMP series will probably consist of 6 patches alone (and may need to go through two separate trees).
Changes since v2 at [3]:
- move the reset line preprocessor defines into a separate file (affects patch #1 as this header file is part of the dt-binding)
- rename the reset line preprocessor macros from RESETID_ to CLKC_RESET_ to clearly indicate that these are provided by the clock controller (unlike the preprocessor macros for the reset lines in the standlone reset controller, which start with RESET_)
- updated patch #2 due to the changes mentioned above
- added Neil's Reviewed-by to all patches
Changes since v1 at [0]:
- updated cover letter description as we are now registering more than four reset lines
- split patch #1 into a dt-binding and clk driver patch
- slightly reworded the dt-binding documentation so it's now clear that the reset identifiers are preprocessor macros in dt-bindings/clock/meson8b-clkc.h (v1 of this series didn't have these macros at all)
- patch #2 (previously part of patch #1) now registers all known reset lines (see [1] and [2] for the results of my detective work)
- patch #3 is untouched
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004283.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004330.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004347.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
Martin Blumenstingl (3):
dt-bindings: clock: meson8b: describe the embedded reset controller
clk: meson: meson8b: register the built-in reset controller
ARM: dts: meson: mark the clock controller also as reset controller
Quoted 11 lines
 .../bindings/clock/amlogic,meson8b-clkc.txt        |   9 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 159 +++++++++++++++++++-
-
 drivers/clk/meson/meson8b.h                        |   9 +-
 .../dt-bindings/reset/amlogic,meson8b-clkc-reset.h |  27 ++++
 7 files changed, 193 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
Series looks good to me overall.
Acked-by Jerome Brunet <[email protected]>
Quoted 7 lines
Quoted 3 lines
Just one thing, which is not an issue really, I wonder if the dt-bindings documentation and the bindings them-self should be in separate patches ?
Hi Martin,
Anyway it's OK for me, I've applied patches 1 & 2 on the clk-meson's next branches.
thank you!
I'm also fine with either way - I chose to include it in the dt-bindings patch due to two reasons:
- my SMP series depends on this header file
- we typically send header updates with a dt-bindings patch (see your AO CEC clock for example)
with these I thought it makes sense to combine the documentation and the header in the dt-bindings patch - if it's an issue I can simply change it

Quoted 1 line

may be the DT-maintainers can comment on this?

If it was a new binding, or significant change, it would be better to send bindings as a separate patch, but in this case, it should be fine.

Quoted 1 line

Quoted 1 line
Kevin, patch 3 is all yours !

Applied to v4.14/dt,

Thanks,

Kevin