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ARM64: dts: meson-gx: consistently use the GIC_SPI and IRQ type macros

PATCH New Martin Blumenstingl 3 participants 3 messages Jul 16, 2017 – Jul 28, 2017

Subsystems (2)
Device tree bindings Arm/Amlogic Meson SoC support
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Martin Blumenstingl

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#0 lore raw

PATCH 1/1 ARM64: dts: meson-gx: consistently use the GIC_SPI and IRQ type macros

the mailbox and ethmac nodes used the magic number "0" instead of the GIC_SPI preprocessor macro. Additionally the ethmac used the magic number "1" instead of IRQ_TYPE_EDGE_RISING.
Fix this to make the .dtsi easier to read.

Signed-off-by Martin Blumenstingl <[email protected]>
---
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +4 -4
index 35b8c88c3220..492e6a24349a 100644
@@ -437,9 +437,9 @@
 			mailbox: mailbox at 404 {
 				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 				reg = <0 0x404 0 0x4c>;
-				interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
-					     <0 209 IRQ_TYPE_EDGE_RISING>,
-					     <0 210 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+					     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+					     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
 				#mbox-cells = <1>;
 			};
 		};

@@ -448,7 +448,7 @@
 			compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 			reg = <0x0 0xc9410000 0x0 0x10000
 			       0x0 0xc8834540 0x0 0x4>;
-			interrupts = <0 8 1>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "macirq";
 			status = "disabled";
 		};
Signature · 1 line
2.13.3
#1 lore raw

PATCH 1/1 ARM64: dts: meson-gx: consistently use the GIC_SPI and IRQ type macros

Quoted 29 lines · Martin Blumenstingl

the mailbox and ethmac nodes used the magic number "0" instead of the GIC_SPI preprocessor macro. Additionally the ethmac used the magic number "1" instead of IRQ_TYPE_EDGE_RISING.
Fix this to make the .dtsi easier to read.

Signed-off-by Martin Blumenstingl <[email protected]>
---
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +3 -3
index 35b8c88c3220..492e6a24349a 100644
@@ -437,9 +437,9 @@
 			mailbox: mailbox at 404 {
 				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 				reg = <0 0x404 0 0x4c>;
-				interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
-					     <0 209 IRQ_TYPE_EDGE_RISING>,
-					     <0 210 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+					     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+					     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
 				#mbox-cells = <1>;
 			};
 		};

arch/arm64/boot/dts/amlogic/meson-gx.dtsi line 454

Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +1 -1
@@ -448,7 +448,7 @@
 			compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 			reg = <0x0 0xc9410000 0x0 0x10000
 			       0x0 0xc8834540 0x0 0x4>;
-			interrupts = <0 8 1>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "macirq";
 			status = "disabled";
 		};
Reviewed-by Neil Armstrong <[email protected]>
maintainer Applied
#2 lore raw

PATCH 1/1 ARM64: dts: meson-gx: consistently use the GIC_SPI and IRQ type macros

In reply to Martin Blumenstingl
Quoted 6 lines · Martin Blumenstingl

the mailbox and ethmac nodes used the magic number "0" instead of the GIC_SPI preprocessor macro. Additionally the ethmac used the magic number "1" instead of IRQ_TYPE_EDGE_RISING.
Fix this to make the .dtsi easier to read.

Signed-off-by Martin Blumenstingl <[email protected]>

Applied to v4.14/dt64,

Kevin