ARM: EXYNOS: reset KFC cores when cpu is up
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
The cpu booting of exynos5422 has been still broken since we discussed it in last year[1]. This patch is inspired from odroid xu3 code(Actually, it was from samsung exynos vendor kernel)[2]. This weird reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the little core(kingfisher core). Some of the exynos5420 boards and all of the exynos5422 boards will be required this code.
There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] gpio value and the other is checking the cluster number of the first cpu. I selected the latter because it's more easier than the former.
Changes since RFC[3]:
- drop checking soc_is_exynos5800 to extend this codes to exynos5420/5422 boards.
- kfc cores will be reset only if the cpu0 is kfc core.
- Rebase top of the kukjin's for-next branch
[1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
--- arch/arm/mach-exynos/mcpm-exynos.c | 18 +++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-)
arch/arm/mach-exynos/mcpm-exynos.c +17 -1
@@ -20,6 +20,7 @@#include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> +#include <asm/smp_plat.h> #include "regs-pmu.h" #include "common.h"
@@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS)return -EINVAL ; -exynos_cpu_power_up (cpunr); +if (!exynos_cpu_power_state (cpunr)) { +exynos_cpu_power_up (cpunr); + +/* This assumes the cluster number of the eagle is 0 and the +* kfc is 1. When the system was booted from the kfc core, +* they should be reset */ +if (cluster && + cluster ==MPIDR_AFFINITY_LEVEL (cpu_logical_map (0 ),1 )) { +while (!pmu_raw_readl (S5P_PMU_SPARE2 )) +udelay (10 ); + +pmu_raw_writel (EXYNOS5420_KFC_CORE_RESET (cpu), +EXYNOS_SWRESET ); + } + } +return 0 ; }
arch/arm/mach-exynos/regs-pmu.h +6 -0
@@ -513,6 +513,12 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)#define SPREAD_ENABLE 0xF#define SPREAD_USE_STANDWFI 0xF +#define EXYNOS5420_KFC_CORE_RESET0 BIT(8) +#define EXYNOS5420_KFC_ETM_RESET0 BIT(20) + +#define EXYNOS5420_KFC_CORE_RESET (_nr) \ + ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) +#define EXYNOS5420_BB_CON1 0x0784#define EXYNOS5420_BB_SEL_EN BIT(31)#define EXYNOS5420_BB_PMOS_EN BIT(7)
Signature · 1 line
2.1.0
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
Quoted 51 lines · Chanho Park
The cpu booting of exynos5422 has been still broken since we discussed it in last year[1]. This patch is inspired from odroid xu3
code(Actually, it was from samsung exynos vendor kernel)[2]. This weird reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the little core(kingfisher core). Some of the exynos5420 boards and all of the exynos5422 boards will be required this code.
There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] gpio value and the other is checking the cluster number of the first cpu. I selected the latter because it's more easier than the former.Changes since RFC[3]:
- drop checkingsoc_is_exynos5800to extend this codes to exynos5420/5422 boards.
- kfc cores will be reset only if the cpu0 is kfc core.
- Rebase top of the kukjin's for-next branch[1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
Cc Joonyoung Shim <[email protected]>Cc Chanwoo Choi <[email protected]>Cc Kevin Hilman <[email protected]>Cc Heesub Shin <[email protected]>Cc Mauro Ribeiro <[email protected]>Cc Abhilash Kesavan <[email protected]>Cc Przemyslaw Marczak <[email protected]>Cc Marek Szyprowski <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Signed-off-by Chanho Park <[email protected]>--- arch/arm/mach-exynos/mcpm-exynos.c | 18 +++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-)arch/arm/mach-exynos/mcpm-exynos.c +1
-0@@ -20,6 +20,7 @@#include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> +#include <asm/smp_plat.h> #include "regs-pmu.h" #include "common.h"
arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 79
Quoted 10 lines
arch/arm/mach-exynos/mcpm-exynos.c +6
-1@@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS)return -EINVAL ; -exynos_cpu_power_up (cpunr); +if (!exynos_cpu_power_state (cpunr)) { +exynos_cpu_power_up (cpunr); + +/* This assumes the cluster number of the eagle is 0 and the +* kfc is 1. When the system was booted from the kfc core, +* they should be reset */
minor: fix multi-line comment style (search for 'multi-line' in Documentation/CodingStyle)
Also minor, but personally, I prefer seeing A15/A7 instead of eagle/KFC as those names are fading from my memory and I can't seem to remember which one is which. :/
arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 91
Quoted 12 lines
arch/arm/mach-exynos/mcpm-exynos.c +10
-0+if (cluster && + cluster ==MPIDR_AFFINITY_LEVEL (cpu_logical_map (0 ),1 )) { +while (!pmu_raw_readl (S5P_PMU_SPARE2 )) +udelay (10 ); + +pmu_raw_writel (EXYNOS5420_KFC_CORE_RESET (cpu), +EXYNOS_SWRESET ); + } + } +return 0 ; }
I tested this on top of mainline (v4.2) using exynos_defconfig (with BL_SWITCHER disabled) and I now see all 8 CPUs booting. Nice!
Also, please note that this does not fix another fundamental problem with this board in that the firmware puts CCI into secure mode, so linux/MCPM cannot manage it, causing hangs whenever CPUidle is enabled (because b.L cpuidle driver tries to use MCPM, which needs to manage CCI.)
In order for this to not hang when using CPUidle, the following patch is also needed.
Kevin
(quoted diff) +0 -0
b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 78e6a502f320..7891bd05bf8e 100644
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3 -0
@@ -49,3 +49,11 @@ shunt-resistor = <10000>; }; }; + +/* + * Secure firmware prevents CCI access/usage from linux, so must be
disabled
+ * to prevent usage by MCPM.
+ */
+&cci {
+ status = "disabled";
+};
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
[adding Krzysztof Kozlowski to cc list]
Hello Kevin,
Quoted 118 lines · Kevin Hilman
Quoted 51 lines · Chanho Park
The cpu booting of exynos5422 has been still broken since we discussed it in last year[1]. This patch is inspired from odroid xu3
code(Actually, it was from samsung exynos vendor kernel)[2]. This weird reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the little core(kingfisher core). Some of the exynos5420 boards and all of the exynos5422 boards will be required this code.
There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] gpio value and the other is checking the cluster number of the first cpu. I selected the latter because it's more easier than the former.Changes since RFC[3]:
- drop checkingsoc_is_exynos5800to extend this codes to exynos5420/5422 boards.
- kfc cores will be reset only if the cpu0 is kfc core.
- Rebase top of the kukjin's for-next branch[1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
Cc Joonyoung Shim <[email protected]>Cc Chanwoo Choi <[email protected]>Cc Kevin Hilman <[email protected]>Cc Heesub Shin <[email protected]>Cc Mauro Ribeiro <[email protected]>Cc Abhilash Kesavan <[email protected]>Cc Przemyslaw Marczak <[email protected]>Cc Marek Szyprowski <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Signed-off-by Chanho Park <[email protected]>--- arch/arm/mach-exynos/mcpm-exynos.c | 18 +++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-)arch/arm/mach-exynos/mcpm-exynos.c +1
-0@@ -20,6 +20,7 @@#include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> +#include <asm/smp_plat.h> #include "regs-pmu.h" #include "common.h" arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 79
Quoted 10 lines
arch/arm/mach-exynos/mcpm-exynos.c +6
-1@@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS)return -EINVAL ; -exynos_cpu_power_up (cpunr); +if (!exynos_cpu_power_state (cpunr)) { +exynos_cpu_power_up (cpunr); + +/* This assumes the cluster number of the eagle is 0 and the +* kfc is 1. When the system was booted from the kfc core, +* they should be reset */ minor: fix multi-line comment style (search for 'multi-line' in
Documentation/CodingStyle)Also minor, but personally, I prefer seeing A15/A7 instead of eagle/KFC as those names are fading from my memory and I can't seem to remember which one is which. :/
arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 91
Quoted 12 lines
arch/arm/mach-exynos/mcpm-exynos.c +10
-0+if (cluster && + cluster ==MPIDR_AFFINITY_LEVEL (cpu_logical_map (0 ),1 )) { +while (!pmu_raw_readl (S5P_PMU_SPARE2 )) +udelay (10 ); + +pmu_raw_writel (EXYNOS5420_KFC_CORE_RESET (cpu), +EXYNOS_SWRESET ); + } + } +return 0 ; }I tested this on top of mainline (v4.2) using
exynos_defconfig(withBL_SWITCHERdisabled) and I now see all 8 CPUs booting. Nice!Tested-by Kevin Hilman <[email protected]>Also, please note that this does not fix another fundamental problem with this board in that the firmware puts CCI into secure mode, so linux/MCPM cannot manage it, causing hangs whenever CPUidle is enabled (because b.L cpuidle driver tries to use MCPM, which needs to manage CCI.)
In order for this to not hang when using CPUidle, the following patch is also needed.
Kevin
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3
-0@@ -49,3 +49,11 @@ shunt-resistor = <10000>; }; }; + +/* + * Secure firmware prevents CCI access/usage from linux, so must bedisabled
+ * to prevent usage by MCPM.
+ */
+&cci {
arch/arm/boot/dts/exynos5422-odroidxu3.dts
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3.dts +2
-0+ status = "disabled"; +};
I posted a similar patch that instead disabling CCI for the XU3 board, it disables in exynos5422-odroidxu3-common.dtsi since all Exynos5422 Odroid boards have the same broken firmware and so the same issue:
https://lkml.org/lkml/2015/8/29/59
Krzysztof tested it on an Odroid XU3 Lite and reported that disabling CCI caused some CPUs to fail to boot even with $subject applied:
https://lkml.org/lkml/2015/8/29/65
Did you succeed booting all CPUs with CONFIG_ARM_BIG_LITTLE_CPUIDLE enabled and CCI disabled in the the Odroid XU3 DTS?
Best regards,
Signature · 3 lines
Javier Martinez Canillas Open Source Group Samsung Research America
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
Quoted 131 lines · Javier Martinez Canillas
[adding Krzysztof Kozlowski to cc list]
Hello Kevin,
Quoted 118 lines · Kevin Hilman
Quoted 51 lines · Chanho Park
The cpu booting of exynos5422 has been still broken since we discussed it in last year[1]. This patch is inspired from odroid xu3
code(Actually, it was from samsung exynos vendor kernel)[2]. This weird reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the little core(kingfisher core). Some of the exynos5420 boards and all of the exynos5422 boards will be required this code.
There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] gpio value and the other is checking the cluster number of the first cpu. I selected the latter because it's more easier than the former.Changes since RFC[3]:
- drop checkingsoc_is_exynos5800to extend this codes to exynos5420/5422 boards.
- kfc cores will be reset only if the cpu0 is kfc core.
- Rebase top of the kukjin's for-next branch[1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
Cc Joonyoung Shim <[email protected]>Cc Chanwoo Choi <[email protected]>Cc Kevin Hilman <[email protected]>Cc Heesub Shin <[email protected]>Cc Mauro Ribeiro <[email protected]>Cc Abhilash Kesavan <[email protected]>Cc Przemyslaw Marczak <[email protected]>Cc Marek Szyprowski <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Signed-off-by Chanho Park <[email protected]>--- arch/arm/mach-exynos/mcpm-exynos.c | 18 +++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-)arch/arm/mach-exynos/mcpm-exynos.c +1
-0@@ -20,6 +20,7 @@#include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> +#include <asm/smp_plat.h> #include "regs-pmu.h" #include "common.h" arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 79
Quoted 10 lines
arch/arm/mach-exynos/mcpm-exynos.c +6
-1@@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS)return -EINVAL ; -exynos_cpu_power_up (cpunr); +if (!exynos_cpu_power_state (cpunr)) { +exynos_cpu_power_up (cpunr); + +/* This assumes the cluster number of the eagle is 0 and the +* kfc is 1. When the system was booted from the kfc core, +* they should be reset */ minor: fix multi-line comment style (search for 'multi-line' in
Documentation/CodingStyle)Also minor, but personally, I prefer seeing A15/A7 instead of eagle/KFC as those names are fading from my memory and I can't seem to remember which one is which. :/
arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 91
Quoted 12 lines
arch/arm/mach-exynos/mcpm-exynos.c +10
-0+if (cluster && + cluster ==MPIDR_AFFINITY_LEVEL (cpu_logical_map (0 ),1 )) { +while (!pmu_raw_readl (S5P_PMU_SPARE2 )) +udelay (10 ); + +pmu_raw_writel (EXYNOS5420_KFC_CORE_RESET (cpu), +EXYNOS_SWRESET ); + } + } +return 0 ; }I tested this on top of mainline (v4.2) using
exynos_defconfig(withBL_SWITCHERdisabled) and I now see all 8 CPUs booting. Nice!Tested-by Kevin Hilman <[email protected]>Also, please note that this does not fix another fundamental problem with this board in that the firmware puts CCI into secure mode, so linux/MCPM cannot manage it, causing hangs whenever CPUidle is enabled (because b.L cpuidle driver tries to use MCPM, which needs to manage CCI.)
In order for this to not hang when using CPUidle, the following patch is also needed.
Kevin
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3
-0@@ -49,3 +49,11 @@ shunt-resistor = <10000>; }; }; + +/* + * Secure firmware prevents CCI access/usage from linux, so must bedisabled
+ * to prevent usage by MCPM.
+ */
+&cci {arch/arm/boot/dts/exynos5422-odroidxu3.dts
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3.dts +2
-0+ status = "disabled"; +};I posted a similar patch that instead disabling CCI for the XU3 board, it disables in
exynos5422-odroidxu3-common.dtsisince all Exynos5422 Odroid boards have the same broken firmware and so the same issue:
Quoted 6 lines
https://lkml.org/lkml/2015/8/29/59
Krzysztof tested it on an Odroid XU3 Lite and reported that disabling CCI caused some CPUs to fail to boot even with $subject applied:
Indeed. On Odroid XU3 Chanho's patch gives me 8 CPUs up. Disabling CCI causes fails on CPU{5,6,7} (Cortex-A15).
Best regards,
Krzysztof
Quoted 6 lines
Did you succeed booting all CPUs with
CONFIG_ARM_BIG_LITTLE_CPUIDLEenabled and CCI disabled in the the Odroid XU3 DTS?Best regards,
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
Hi,
Quoted 134 lines · Krzysztof Kozlowski
Quoted 133 lines · Javier Martinez Canillas
[adding Krzysztof Kozlowski to cc list]
Hello Kevin,
Quoted 118 lines · Kevin Hilman
Quoted 51 lines · Chanho Park
The cpu booting of exynos5422 has been still broken since we discussed it in last year[1]. This patch is inspired from odroid xu3
code(Actually, it was from samsung exynos vendor kernel)[2]. This weird reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the little core(kingfisher core). Some of the exynos5420 boards and all of the exynos5422 boards will be required this code.
There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] gpio value and the other is checking the cluster number of the first cpu. I selected the latter because it's more easier than the former.Changes since RFC[3]:
- drop checkingsoc_is_exynos5800to extend this codes to exynos5420/5422 boards.
- kfc cores will be reset only if the cpu0 is kfc core.
- Rebase top of the kukjin's for-next branch[1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
Cc Joonyoung Shim <[email protected]>Cc Chanwoo Choi <[email protected]>Cc Kevin Hilman <[email protected]>Cc Heesub Shin <[email protected]>Cc Mauro Ribeiro <[email protected]>Cc Abhilash Kesavan <[email protected]>Cc Przemyslaw Marczak <[email protected]>Cc Marek Szyprowski <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Signed-off-by Chanho Park <[email protected]>--- arch/arm/mach-exynos/mcpm-exynos.c | 18 +++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-)arch/arm/mach-exynos/mcpm-exynos.c +1
-0@@ -20,6 +20,7 @@#include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> +#include <asm/smp_plat.h> #include "regs-pmu.h" #include "common.h" arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 79
Quoted 10 lines
arch/arm/mach-exynos/mcpm-exynos.c +6
-1@@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS)return -EINVAL ; -exynos_cpu_power_up (cpunr); +if (!exynos_cpu_power_state (cpunr)) { +exynos_cpu_power_up (cpunr); + +/* This assumes the cluster number of the eagle is 0 and the +* kfc is 1. When the system was booted from the kfc core, +* they should be reset */ minor: fix multi-line comment style (search for 'multi-line' in
Documentation/CodingStyle)Also minor, but personally, I prefer seeing A15/A7 instead of eagle/KFC as those names are fading from my memory and I can't seem to remember which one is which. :/
arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 91
Quoted 12 lines
arch/arm/mach-exynos/mcpm-exynos.c +10
-0+if (cluster && + cluster ==MPIDR_AFFINITY_LEVEL (cpu_logical_map (0 ),1 )) { +while (!pmu_raw_readl (S5P_PMU_SPARE2 )) +udelay (10 ); + +pmu_raw_writel (EXYNOS5420_KFC_CORE_RESET (cpu), +EXYNOS_SWRESET ); + } + } +return 0 ; }I tested this on top of mainline (v4.2) using
exynos_defconfig(withBL_SWITCHERdisabled) and I now see all 8 CPUs booting. Nice!Tested-by Kevin Hilman <[email protected]>Also, please note that this does not fix another fundamental problem with this board in that the firmware puts CCI into secure mode, so linux/MCPM cannot manage it, causing hangs whenever CPUidle is enabled (because b.L cpuidle driver tries to use MCPM, which needs to manage CCI.)
In order for this to not hang when using CPUidle, the following patch is also needed.
Kevin
arch/arm/boot/dts/exynos5422-odroidxu3.dts +3
-0@@ -49,3 +49,11 @@ shunt-resistor = <10000>; }; }; + +/* + * Secure firmware prevents CCI access/usage from linux, so must bedisabled
+ * to prevent usage by MCPM.
+ */
+&cci {arch/arm/boot/dts/exynos5422-odroidxu3.dts
Quoted 2 lines
arch/arm/boot/dts/exynos5422-odroidxu3.dts +2
-0+ status = "disabled"; +};I posted a similar patch that instead disabling CCI for the XU3 board, it disables in
exynos5422-odroidxu3-common.dtsisince all Exynos5422 Odroid boards have the same broken firmware and so the same issue:
Quoted 7 lines
Quoted 4 lines
Krzysztof tested it on an Odroid XU3 Lite and reported that disabling CCI caused some CPUs to fail to boot even with $subject applied:
Indeed. On Odroid XU3 Chanho's patch gives me 8 CPUs up. Disabling CCI causes fails on CPU{5,6,7} (Cortex-A15).
Chanho's patch is for the exynos mcpm back-end. However, when we disable CCI the mcpm code is bypassed and we default to the code in exynos' platsmp.c/firmware.c. If the A7s were failing to boot-up then the reason could have been that Chanho's workaround was not being executed after applying the CCI disablement patch. According to the comments the A15s are not booting and so the exynos_boot_secondary function needs to be checked further.
Regards,
Abhilash
Quoted 16 lines
Best regards,
KrzysztofQuoted 6 lines
Did you succeed booting all CPUs with
CONFIG_ARM_BIG_LITTLE_CPUIDLEenabled and CCI disabled in the the Odroid XU3 DTS?Best regards,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
Quoted 3 lines · Abhilash Kesavan
Quoted 1 line · Krzysztof Kozlowski
On 01.09.2015 07:46, Javier Martinez Canillas wrote:
[...]
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
I posted a similar patch that instead disabling CCI for the XU3 board, it disables in
exynos5422-odroidxu3-common.dtsisince all Exynos5422 Odroid boards have the same broken firmware and so the same issue:
OK, that makes more sense. Thanks.
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Krzysztof tested it on an Odroid XU3 Lite and reported that disabling CCI caused some CPUs to fail to boot even with $subject applied:
https://lkml.org/lkml/2015/8/29/65
Did you succeed booting all CPUs with
CONFIG_ARM_BIG_LITTLE_CPUIDLEenabled and CCI disabled in the the Odroid XU3 DTS?
I thought so, but re-testing I'm seein the same results as Krzysztof:
Quoted 10 lines
Quoted 2 lines
Indeed. On Odroid XU3 Chanho's patch gives me 8 CPUs up. Disabling CCI causes fails on CPU{5,6,7} (Cortex-A15).
Chanho's patch is for the exynos mcpm back-end. However, when we disable CCI the mcpm code is bypassed and we default to the code in exynos'
platsmp.c/firmware.c. If the A7s were failing to boot-up then the reason could have been that Chanho's workaround was not being executed after applying the CCI disablement patch. According to the comments the A15s are not booting and so theexynos_boot_secondaryfunction needs to be checked further.
Thanks for the explanation. That makes sense. $SUBJECT fix should be made so it works for both scenarios.
Kevin
PATCH 1/1 ARM: EXYNOS: reset KFC cores when cpu is up
In reply to Chanho ParkQuoted 1 line · Chanho Park
The cpu booting of exynos5422 has been still broken since we discussed
s/cpu/CPU/ (here and in other places)
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it in last year[1]. This patch is inspired from odroid xu3
s/odroid xu3/Odroid XU3/
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code(Actually, it was from samsung exynos vendor kernel)[2]. This weird
Space before parenthesis.
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reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the little core(kingfisher core).
Again space before parenthesis.
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Some of the exynos5420 boards and all of the exynos5422 boards will be required this code.
s/will be required/require/
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There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] gpio value and the other is checking the cluster
s/gpio/GPIO/
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number of the first cpu. I selected the latter because it's more easier than the former.
Changes since RFC[3]:
- drop checkingsoc_is_exynos5800to extend this codes to exynos5420/5422 boards.
- kfc cores will be reset only if the cpu0 is kfc core.
- Rebase top of the kukjin's for-next branch
Changelog and its references ([3]) goes after '---'.
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[1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ [3]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/356610.html
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Cc Joonyoung Shim <[email protected]>Cc Chanwoo Choi <[email protected]>Cc Kevin Hilman <[email protected]>Cc Heesub Shin <[email protected]>Cc Mauro Ribeiro <[email protected]>Cc Abhilash Kesavan <[email protected]>Cc Przemyslaw Marczak <[email protected]>Cc Marek Szyprowski <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Signed-off-by Chanho Park <[email protected]>
That's a huge CC-list. Everyone are important to CC? Definitely you can remove me because I appear as a maintainer. :)
I think you can leave only people who participated in the recent discussions.
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--- arch/arm/mach-exynos/mcpm-exynos.c | 18 +++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-)arch/arm/mach-exynos/mcpm-exynos.c +1
-0@@ -20,6 +20,7 @@#include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> +#include <asm/smp_plat.h> #include "regs-pmu.h" #include "common.h" @@ -70,7 +71,22 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS)return -EINVAL ;
arch/arm/mach-exynos/mcpm-exynos.c static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) · line 81
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arch/arm/mach-exynos/mcpm-exynos.c +8
-1-exynos_cpu_power_up (cpunr); +if (!exynos_cpu_power_state (cpunr)) { +exynos_cpu_power_up (cpunr); + +/* This assumes the cluster number of the eagle is 0 and the +* kfc is 1. When the system was booted from the kfc core, +* they should be reset */ +if (cluster && + cluster ==MPIDR_AFFINITY_LEVEL (cpu_logical_map (0 ),1 )) {
I already asked for that - please describe what happens here. Why we are spinning on SPARE2? At least one or two lines. Grepping through commits or mailing lists is less efficient than looking at comment at code.
Everything boils to firmware on Exynos5422 boards which uses SPARE2 as synchronisation mechanism. After powering up a CPU, if SPARE2 is not set to 1, then firmware (BL1 or code in IROM) spins over it and we can safely execute software reset.
The patch is itself good, just please fix these minor nits.
Best regards,
Krzysztof
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arch/arm/mach-exynos/mcpm-exynos.c +8
-0+while (!pmu_raw_readl (S5P_PMU_SPARE2 )) +udelay (10 ); + +pmu_raw_writel (EXYNOS5420_KFC_CORE_RESET (cpu), +EXYNOS_SWRESET ); + } + } +return 0 ; }arch/arm/mach-exynos/regs-pmu.h +6
-0@@ -513,6 +513,12 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)#define SPREAD_ENABLE 0xF#define SPREAD_USE_STANDWFI 0xF +#define EXYNOS5420_KFC_CORE_RESET0 BIT(8) +#define EXYNOS5420_KFC_ETM_RESET0 BIT(20) + +#define EXYNOS5420_KFC_CORE_RESET (_nr) \ + ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) +#define EXYNOS5420_BB_CON1 0x0784#define EXYNOS5420_BB_SEL_EN BIT(31)#define EXYNOS5420_BB_PMOS_EN BIT(7)