x86/mce: Add Zhaoxin CMCI support
Subsystems (3)
PATCH v3 3/4 x86/mce: Add Zhaoxin CMCI support
All Zhaoxin newer CPUs support CMCI that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin CMCI in mce/core.c and mce/intel.c.
Signed-off-by Tony W Wang-oc <[email protected]>
---v2->v3:
- Rework mce_zhaoxin_feature_init() as static
- Rework comment about Zhaoxin MCA SVAD and CMCI
- Simplify Zhaoxin CPU FMS checking
v1->v2:
- Fix redefinition of "mce_zhaoxin_feature_init"
arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/intel.c | 5 ++++- 2 files changed, 29 insertions(+), 1 deletion(-)
arch/x86/kernel/cpu/mce/core.c +25 -0
@@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c) } } +static void mce_zhaoxin_feature_init (struct cpuinfo_x86 *c) +{ +struct mce_bank *mce_banks =this_cpu_ptr (mce_banks_array); + +/* +* These CPUs have MCA bank 8, that only has one error called SVAD +* (System View Address Decoder) which be controlled by IA32_MC8.CTL.0 +* If enabled, the prefetch on these CPUs will cause SVAD machine +* check exception when virtual machine startup and cause system +* panic. Always disable bank 8 SVAD error by default. +*/ +if ((c->x86 ==7 && c->x86_model ==0x1b ) || + (c->x86_model ==0x19 || c->x86_model ==0x1f )) { +if (this_cpu_read (mce_num_banks) >8 ) + mce_banks[8 ].ctl =0 ; + } + +intel_init_cmci (); + mce_adjust_timer = cmci_intel_adjust_timer; +} +static void __mcheck_cpu_init_vendor (struct cpuinfo_x86 *c) {switch (c->x86_vendor) {
@@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)mce_centaur_feature_init (c);break ; +case X86_VENDOR_ZHAOXIN : +mce_zhaoxin_feature_init (c); +break ; +default :break ; }
arch/x86/kernel/cpu/mce/intel.c +4 -1
@@ -84,9 +84,12 @@ static int cmci_supported(int *banks)* Vendor check is not strictly needed, but the initial * initialization is vendor keyed and this * makes sure none of the backdoors are entered otherwise. +* Checks the vendor are Intel/Zhaoxin-specific: */ -if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL ) +if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor !=X86_VENDOR_ZHAOXIN )return 0 ; +if (!boot_cpu_has (X86_FEATURE_APIC ) ||lapic_get_maxlvt () <6 )return 0 ;rdmsrl (MSR_IA32_MCG_CAP , cap);
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2.7.4