Basic device tree support for StarFive JH7110 RISC-V SoC

From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/riscv/starfive.yaml +4 -0

index 5b36243fd674..64008c57e31f 100644
@@ -22,6 +22,10 @@ properties:
           - const: beagle,beaglev-starlight-jh7100-r0
           - const: starfive,jh7100
 
+      - items:
+          - const: starfive,visionfive-v2
+          - const: starfive,jh7110
+
 additionalProperties: true
 
...

Signature · 7 lines

2.38.1


_______________________________________________
linux-riscv mailing list
[email protected]
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From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html

From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/riscv/starfive.yaml +0 -0

index 5b36243fd674..64008c57e31f 100644

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -1

+          - const: starfive,jh7110
+
 additionalProperties: true
 
...
--

2.38.1

Quoted 5 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

Quoted 2 lines

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

Could you make these two into "Link:" tags please? Otherwise,

Reviewed-by Conor Dooley <[email protected]>

Quoted 20 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/riscv/starfive.yaml +0 -0

index 5b36243fd674..64008c57e31f 100644

Documentation/devicetree/bindings/riscv/starfive.yaml properties: · line 26

Quoted 5 lines

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -0

@@ -22,6 +22,10 @@ properties:
           - const: beagle,beaglev-starlight-jh7100-r0
           - const: starfive,jh7100
 
+      - items:
+          - const: starfive,visionfive-v2

I think StarFive has switched to just calling it VisionFive 2 and not V2. Please check up on this before committing to the compatible string.

Also there are going to be different revisions of the VisionFive 2 board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and starfive,visionfive-2-v1,2b early.

Quoted 4 lines

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -0

+          - const: starfive,jh7110
+
 additionalProperties: true

Quoted 31 lines · Emil Renner Berthing

Quoted 20 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/riscv/starfive.yaml +0 -0

index 5b36243fd674..64008c57e31f 100644

Documentation/devicetree/bindings/riscv/starfive.yaml properties: · line 26

Quoted 5 lines

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -0

@@ -22,6 +22,10 @@ properties:
           - const: beagle,beaglev-starlight-jh7100-r0
           - const: starfive,jh7100
 
+      - items:
+          - const: starfive,visionfive-v2

I think StarFive has switched to just calling it VisionFive 2 and not V2. Please check up on this before committing to the compatible string.

Quoted 3 lines

Also there are going to be different revisions of the VisionFive 2 board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and starfive,visionfive-2-v1,2b early.

I checked that the official name of this board is "VisionFive 2". The board has version A and version B, which are different in gmac and phy chip. The version A board has one 1000M and one 100M Ethernet ports while the version B board has two 1000M Ethernet ports. In dts, they have different configuration parameters for gmac. So I would like to distinguish them by two compatibles as below in the next version.

- items:
- enum:
- starfive,visionfive-2-va
- starfive,visionfive-2-vb
- const: starfive,jh7110

Best regards,
Hal

Quoted 4 lines

Quoted 4 lines

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -0

+          - const: starfive,jh7110
+
 additionalProperties: true

Quoted 44 lines · Hal Feng

Quoted 31 lines · Emil Renner Berthing

Quoted 20 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add device tree bindings for the StarFive JH7110 RISC-V SoC [1] and the VisionFive2 board [2] equipped with it.

[1]: https://doc-en.rvspace.org/Doc_Center/jh7110.html
[2]: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/riscv/starfive.yaml +0 -0

index 5b36243fd674..64008c57e31f 100644

Documentation/devicetree/bindings/riscv/starfive.yaml properties: · line 26

Quoted 5 lines

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -0

@@ -22,6 +22,10 @@ properties:
           - const: beagle,beaglev-starlight-jh7100-r0
           - const: starfive,jh7100
 
+      - items:
+          - const: starfive,visionfive-v2

I think StarFive has switched to just calling it VisionFive 2 and not V2. Please check up on this before committing to the compatible string.

Quoted 3 lines

Also there are going to be different revisions of the VisionFive 2 board, so maybe consider adding eg. starfive,visionfive-2-v1.1 and starfive,visionfive-2-v1,2b early.

I checked that the official name of this board is "VisionFive 2". The board has version A and version B, which are different in gmac and phy chip. The version A board has one 1000M and one 100M Ethernet ports while the version B board has two 1000M Ethernet ports. In dts, they have different configuration parameters for gmac. So I would like to distinguish them by two compatibles as below in the next version.

Quoted 5 lines

- items:
- enum:
- starfive,visionfive-2-va
- starfive,visionfive-2-vb
- const: starfive,jh7110

Cool. Though the silkscreen on my board says "VisionFive 2 V1.2B" so I think it would be less confusing if you used that as the model, and "starfive,visionfive-2-v1.2b" as the compatible string for the board.

Quoted 10 lines

Best regards,
Hal

Quoted 4 lines

Quoted 4 lines

Documentation/devicetree/bindings/riscv/starfive.yaml +2 -0

+          - const: starfive,jh7110
+
 additionalProperties: true

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 .../devicetree/bindings/riscv/sifive,ccache0.yaml          | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +6 -1

index bf3f07421f7e..262d1d49ce25 100644
@@ -25,6 +25,7 @@ select:
           - sifive,ccache0
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - starfive,jh7110-ccache
 
   required:
     - compatible

@@ -37,6 +38,7 @@ properties:
               - sifive,ccache0
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
+              - starfive,jh7110-ccache
           - const: cache
       - items:
           - const: microchip,mpfs-ccache

@@ -86,6 +88,7 @@ allOf:
             enum:
               - sifive,fu740-c000-ccache
               - microchip,mpfs-ccache
+              - starfive,jh7110-ccache
 
     then:
       properties:

@@ -105,7 +108,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: sifive,fu740-c000-ccache
+            enum:
+              - sifive,fu740-c000-ccache
+              - starfive,jh7110-ccache
 
     then:
       properties:

Signature · 7 lines

2.38.1


_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 49 lines

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 .../devicetree/bindings/riscv/sifive,ccache0.yaml          | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +6 -1

index bf3f07421f7e..262d1d49ce25 100644
@@ -25,6 +25,7 @@ select:
           - sifive,ccache0
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
+          - starfive,jh7110-ccache
 
   required:
     - compatible

@@ -37,6 +38,7 @@ properties:
               - sifive,ccache0
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
+              - starfive,jh7110-ccache
           - const: cache
       - items:
           - const: microchip,mpfs-ccache

@@ -86,6 +88,7 @@ allOf:
             enum:
               - sifive,fu740-c000-ccache
               - microchip,mpfs-ccache
+              - starfive,jh7110-ccache
 
     then:
       properties:

@@ -105,7 +108,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: sifive,fu740-c000-ccache
+            enum:
+              - sifive,fu740-c000-ccache
+              - starfive,jh7110-ccache
 
     then:
       properties:

Signature · 1 line

2.38.1

Quoted 4 lines

_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

Quoted 3 lines · Conor Dooley

Quoted 2 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Quoted 5 lines

Quoted 1 line

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Quoted 18 lines · Conor Dooley

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Quoted 7 lines

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Just like what microchip did as blow?

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache

- items:
- const: starfive,jh7110-ccache
- const: sifive,fu740-c000-ccache
- const: cache

Quoted 23 lines · Hal Feng

Quoted 22 lines · Conor Dooley

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

Quoted 5 lines

Quoted 3 lines

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Just like what microchip did as blow?

Quoted 16 lines

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache

No, I don't think this is correct either. You'd do something like:

Quoted 4 lines

- items:
- const: starfive,jh7110-ccache
- const: sifive,fu740-c000-ccache
- const: cache

And then the driver needs no changes.

Quoted 24 lines · Conor Dooley

Quoted 23 lines · Hal Feng

Quoted 22 lines · Conor Dooley

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

Quoted 5 lines

Quoted 5 lines

Quoted 3 lines

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Just like what microchip did as blow?

below

Quoted 22 lines

Quoted 16 lines

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache

No, I don't think this is correct either. You'd do something like:

Quoted 3 lines

- items:
- const: starfive,jh7110-ccache
- const: sifive,fu740-c000-ccache

Quoted 1 line

Quoted 1 line

- const: cache

Yeah, this is what I mean. Thanks.

Best regards,
Hal

Quoted 2 lines

And then the driver needs no changes.

Quoted 53 lines · Hal Feng

Quoted 24 lines · Conor Dooley

Quoted 23 lines · Hal Feng

Quoted 22 lines · Conor Dooley

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

Quoted 5 lines

Quoted 5 lines

Quoted 3 lines

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Just like what microchip did as blow?

below

Quoted 19 lines

Quoted 16 lines

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache

No, I don't think this is correct either. You'd do something like:

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

- items:
- const: starfive,jh7110-ccache
- const: sifive,fu740-c000-ccache

For the record I don't think the line above should be there. The fu7400-c000 is a specific tapeout and pretending the JH7110 is that tapeout is not right. Especially when there is already the "sifive,ccache0" string for the generic IP.

Quoted 11 lines

Quoted 2 lines

Quoted 2 lines

- const: cache

Yeah, this is what I mean. Thanks.

Best regards,
Hal

Quoted 2 lines

And then the driver needs no changes.

Quoted 53 lines · Hal Feng

Quoted 24 lines · Conor Dooley

Quoted 23 lines · Hal Feng

Quoted 22 lines · Conor Dooley

Quoted 11 lines · Hal Feng

Quoted 10 lines · Conor Dooley

Quoted 8 lines · Conor Dooley

Quoted 3 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This cache controller is also used on the StarFive JH7110 SoC.

"... and configured identically to that of the FU740"? Anyways,

Reviewed-by Conor Dooley <[email protected]>

Quoted 5 lines

Quoted 2 lines

Actually, after looking at the next patch - why can you not fall back to the fu740 one since you appear to have the same configuration as it?

Right, I will drop this patch and use "sifive,fu740-c000-ccache" as compatible in dts.

Uh, that's not quite what I was suggesting. Rather than using that one in isolation, you can do the following in your dt:
"starfive,jh7110-ccache", "sifive,fu740-c000-ccache"

Quoted 5 lines

Quoted 5 lines

Quoted 3 lines

And then in the driver we need to make no changes - unless down the line we find some sort of issue that requires special handling etc. There's no harm in having a "starfive,jh7110-ccache" IMO.

Just like what microchip did as blow?

below

Quoted 19 lines

Quoted 16 lines

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml:
properties:
compatible:
oneOf:
- items:
- enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- starfive,jh7110-ccache
- const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache

No, I don't think this is correct either. You'd do something like:

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

- items:
- const: starfive,jh7110-ccache
- const: sifive,fu740-c000-ccache

For the record I don't think the line above should be there. The fu7400-c000 is a specific tapeout and pretending the JH7110 is that tapeout is not right. Especially when there is already the "sifive,ccache0" string for the generic IP.

From: Emil Renner Berthing <[email protected]>

This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/Kconfig.socs            | 1 +
 drivers/soc/Makefile               | 2 +-
 drivers/soc/sifive/Kconfig         | 2 +-
 drivers/soc/sifive/sifive_ccache.c | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

arch/riscv/Kconfig.socs +0 -0

index 69774bb362d6..5a40e05f8cab 100644

Hey Emil/Hal,

Quoted 14 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/Kconfig.socs            | 1 +
 drivers/soc/Makefile               | 2 +-
 drivers/soc/sifive/Kconfig         | 2 +-
 drivers/soc/sifive/sifive_ccache.c | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

arch/riscv/Kconfig.socs config SOC_STARFIVE · line 25

Quoted 9 lines

arch/riscv/Kconfig.socs +1 -0

index 69774bb362d6..5a40e05f8cab 100644
@@ -22,6 +22,7 @@ config SOC_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
+	select SIFIVE_CCACHE

Please no. I am trying to get rid of these selects + I cannot figure out why this driver is so important that you *need* to select it. Surely the SoC is useable without it>
Is this a hang over from your vendor tree that uses the driver to do non-coherent stuff for the jh7100?

Quoted 9 lines

arch/riscv/Kconfig.socs +0 -0

 	select SIFIVE_PLIC
 	help
 	  This enables support for StarFive SoC platform hardware.

drivers/soc/Makefile +0 -0

index 69ba6508cf2c..534669840858 100644

drivers/soc/Makefile obj-y += qcom/ · line 29

Quoted 5 lines

drivers/soc/Makefile +1 -1

@@ -26,7 +26,7 @@ obj-y				+= qcom/
 obj-y				+= renesas/
 obj-y				+= rockchip/
 obj-$(CONFIG_SOC_SAMSUNG)	+= samsung/
-obj-$(CONFIG_SOC_SIFIVE)	+= sifive/
+obj-y				+= sifive/

This bit is fine.

drivers/soc/sifive/Kconfig line 3

Quoted 12 lines

drivers/soc/Makefile +0 -0

 obj-y				+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-y				+= ti/

drivers/soc/sifive/Kconfig +1 -1

index ed4c571f8771..e86870be34c9 100644
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE

As I suppose is this - but hardly scalable. I suppose it doesn't really matter.

drivers/soc/sifive/sifive_ccache.c static const struct of_device_id sifive_ccache_ids[] = { · line 110

Quoted 11 lines

drivers/soc/sifive/Kconfig +0 -0

 config SIFIVE_CCACHE
 	bool "Sifive Composable Cache controller"

drivers/soc/sifive/sifive_ccache.c +1 -0

index 1c171150e878..9489d1a90fbc 100644
@@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
 	{ .compatible = "sifive,fu540-c000-ccache" },
 	{ .compatible = "sifive,fu740-c000-ccache" },
 	{ .compatible = "sifive,ccache0" },
+	{ .compatible = "starfive,jh7110-ccache" },

Per my second reply to the previous patch, I am not sure why you do not just have a fallback compatible in the binding/dt for the fu740 ccache since you appear to have identical configuration?

Quoted 17 lines · Conor Dooley

Hey Emil/Hal,

Quoted 14 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/Kconfig.socs            | 1 +
 drivers/soc/Makefile               | 2 +-
 drivers/soc/sifive/Kconfig         | 2 +-
 drivers/soc/sifive/sifive_ccache.c | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

Quoted 15 lines

arch/riscv/Kconfig.socs config SOC_STARFIVE · line 25

Quoted 9 lines

arch/riscv/Kconfig.socs +1 -0

index 69774bb362d6..5a40e05f8cab 100644
@@ -22,6 +22,7 @@ config SOC_STARFIVE
    bool "StarFive SoCs"
    select PINCTRL
    select RESET_CONTROLLER
+   select SIFIVE_CCACHE

Please no. I am trying to get rid of these selects + I cannot figure out why this driver is so important that you *need* to select it. Surely the SoC is useable without it>
Is this a hang over from your vendor tree that uses the driver to do non-coherent stuff for the jh7100?

I have tested that the board can successfully boot up without the cache driver. The select can be removed for JH7110. @Emil, what do you think of this?

Quoted 33 lines

Quoted 9 lines

arch/riscv/Kconfig.socs +0 -0

    select SIFIVE_PLIC
    help
      This enables support for StarFive SoC platform hardware.

drivers/soc/Makefile +0 -0

index 69ba6508cf2c..534669840858 100644

drivers/soc/Makefile obj-y += qcom/ · line 29

Quoted 5 lines

drivers/soc/Makefile +1 -1

@@ -26,7 +26,7 @@ obj-y                             += qcom/
 obj-y                              += renesas/
 obj-y                              += rockchip/
 obj-$(CONFIG_SOC_SAMSUNG)  += samsung/
-obj-$(CONFIG_SOC_SIFIVE)   += sifive/
+obj-y                              += sifive/

This bit is fine.

drivers/soc/sifive/Kconfig line 3

Quoted 12 lines

drivers/soc/Makefile +0 -0

 obj-y                              += sunxi/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-y                              += ti/

drivers/soc/sifive/Kconfig +1 -1

index ed4c571f8771..e86870be34c9 100644
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE

As I suppose is this - but hardly scalable. I suppose it doesn't really matter.

Quoted 15 lines

drivers/soc/sifive/sifive_ccache.c static const struct of_device_id sifive_ccache_ids[] = { · line 110

Quoted 11 lines

drivers/soc/sifive/Kconfig +0 -0

 config SIFIVE_CCACHE
    bool "Sifive Composable Cache controller"

drivers/soc/sifive/sifive_ccache.c +1 -0

index 1c171150e878..9489d1a90fbc 100644
@@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
    { .compatible = "sifive,fu540-c000-ccache" },
    { .compatible = "sifive,fu740-c000-ccache" },
    { .compatible = "sifive,ccache0" },
+   { .compatible = "starfive,jh7110-ccache" },

Per my second reply to the previous patch, I am not sure why you do not just have a fallback compatible in the binding/dt for the fu740 ccache since you appear to have identical configuration?

Yeah, I will use the compatible of fu740 and modify this patch.

Best regards,
Hal

Quoted 21 lines · Hal Feng

Quoted 19 lines · Conor Dooley

Hey Emil/Hal,

arch/riscv/Kconfig.socs config SOC_STARFIVE · line 25

Quoted 11 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

arch/riscv/Kconfig.socs +1 -0

index 69774bb362d6..5a40e05f8cab 100644
@@ -22,6 +22,7 @@ config SOC_STARFIVE
    bool "StarFive SoCs"
    select PINCTRL
    select RESET_CONTROLLER
+   select SIFIVE_CCACHE

Please no. I am trying to get rid of these selects + I cannot figure out why this driver is so important that you *need* to select it. Surely the SoC is useable without it>
Is this a hang over from your vendor tree that uses the driver to do non-coherent stuff for the jh7100?

Quoted 3 lines

I have tested that the board can successfully boot up without the cache driver. The select can be removed for JH7110. @Emil, what do you think of this?

Yes, for the JH7110 this is not strictly needed, just like the Unmatched board. For the StarFive JH7100 it is though.
So if you're only adding support for the JH7110 then it's not needed.

Quoted 16 lines

Quoted 15 lines

drivers/soc/sifive/sifive_ccache.c static const struct of_device_id sifive_ccache_ids[] = { · line 110

Quoted 11 lines

arch/riscv/Kconfig.socs +0 -0

 config SIFIVE_CCACHE
    bool "Sifive Composable Cache controller"

drivers/soc/sifive/sifive_ccache.c +1 -0

index 1c171150e878..9489d1a90fbc 100644
@@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
    { .compatible = "sifive,fu540-c000-ccache" },
    { .compatible = "sifive,fu740-c000-ccache" },
    { .compatible = "sifive,ccache0" },
+   { .compatible = "starfive,jh7110-ccache" },

Per my second reply to the previous patch, I am not sure why you do not just have a fallback compatible in the binding/dt for the fu740 ccache since you appear to have identical configuration?

Quoted 1 line

Yeah, I will use the compatible of fu740 and modify this patch.

No, the JH7110 should not pretend to be a fu740, but if you add

compatible = "starfive,jh7110-ccache", "sifive,ccache0";

then this driver should still match "sifive,ccache0" without adding the "starfive,jh7110-ccache" entry.

From: Emil Renner Berthing <[email protected]>

This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller.

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---

 arch/riscv/Kconfig.socs            | 1 +
 drivers/soc/Makefile               | 2 +-
 drivers/soc/sifive/Kconfig         | 2 +-
 drivers/soc/sifive/sifive_ccache.c | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

arch/riscv/Kconfig.socs +1 -0

index 69774bb362d6..5a40e05f8cab 100644
@@ -22,6 +22,7 @@ config SOC_STARFIVE
        bool "StarFive SoCs"
        select PINCTRL
        select RESET_CONTROLLER
+       select SIFIVE_CCACHE
        select SIFIVE_PLIC
        help
          This enables support for StarFive SoC platform hardware.

drivers/soc/Makefile +1 -1

index 69ba6508cf2c..534669840858 100644
@@ -26,7 +26,7 @@ obj-y                         += qcom/
 obj-y                          += renesas/
 obj-y                          += rockchip/
 obj-$(CONFIG_SOC_SAMSUNG)      += samsung/
-obj-$(CONFIG_SOC_SIFIVE)       += sifive/
+obj-y                          += sifive/
 obj-y                          += sunxi/
 obj-$(CONFIG_ARCH_TEGRA)       += tegra/
 obj-y                          += ti/

drivers/soc/sifive/Kconfig +1 -1

index ed4c571f8771..e86870be34c9 100644
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
 
 config SIFIVE_CCACHE
        bool "Sifive Composable Cache controller"

drivers/soc/sifive/sifive_ccache.c +1 -1

index 1c171150e878..9489d1a90fbc 100644
@@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = {
        { .compatible = "sifive,fu540-c000-ccache" },
        { .compatible = "sifive,fu740-c000-ccache" },
        { .compatible = "sifive,ccache0" },
+       { .compatible = "starfive,jh7110-ccache" },
        { /* end of table */ }
 };
 
--

2.38.1

Quoted 6 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller.

Quoted 3 lines

Signed-off-by Emil Renner Berthing <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---

I'm fine with this, but it would be great if you could add the jh7100 support at the same time like the original patch did.

From: Emil Renner Berthing <[email protected]>

Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd.

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +0 -0

new file mode 100644
index 000000000000..c22e8f1d2640

Quoted 15 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd.

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

arch/riscv/boot/dts/starfive/jh7110.dtsi line 4

Quoted 10 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +4 -0

new file mode 100644
index 000000000000..c22e8f1d2640
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>

@Emil, I feel like I have to ask given the 2022 date, but should this stuff be attributed to your canonical address or is this fine?

Other than that, a cursory check /looks/ fine, other than the:

arch/riscv/boot/dts/starfive/jh7110.dtsi line 202

Quoted 6 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +6 -0

+       gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };

If you remove the clock-frequency = <0> bit, dtb validation will force people to set the value in jh7110-board.dts which I'd prefer to rely on than a comment.

Glad to see you sorted out the clock/reset stuff too!

Thanks,
Conor.

arch/riscv/boot/dts/starfive/jh7110.dtsi line 4

Quoted 10 lines · Hal Feng

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +4 -0

new file mode 100644
index 000000000000..c22e8f1d2640
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>

@Emil, I feel like I have to ask given the 2022 date, but should this stuff be attributed to your canonical address or is this fine?

Other than that, a cursory check /looks/ fine, other than the:

arch/riscv/boot/dts/starfive/jh7110.dtsi line 202

Quoted 6 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +6 -0

+       gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };

If you remove the clock-frequency = <0> bit, dtb validation will force people to set the value in jh7110-board.dts which I'd prefer to rely on than a comment.

From: Emil Renner Berthing <[email protected]>

Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd.

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +250 -0

new file mode 100644
index 000000000000..c22e8f1d2640
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive-jh7110.h>
+#include <dt-bindings/reset/starfive-jh7110.h>
+
+/ {
+       compatible = "starfive,jh7110";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               S76_0: cpu@0 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <0>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <8192>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <16384>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imac";
+                       tlb-split;
+                       status = "disabled";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_1: cpu@1 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <1>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc";
+                       tlb-split;
+
+                       cpu1_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_2: cpu@2 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <2>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc";
+                       tlb-split;
+
+                       cpu2_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_3: cpu@3 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <3>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc";
+                       tlb-split;
+
+                       cpu3_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               U74_4: cpu@4 {
+                       compatible = "sifive,u74-mc", "riscv";
+                       reg = <4>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <64>;
+                       d-cache-size = <32768>;
+                       d-tlb-sets = <1>;
+                       d-tlb-size = <40>;
+                       device_type = "cpu";
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <64>;
+                       i-cache-size = <32768>;
+                       i-tlb-sets = <1>;
+                       i-tlb-size = <40>;
+                       mmu-type = "riscv,sv39";
+                       next-level-cache = <&ccache>;
+                       riscv,isa = "rv64imafdc";
+                       tlb-split;
+
+                       cpu4_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&S76_0>;
+                               };
+
+                               core1 {
+                                       cpu = <&U74_1>;
+                               };
+
+                               core2 {
+                                       cpu = <&U74_2>;
+                               };
+
+                               core3 {
+                                       cpu = <&U74_3>;
+                               };
+
+                               core4 {
+                                       cpu = <&U74_4>;
+                               };
+                       };
+               };
+       };
+
+       osc: osc {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       clk_rtc: clk_rtc {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac0_rmii_refin: gmac0_rmii_refin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac1_rmii_refin: gmac1_rmii_refin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2stx_bclk_ext: i2stx_bclk_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2stx_lrck_ext: i2stx_lrck_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2srx_bclk_ext: i2srx_bclk_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       i2srx_lrck_ext: i2srx_lrck_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       tdm_ext: tdm_ext {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +177 -1

+               compatible = "simple-bus";
+               interrupt-parent = <&plic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clint: clint@2000000 {
+                       compatible = "starfive,jh7110-clint", "sifive,clint0";
+                       reg = <0x0 0x2000000 0x0 0x10000>;
+                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+                                             <&cpu1_intc 3>, <&cpu1_intc 7>,
+                                             <&cpu2_intc 3>, <&cpu2_intc 7>,
+                                             <&cpu3_intc 3>, <&cpu3_intc 7>,
+                                             <&cpu4_intc 3>, <&cpu4_intc 7>;
+               };
+
+               plic: plic@c000000 {
+                       compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+                       reg = <0x0 0xc000000 0x0 0x4000000>;
+                       interrupts-extended = <&cpu0_intc 11>,
+                                             <&cpu1_intc 11>, <&cpu1_intc 9>,
+                                             <&cpu2_intc 11>, <&cpu2_intc 9>,
+                                             <&cpu3_intc 11>, <&cpu3_intc 9>,
+                                             <&cpu4_intc 11>, <&cpu4_intc 9>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       #address-cells = <0>;
+                       riscv,ndev = <136>;
+               };
+
+               ccache: cache-controller@2010000 {
+                       compatible = "starfive,jh7110-ccache", "cache";
+                       reg = <0x0 0x2010000 0x0 0x4000>;
+                       interrupts = <1>, <3>, <4>, <2>;
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-sets = <2048>;
+                       cache-size = <2097152>;
+                       cache-unified;
+               };
+
+               syscrg: clock-controller@13020000 {
+                       compatible = "starfive,jh7110-syscrg";
+                       reg = <0x0 0x13020000 0x0 0x10000>;
+                       clocks = <&osc>, <&gmac1_rmii_refin>,
+                                <&gmac1_rgmii_rxin>,
+                                <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                                <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                                <&tdm_ext>, <&mclk_ext>;
+                       clock-names = "osc", "gmac1_rmii_refin",
+                                     "gmac1_rgmii_rxin",
+                                     "i2stx_bclk_ext", "i2stx_lrck_ext",
+                                     "i2srx_bclk_ext", "i2srx_lrck_ext",
+                                     "tdm_ext", "mclk_ext";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               aoncrg: clock-controller@17000000 {
+                       compatible = "starfive,jh7110-aoncrg";
+                       reg = <0x0 0x17000000 0x0 0x10000>;
+                       clocks = <&osc>, <&clk_rtc>,
+                                <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+                                <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+                                <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>,
+                                <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+                       clock-names = "osc", "clk_rtc", "gmac0_rmii_refin",
+                                     "gmac0_rgmii_rxin", "stg_axiahb",
+                                     "apb_bus_func", "gmac0_gtxclk";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               gpio: gpio@13040000 {
+                       compatible = "starfive,jh7110-sys-pinctrl";
+                       reg = <0x0 0x13040000 0x0 0x10000>;
+                       reg-names = "control";
+                       clocks = <&syscrg JH7110_SYSCLK_IOMUX>;
+                       resets = <&syscrg JH7110_SYSRST_IOMUX>;
+                       interrupts = <86>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               gpioa: gpio@17020000 {
+                       compatible = "starfive,jh7110-aon-pinctrl";
+                       reg = <0x0 0x17020000 0x0 0x10000>;
+                       reg-names = "control";
+                       resets = <&aoncrg JH7110_AONRST_AON_IOMUX>;
+                       interrupts = <85>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
+               uart0: serial@10000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10000000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART0_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+                       interrupts = <32>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart1: serial@10010000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART1_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+                       interrupts = <33>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart2: serial@10020000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x10020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART2_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+                       interrupts = <34>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart3: serial@12000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12000000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART3_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+                       interrupts = <45>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart4: serial@12010000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12010000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART4_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+                       interrupts = <46>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+
+               uart5: serial@12020000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x0 0x12020000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+                                <&syscrg JH7110_SYSCLK_UART5_APB>;
+                       clock-names = "baudclk", "apb_pclk";
+                       resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+                       interrupts = <47>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+       };
+};
--

2.38.1

Quoted 28 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd.

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +6 -0

new file mode 100644
index 000000000000..c22e8f1d2640
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+

arch/riscv/boot/dts/starfive/jh7110.dtsi

Quoted 2 lines

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +2 -0

+
+       soc {

Please sort these nodes after their address like the jh7100.dtsi. That is sort the nodes after @<number>.

From: Emil Renner Berthing <[email protected]>

Add a minimal device tree for StarFive JH7110 VisionFive2 board.

Support booting and basic clock/reset/pinctrl/uart drivers.

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/boot/dts/starfive/Makefile         |   1 +
 .../jh7110-starfive-visionfive-v2.dts         | 116 ++++++++++++++++++
 2 files changed, 117 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts

arch/riscv/boot/dts/starfive/Makefile +1 -0

index 0ea1bc15ab30..e1237dbc6aac 100644
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +4 -0

new file mode 100644
index 000000000000..c8946cf3a268
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +70 -0

+       };
+
+       cpus {
+               timebase-frequency = <4000000>;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0x1 0x0>;
+       };
+
+       gpio-restart {
+               compatible = "gpio-restart";
+               gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+               priority = <224>;
+       };
+};
+
+&osc {
+       clock-frequency = <24000000>;
+};
+
+&clk_rtc {
+       clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&tdm_ext {
+       clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&gpio {
+       uart0_pins: uart0-0 {
+               tx-pins {
+                       pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +13 -1

+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-enable;
+                       slew-rate = <0>;
+               };
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};
--

2.38.1

Quoted 4 lines · Hal Feng

From: Emil Renner Berthing <[email protected]>

Add a minimal device tree for StarFive JH7110 VisionFive2 board.

Missing space between VisionFive and 2.

Quoted 38 lines

Support booting and basic clock/reset/pinctrl/uart drivers.

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/boot/dts/starfive/Makefile         |   1 +
 .../jh7110-starfive-visionfive-v2.dts         | 116 ++++++++++++++++++
 2 files changed, 117 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts

arch/riscv/boot/dts/starfive/Makefile +1 -0

index 0ea1bc15ab30..e1237dbc6aac 100644
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +10 -0

new file mode 100644
index 000000000000..c8946cf3a268
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts line 14

Quoted 4 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +4 -0

+
+/ {
+       model = "StarFive VisionFive V2";
+       compatible = "starfive,visionfive-v2", "starfive,jh7110";

Again, please consult your colleagues if you're calling the board "VisionFive 2" or "VisionFive V2" and name the file, model and board accordingly.

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts line 22

Quoted 8 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +7 -0

+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               linux,initrd-start = <0x46100000>;
+               linux,initrd-end = <0x4c000000>;

These two lines don't belong here. They're added by the bootloader dynamically.

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts line 23

Quoted 2 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +1 -0

+               stdout-path = "serial0:115200";

You're missing a n8.

Quoted 71 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +70 -0

+       };
+
+       cpus {
+               timebase-frequency = <4000000>;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0x1 0x0>;
+       };
+
+       gpio-restart {
+               compatible = "gpio-restart";
+               gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+               priority = <224>;
+       };
+};
+
+&osc {
+       clock-frequency = <24000000>;
+};
+
+&clk_rtc {
+       clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&tdm_ext {
+       clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&gpio {
+       uart0_pins: uart0-0 {
+               tx-pins {
+                       pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts line 103

Quoted 10 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +10 -0

+                       bias-disable;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               rx-pins {
+                       pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
+                       bias-pull-up;

There are external pull-ups, so maybe change this line to

bias-disable; /* external pull-up */

Quoted 14 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts new file +13 -0

+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-enable;
+                       slew-rate = <0>;
+               };
+       };
+};
+
+&uart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/riscv/configs/defconfig +1 -0

index 05fd5fcf24f9..a23d022974ad 100644
@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y

Signature · 7 lines

2.38.1


_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/riscv/configs/defconfig +0 -0

index 05fd5fcf24f9..a23d022974ad 100644

Quoted 9 lines · On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

arch/riscv/configs/defconfig CONFIG_MICROSEMI_PHY=y · line 128

Quoted 12 lines

arch/riscv/configs/defconfig +1 -0

index 05fd5fcf24f9..a23d022974ad 100644
@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y

Acked-by Palmer Dabbelt <[email protected]>

Quoted 10 lines · Palmer Dabbelt

Quoted 9 lines · On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

Quoted 14 lines

arch/riscv/configs/defconfig CONFIG_MICROSEMI_PHY=y · line 128

Quoted 12 lines

arch/riscv/configs/defconfig +1 -0

index 05fd5fcf24f9..a23d022974ad 100644
@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y

Acked-by Palmer Dabbelt <[email protected]>

Hey Palmer, could you take this as v6.2 material instead of Acking it please? It applies to the jh7100 stuff that's already in-tree.

Quoted 25 lines · Conor Dooley

Quoted 23 lines · Palmer Dabbelt

Quoted 8 lines · On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Quoted 1 line

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

Review

Quoted 1 line

(quoted diff) +0 -0

b/arch/riscv/configs/defconfig

arch/riscv/configs/defconfig CONFIG_MICROSEMI_PHY=y · line 128

Quoted 11 lines

index 05fd5fcf24f9..a23d022974ad 100644

arch/riscv/configs/defconfig +1 -0

@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y

Acked-by Palmer Dabbelt <[email protected]>

Quoted 2 lines

Hey Palmer, could you take this as v6.2 material instead of Acking it please? It applies to the jh7100 stuff that's already in-tree.

Ya, no problem. Just this patch, or the whole series?

Quoted 26 lines · Palmer Dabbelt

Quoted 25 lines · Conor Dooley

Quoted 23 lines · Palmer Dabbelt

Quoted 8 lines · On Thu, 17 Nov 2022 17:17:14 PST (-0800), [email protected] wrote:

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Quoted 1 line

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

Review

Quoted 1 line

(quoted diff) +0 -0

b/arch/riscv/configs/defconfig

arch/riscv/configs/defconfig CONFIG_MICROSEMI_PHY=y · line 128

Quoted 11 lines

index 05fd5fcf24f9..a23d022974ad 100644

arch/riscv/configs/defconfig +1 -0

@@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM=y

Acked-by Palmer Dabbelt <[email protected]>

Quoted 4 lines

Quoted 2 lines

Hey Palmer, could you take this as v6.2 material instead of Acking it please? It applies to the jh7100 stuff that's already in-tree.

Ya, no problem. Just this patch, or the whole series?

Just this one defconfig patch please, the rest is not ready. Sorry that that was not clear,

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Quoted 4 lines · Hal Feng

Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports.

Applied, thanks!

[8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW

      https://git.kernel.org/palmer/c/6925ba3d9b8c

The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1] is split into 3 patch series. They respectively add basic clock&reset, pinctrl and device tree support for StarFive JH7110 SoC. These patch series are independent, but the Visionfive2 board can boot up successfully

only if all these patches series applied. This one adds basic device

Hello:

This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:

Quoted 10 lines · On Fri, 18 Nov 2022 09:17:06 +0800 you wrote:

The original patch series "Basic StarFive JH7110 RISC-V SoC support" [1] is split into 3 patch series. They respectively add basic clock&reset, pinctrl and device tree support for StarFive JH7110 SoC. These patch series are independent, but the Visionfive2 board can boot up successfully only if all these patches series applied. This one adds basic device tree support. This patch series is pulled out from the patch 1~6 and patch 27~30 of v1 [1]. You can simply get or review the patches at the link [2].

[...]

Here is the summary with links:
- [v2,1/8] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive2 board (no matching commit)
- [v2,2/8] dt-bindings: timer: Add StarFive JH7110 clint
(no matching commit)
- [v2,3/8] dt-bindings: interrupt-controller: Add StarFive JH7110 plic (no matching commit)
- [v2,4/8] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC (no matching commit)
- [v2,5/8] soc: sifive: ccache: Add StarFive JH7110 support
(no matching commit)
- [v2,6/8] riscv: dts: starfive: Add initial StarFive JH7110 device tree (no matching commit)
- [v2,7/8] riscv: dts: starfive: Add StarFive JH7110 VisionFive2 board device tree (no matching commit)
- [v2,8/8] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW

    https://git.kernel.org/riscv/c/6925ba3d9b8c

You are awesome, thank you!