allwinner: a523: Enable I2S and SPDIF TX

The TX side of the SPDIF block on the A523 is almost the same the previous generations, the only difference being that it has separate module clock inputs for the TX and RX side.

Since this driver currently only supports TX, add support for a different clock name so that TX and RX clocks can be separated if RX support is ever added. Then add support for the A523.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 sound/soc/sunxi/sun4i-spdif.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)

sound/soc/sunxi/sun4i-spdif.c +2 -0

index 34e5bd94e9af..6a58dc4311de 100644
@@ -177,6 +177,7 @@ struct sun4i_spdif_quirks {
 	bool has_reset;
 	unsigned int val_fctl_ftx;
 	unsigned int mclk_multiplier;
+	const char *tx_clk_name;
 };
 
 struct sun4i_spdif_dev {

@@ -323,6 +324,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
 	}
 	mclk *= host->quirks->mclk_multiplier;
 
+	dev_info(&pdev->dev, "Setting SPDIF clock rate to %u\n", mclk);
 	ret = clk_set_rate(host->spdif_clk, mclk);
 	if (ret < 0) {
 		dev_err(&pdev->dev,

sound/soc/sunxi/sun4i-spdif.c +17 -0

 };
 
 static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {

@@ -572,6 +573,14 @@ static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
 	.mclk_multiplier = 1,
 };
 
+static const struct sun4i_spdif_quirks sun55i_a523_spdif_quirks = {
+	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
+	.has_reset      = true,
+	.mclk_multiplier = 1,
+	.tx_clk_name	= "tx",
+};
+
 static const struct of_device_id sun4i_spdif_of_match[] = {
 	{
 		.compatible = "allwinner,sun4i-a10-spdif",

@@ -594,6 +603,15 @@ static const struct of_device_id sun4i_spdif_of_match[] = {
 		/* Essentially the same as the H6, but without RX */
 		.data = &sun50i_h6_spdif_quirks,
 	},
+	{
+		.compatible = "allwinner,sun55i-a523-spdif",
+		/*
+		 * Almost the same as H6, but has split the TX and RX clocks,
+		 * has a separate reset bit for the RX side, and has some
+		 * expanded features for the RX side.
+		 */
+		.data = &sun55i_a523_spdif_quirks,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);

sound/soc/sunxi/sun4i-spdif.c +5 -2

 	dev_dbg(&pdev->dev, "Entered %s\n", __func__);
 

@@ -671,9 +690,12 @@ static int sun4i_spdif_probe(struct platform_device *pdev)
 		return PTR_ERR(host->apb_clk);
 	}
 
-	host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
+	if (quirks->tx_clk_name)
+		tx_clk_name = quirks->tx_clk_name;
+	host->spdif_clk = devm_clk_get(&pdev->dev, tx_clk_name);
 	if (IS_ERR(host->spdif_clk)) {
-		dev_err(&pdev->dev, "failed to get a spdif clock.\n");
+		dev_err(&pdev->dev, "failed to get the \"%s\" clock.\n",
+			tx_clk_name);
 		return PTR_ERR(host->spdif_clk);
 	}
 

Hi,

Dne ponedeljek, 20. oktober 2025 ob 19:10:50 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):

Quoted 29 lines

The TX side of the SPDIF block on the A523 is almost the same the previous generations, the only difference being that it has separate module clock inputs for the TX and RX side.

Since this driver currently only supports TX, add support for a different clock name so that TX and RX clocks can be separated if RX support is ever added. Then add support for the A523.

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 sound/soc/sunxi/sun4i-spdif.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)

sound/soc/sunxi/sun4i-spdif.c +1 -0

index 34e5bd94e9af..6a58dc4311de 100644
@@ -177,6 +177,7 @@ struct sun4i_spdif_quirks {
      bool has_reset;
      unsigned int val_fctl_ftx;
      unsigned int mclk_multiplier;
+     const char *tx_clk_name;
 };
 
 struct sun4i_spdif_dev {

@@ -323,6 +324,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
      }
      mclk *= host->quirks->mclk_multiplier;
 

sound/soc/sunxi/sun4i-spdif.c static struct snd_soc_dai_driver sun4i_spdif_dai = { · line 545

Quoted 9 lines

sound/soc/sunxi/sun4i-spdif.c +1 -1

+     dev_info(&pdev->dev, "Setting SPDIF clock rate to %u\n", mclk);
      ret = clk_set_rate(host->spdif_clk, mclk);
      if (ret < 0) {
              dev_err(&pdev->dev,

@@ -542,7 +544,6 @@ static struct snd_soc_dai_driver sun4i_spdif_dai = {
              .formats = SUN4I_FORMATS,
      },
      .ops = &sun4i_spdif_dai_ops,
-     .name = "spdif",

Why this change?

Quoted 33 lines

sound/soc/sunxi/sun4i-spdif.c +17 -0

 };
 
 static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {

@@ -572,6 +573,14 @@ static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
      .mclk_multiplier = 1,
 };
 
+static const struct sun4i_spdif_quirks sun55i_a523_spdif_quirks = {
+     .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
+     .val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
+     .has_reset      = true,
+     .mclk_multiplier = 1,
+     .tx_clk_name    = "tx",
+};
+
 static const struct of_device_id sun4i_spdif_of_match[] = {
      {
              .compatible = "allwinner,sun4i-a10-spdif",

@@ -594,6 +603,15 @@ static const struct of_device_id sun4i_spdif_of_match[] = {
              /* Essentially the same as the H6, but without RX */
              .data = &sun50i_h6_spdif_quirks,
      },
+     {
+             .compatible = "allwinner,sun55i-a523-spdif",
+             /*
+              * Almost the same as H6, but has split the TX and RX clocks,
+              * has a separate reset bit for the RX side, and has some
+              * expanded features for the RX side.
+              */
+             .data = &sun55i_a523_spdif_quirks,
+     },
      { /* sentinel */ }
 };

sound/soc/sunxi/sun4i-spdif.c static int sun4i_spdif_probe(struct platform_device *pdev) · line 656

Quoted 6 lines

sound/soc/sunxi/sun4i-spdif.c +1 -0

 MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);

@@ -635,6 +653,7 @@ static int sun4i_spdif_probe(struct platform_device *pdev)
      const struct sun4i_spdif_quirks *quirks;
      int ret;
      void __iomem *base;
+     const char *tx_clk_name = "spdif";

Reverse tree?

Otherwise it looks good.

Best regards,
Jernej

Quoted 19 lines

sound/soc/sunxi/sun4i-spdif.c +5 -2

      dev_dbg(&pdev->dev, "Entered %s\n", __func__);
 

@@ -671,9 +690,12 @@ static int sun4i_spdif_probe(struct platform_device *pdev)
              return PTR_ERR(host->apb_clk);
      }
 
-     host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
+     if (quirks->tx_clk_name)
+             tx_clk_name = quirks->tx_clk_name;
+     host->spdif_clk = devm_clk_get(&pdev->dev, tx_clk_name);
      if (IS_ERR(host->spdif_clk)) {
-             dev_err(&pdev->dev, "failed to get a spdif clock.\n");
+             dev_err(&pdev->dev, "failed to get the \"%s\" clock.\n",
+                     tx_clk_name);
              return PTR_ERR(host->spdif_clk);
      }
 

The "bus-r-dma" clock in the A523's PRCM clock controller is also referred to as "DMA_CLKEN_SW" or "DMA ADB400 gating". It is unclear how this ties into the DMA controller MBUS clock gate; however if the clock is not enabled, the DMA controller in the MCU block will fail to access DRAM, even failing to retrieve the DMA descriptors.

Mark this clock as critical. This sort of mirrors what is done for the main DMA controller's MBUS clock, which has a separate toggle that is currently left out of the main clock controller driver.

Fixes 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +1 -1

index 70ce0ca0cb7d..fdcdcccd0939 100644
@@ -121,7 +121,7 @@ static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx",
 			 &r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
 
 static SUNXI_CCU_GATE_HW(bus_r_dma_clk, "bus-r-dma",
-			 &r_apb0_clk.common.hw, 0x1dc, BIT(0), 0);
+			 &r_apb0_clk.common.hw, 0x1dc, BIT(0), CLK_IS_CRITICAL);
 static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc",
 			 &r_apb0_clk.common.hw, 0x20c, BIT(0), 0);
 static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg",

While the user manual states that the PLL's rate should be between 180 MHz and 3 GHz in the register defninition section, it also says the actual operating frequency is 22.5792*4 MHz in the PLL features table.

22.5792*4 MHz is one of the actual clock rates that we want and is is available in the SDM table. Lower the minimum clock rate to 90 MHz so that both rates in the SDM table can be used.

Fixes 7cae1e2b5544 ("clk: sunxi-ng: Add support for the A523/T527 CCU PLLs")

Signed-off-by Chen-Yu Tsai <[email protected]>

---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/sunxi-ng/ccu-sun55i-a523.c +1 -1

index acb532f8361b..20dad06b37ca 100644
@@ -300,7 +300,7 @@ static struct ccu_nm pll_audio0_4x_clk = {
 	.m		= _SUNXI_CCU_DIV(16, 6),
 	.sdm		= _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
 					 0x178, BIT(31)),
-	.min_rate	= 180000000U,
+	.min_rate	= 90000000U,
 	.max_rate	= 3000000000U,
 	.common		= {
 		.reg		= 0x078,

Dne ponedeljek, 20. oktober 2025 ob 19:10:52 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):

Quoted 7 lines

While the user manual states that the PLL's rate should be between 180 MHz and 3 GHz in the register defninition section, it also says the actual operating frequency is 22.5792*4 MHz in the PLL features table.

22.5792*4 MHz is one of the actual clock rates that we want and is is available in the SDM table. Lower the minimum clock rate to 90 MHz so that both rates in the SDM table can be used.

So factor of 2 could be missed somewhere?

Quoted 3 lines

Fixes 7cae1e2b5544 ("clk: sunxi-ng: Add support for the A523/T527 CCU PLLs")

Signed-off-by Chen-Yu Tsai <[email protected]>

Reviewed-by Jernej Skrabec <[email protected]>

Best regards,
Jernej

Quoted 18 lines

---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/sunxi-ng/ccu-sun55i-a523.c +1 -1

index acb532f8361b..20dad06b37ca 100644
@@ -300,7 +300,7 @@ static struct ccu_nm pll_audio0_4x_clk = {
      .m              = _SUNXI_CCU_DIV(16, 6),
      .sdm            = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
                                       0x178, BIT(31)),
-     .min_rate       = 180000000U,
+     .min_rate       = 90000000U,
      .max_rate       = 3000000000U,
      .common         = {
              .reg            = 0x078,

Quoted 6 lines

Dne ponedeljek, 20. oktober 2025 ob 19:10:52 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):

Quoted 4 lines

While the user manual states that the PLL's rate should be between 180 MHz and 3 GHz in the register defninition section, it also says the actual operating frequency is 22.5792*4 MHz in the PLL features table.

Quoted 5 lines

Quoted 3 lines

22.5792*4 MHz is one of the actual clock rates that we want and is is available in the SDM table. Lower the minimum clock rate to 90 MHz so that both rates in the SDM table can be used.

So factor of 2 could be missed somewhere?

Not sure what you mean? This PLL only gives *4 and *1 outputs.

Quoted 32 lines

Quoted 4 lines

Fixes 7cae1e2b5544 ("clk: sunxi-ng: Add support for the A523/T527 CCU PLLs")

Signed-off-by Chen-Yu Tsai <[email protected]>

Reviewed-by Jernej Skrabec <[email protected]>

Best regards,
Jernej

Quoted 18 lines

---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/sunxi-ng/ccu-sun55i-a523.c +1 -1

index acb532f8361b..20dad06b37ca 100644
@@ -300,7 +300,7 @@ static struct ccu_nm pll_audio0_4x_clk = {
      .m              = _SUNXI_CCU_DIV(16, 6),
      .sdm            = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
                                       0x178, BIT(31)),
-     .min_rate       = 180000000U,
+     .min_rate       = 90000000U,
      .max_rate       = 3000000000U,
      .common         = {
              .reg            = 0x078,

From: Chen-Yu Tsai <[email protected]>

The A523 has two DMA controllers. Add device nodes for both. Also hook up DMA for existing devices.

Signed-off-by Chen-Yu Tsai <[email protected]>

The A523 has a SPDIF interface that is capable of both playback and capture.

Add a node for it.

Signed-off-by Chen-Yu Tsai <[email protected]>

The A523 family of SoCs have four I2S controllers capable of both playback and capture. The user manual also implies that I2S2 also outputs to the eDP interface controller.

Add device nodes for all of them.

Signed-off-by Chen-Yu Tsai <[email protected]>

The Radxa Cubie A5E exposes I2S2 through the PI pin group on the 40-pin GPIO header.

Add a pinmux setting for it so potential users can directly reference it.

Signed-off-by Chen-Yu Tsai <[email protected]>

This series enables the SPDIF and I2S hardware found on the Allwinner A523/A527/T527 family SoCs. These SoCs have one SPDIF interface and four I2S interfaces. All of them are capable of both playback and capture, however the SPDIF driver only supports playback.

The series is organized by subsystem, so each maintainer can find the patches they need to take.

[...]