Skip to contentSkip to conversation

arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

PATCH In review Shanker Donthineni 3 participants 6 messages Mar 5, 2018 – Mar 20, 2018

Subsystems (2)
arm64 KVM arm64
lore
Share & tools
lore

Shanker Donthineni

author
#0 lore raw

PATCH v2 1/1 arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700.

Signed-off-by Shanker Donthineni <[email protected]>

---
Chnages since v1:
- Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)

 arch/arm64/include/asm/cpucaps.h |  5 ++--
 arch/arm64/include/asm/kvm_asm.h |  2 --
 arch/arm64/kernel/bpi.S          |  8 ------
 arch/arm64/kernel/cpu_errata.c   | 55 ++++++++++++++--------------------------
 arch/arm64/kvm/hyp/entry.S       | 12 ---------
 arch/arm64/kvm/hyp/switch.c      | 10 --------
 6 files changed, 21 insertions(+), 71 deletions(-)
arch/arm64/include/asm/cpucaps.h +2 -3
index bb26382..324c85e 100644
@@ -43,9 +43,8 @@
 #define ARM64_SVE				22
 #define ARM64_UNMAP_KERNEL_AT_EL0		23
 #define ARM64_HARDEN_BRANCH_PREDICTOR		24
-#define ARM64_HARDEN_BP_POST_GUEST_EXIT		25
-#define ARM64_HAS_RAS_EXTN			26
+#define ARM64_HAS_RAS_EXTN			25
 
-#define ARM64_NCAPS				27
+#define ARM64_NCAPS				26
 
 #endif /* __ASM_CPUCAPS_H */
arch/arm64/include/asm/kvm_asm.h +0 -2
index 24961b7..ab4d0a9 100644
@@ -68,8 +68,6 @@
 
 extern u32 __init_stage2_translation(void);
 
-extern void __qcom_hyp_sanitize_btac_predictors(void);
-
 #endif
 
 #endif /* __ARM_KVM_ASM_H__ */
arch/arm64/kernel/bpi.S +0 -8
index e5de335..dc4eb15 100644
@@ -55,14 +55,6 @@ ENTRY(__bp_harden_hyp_vecs_start)
 	.endr
 ENTRY(__bp_harden_hyp_vecs_end)
 
-ENTRY(__qcom_hyp_sanitize_link_stack_start)
-	stp     x29, x30, [sp, #-16]!
-	.rept	16
-	bl	. + 4
-	.endr
-	ldp	x29, x30, [sp], #16
-ENTRY(__qcom_hyp_sanitize_link_stack_end)
-
 .macro smccc_workaround_1 inst
 	sub	sp, sp, #(8 * 4)
 	stp	x2, x3, [sp, #(8 * 0)]
arch/arm64/kernel/cpu_errata.c +19 -36

100 lines not on this page · raw message

arch/arm64/kvm/hyp/entry.S +0 -12
index fdd1068..56fc2bb 100644
@@ -213,15 +213,3 @@ alternative_endif
 
 	eret
 ENDPROC(__fpsimd_guest_restore)
-
-ENTRY(__qcom_hyp_sanitize_btac_predictors)
-	/**
-	 * Call SMC64 with Silicon provider serviceID 23<<8 (0xc2001700)
-	 * 0xC2000000-0xC200FFFF: assigned to SiP Service Calls
-	 * b15-b0: contains SiP functionID
-	 */
-	movz    x0, #0x1700
-	movk    x0, #0xc200, lsl #16
-	smc     #0
-	ret
-ENDPROC(__qcom_hyp_sanitize_btac_predictors)
arch/arm64/kvm/hyp/switch.c +0 -10
index 870f4b1..d4a336e 100644
@@ -403,16 +403,6 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 		/* 0 falls through to be handled out of EL2 */
 	}
 
-	if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) {
-		u32 midr = read_cpuid_id();
-
-		/* Apply BTAC predictors mitigation to all Falkor chips */
-		if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
-		    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
-			__qcom_hyp_sanitize_btac_predictors();
-		}
-	}
-
 	fp_enabled = __fpsimd_enabled();
 
 	__sysreg_save_guest_state(guest_ctxt);
Signature · 2 lines
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Reviewed-by on v2 1/1
#1 lore raw
Quoted 11 lines · Shanker Donthineni

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700.

Signed-off-by Shanker Donthineni <[email protected]>

---
Chnages since v1:
- Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)

Quoted 7 lines
 arch/arm64/include/asm/cpucaps.h |  5 ++--
 arch/arm64/include/asm/kvm_asm.h |  2 --
 arch/arm64/kernel/bpi.S          |  8 ------
 arch/arm64/kernel/cpu_errata.c   | 55 ++++++++++++++--------------------------
 arch/arm64/kvm/hyp/entry.S       | 12 ---------
 arch/arm64/kvm/hyp/switch.c      | 10 --------
 6 files changed, 21 insertions(+), 71 deletions(-)
Reviewed-by Marc Zyngier <[email protected]>

Will/Catalin, if you want to take it via the arm64 tree, that's fine by me.

Thanks,

	M.
Signature · 1 line
Jazz is not dead, it just smell funny.
#2 lore raw
Quoted 21 lines · Marc Zyngier
Quoted 11 lines · Shanker Donthineni

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700.

Signed-off-by Shanker Donthineni <[email protected]>

---
Chnages since v1:
- Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)

Quoted 7 lines
 arch/arm64/include/asm/cpucaps.h |  5 ++--
 arch/arm64/include/asm/kvm_asm.h |  2 --
 arch/arm64/kernel/bpi.S          |  8 ------
 arch/arm64/kernel/cpu_errata.c   | 55 ++++++++++++++--------------------------
 arch/arm64/kvm/hyp/entry.S       | 12 ---------
 arch/arm64/kvm/hyp/switch.c      | 10 --------
 6 files changed, 21 insertions(+), 71 deletions(-)
Quoted 4 lines
Reviewed-by Marc Zyngier <[email protected]>

Will/Catalin, if you want to take it via the arm64 tree, that's fine by me.

Please allow me to change my mind. This is going to conflict horribly with the VHE rework and the HYP randomization patches.

I'll take it via the KVM tree, which will make everyone's life a lot easier.

Thanks,

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Acked-by
#3 lore raw
Quoted 24 lines · Marc Zyngier
Quoted 23 lines · Marc Zyngier
Quoted 11 lines · Shanker Donthineni

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700.

Signed-off-by Shanker Donthineni <[email protected]>

---
Chnages since v1:
- Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)

Quoted 7 lines
 arch/arm64/include/asm/cpucaps.h |  5 ++--
 arch/arm64/include/asm/kvm_asm.h |  2 --
 arch/arm64/kernel/bpi.S          |  8 ------
 arch/arm64/kernel/cpu_errata.c   | 55 ++++++++++++++--------------------------
 arch/arm64/kvm/hyp/entry.S       | 12 ---------
 arch/arm64/kvm/hyp/switch.c      | 10 --------
 6 files changed, 21 insertions(+), 71 deletions(-)
Reviewed-by Marc Zyngier <[email protected]>
Quoted 7 lines
Quoted 2 lines

Will/Catalin, if you want to take it via the arm64 tree, that's fine by me.

Please allow me to change my mind. This is going to conflict horribly with the VHE rework and the HYP randomization patches.

I'll take it via the KVM tree, which will make everyone's life a lot easier.

Sure; if you need it:

Acked-by Will Deacon <[email protected]>

You'll probably want to comment out the ARM64_HARDEN_BP_POST_GUEST_EXIT capability for now to avoid silly conflicts in -next. I can remove and renumber at -rc1.

Will

#4 lore raw
In reply to Shanker Donthineni

Hi SHanker,

Quoted 10 lines · Shanker Donthineni

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700.

Signed-off-by Shanker Donthineni <[email protected]>

---
Chnages since v1:
- Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)

Quoted 7 lines
 arch/arm64/include/asm/cpucaps.h |  5 ++--
 arch/arm64/include/asm/kvm_asm.h |  2 --
 arch/arm64/kernel/bpi.S          |  8 ------
 arch/arm64/kernel/cpu_errata.c   | 55 ++++++++++++++--------------------------
 arch/arm64/kvm/hyp/entry.S       | 12 ---------
 arch/arm64/kvm/hyp/switch.c      | 10 --------
 6 files changed, 21 insertions(+), 71 deletions(-)

Could you reply to my outstanding question on the last version of this patch please?

http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/564194.html

Will

author
#5 lore raw

Hi Will,

Quoted 21 lines · Will Deacon

Hi SHanker,

Quoted 10 lines · Shanker Donthineni

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700.

Signed-off-by Shanker Donthineni <[email protected]>

---
Chnages since v1:
- Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)

Quoted 7 lines
 arch/arm64/include/asm/cpucaps.h |  5 ++--
 arch/arm64/include/asm/kvm_asm.h |  2 --
 arch/arm64/kernel/bpi.S          |  8 ------
 arch/arm64/kernel/cpu_errata.c   | 55 ++++++++++++++--------------------------
 arch/arm64/kvm/hyp/entry.S       | 12 ---------
 arch/arm64/kvm/hyp/switch.c      | 10 --------
 6 files changed, 21 insertions(+), 71 deletions(-)
Quoted 3 lines

Could you reply to my outstanding question on the last version of this patch please?

I replied to your comments. This patch contents have been discussed with QCOM CPU architecture and design team. Their recommendation was to keep two variants of variant2 mitigation in order to take advantage of Falkor hardware and avoid the unnecessary overhead by calling SMMCC always.

Quoted 9 lines

http://lists.infradead.org/pipermail/linux-arm-kernel/2018-March/564194.html

Will

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 3 lines
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.