Add quirk to support address bus size limitation
cover Add quirk to support address bus size limitation
From: Adrian Ng Ho Yin <[email protected]>
This patch set adds support for the address bus size limitation by allocating buffers with in a 32 bit address range.
-Add device tree binding to enable a quirk to support a limited address bus size.
-Update ITS node for Agilex5 with dma_32bit_quirk.
-Add implementation to configure gfp flags to allocate buffers within 32 bit addressable range when quirk is set.
Adrian Ng Ho Yin (3):
dt-bindings: interrupt-controller: arm,gic-v3-its: Add quirk to
support 32 bit addressable range
arm64: dts: socfpga: agilex5: Add dma_32bit_quirk in GIC ITS node
irqchip: gic-v3-its: add support for 32bit addressing
.../interrupt-controller/arm,gic-v3.yaml | 5 ++++ .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 + drivers/irqchip/irq-gic-v3-its.c | 23 +++++++++++++++---- 3 files changed, 25 insertions(+), 4 deletions(-)
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2.49.GIT
PATCH 1/3 dt-bindings: interrupt-controller: arm,gic-v3-its: Add quirk to support 32 bit addressable range
From: Adrian Ng Ho Yin <[email protected]>
Add quirk to configure gfp flags to only allocate buffers within 32 bit addressable range to support devices that cannot support the full 64 bit address range.
--- .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +5 -0
@@ -225,6 +225,11 @@ patternProperties: minItems: 2 maxItems: 2 + dma-32bit-quirk: + type: boolean + description: + Set when supported addressable range is only 32 bits. + required: - compatible - msi-controller
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2.49.GIT
PATCH 2/3 arm64: dts: socfpga: agilex5: Add dma_32bit_quirk in GIC ITS node
In reply to [email protected]From: Adrian Ng Ho Yin <[email protected]>
Add dma_32bit_quirk in GIC ITS node in Agilex5 dtsi to address hardware addressing limitation.
--- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +1 -0
@@ -82,6 +82,7 @@ its: msi-controller@1d040000 { compatible = "arm,gic-v3-its"; reg = <0x0 0x1d040000 0x0 0x20000>; msi-controller; + dma-32bit-quirk; #msi-cells = <1>; }; };
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2.49.GIT
PATCH 3/3 irqchip: gic-v3-its: add support for 32bit addressing
In reply to [email protected]From: Adrian Ng Ho Yin <[email protected]>
Add quirk to support limited address bus size by allocating buffers within a 32bit address range.
--- drivers/irqchip/irq-gic-v3-its.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-)
drivers/irqchip/irq-gic-v3-its.c +19 -4
@@ -54,6 +54,7 @@#define RD_LOCAL_MEMRESERVE_DONE BIT(2)static u32 lpi_id_bits; +static bool dma_32bit_flag;/* * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
@@ -2385,6 +2386,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,u32 alloc_pages, psz;struct page *page;void *base; +gfp_t flags =GFP_KERNEL | __GFP_ZERO; psz = baser->psz; alloc_pages = (PAGE_ORDER_TO_SIZE (order) / psz);
@@ -2396,7 +2398,10 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, order =get_order (GITS_BASER_PAGES_MAX * psz); } - page =its_alloc_pages_node (its->numa_node,GFP_KERNEL | __GFP_ZERO, order); +if (dma_32bit_flag) + flags |=GFP_DMA32 ; + + page =alloc_pages_node (its->numa_node, flags, order);if (!page)return -ENOMEM ;
@@ -3367,6 +3372,7 @@ static bool its_alloc_table_entry(struct its_node *its,struct page *page;u32 esz, idx;__le64 *table; +gfp_t flags =GFP_KERNEL | __GFP_ZERO;/* Don't allow device id that exceeds single, flat table limit */ esz =GITS_BASER_ENTRY_SIZE (baser->val);
@@ -3382,7 +3388,10 @@ static bool its_alloc_table_entry(struct its_node *its,/* Allocate memory for 2nd level table */ if (!table[idx]) { - page =its_alloc_pages_node (its->numa_node,GFP_KERNEL | __GFP_ZERO, +if (dma_32bit_flag) + flags |=GFP_DMA32 ; + + page =alloc_pages_node (its->numa_node, flags,get_order (baser->psz));if (!page)return false;
@@ -5227,9 +5236,13 @@ static int __init its_probe_one(struct its_node *its)struct page *page;u32 ctlr;int err; +gfp_t flags =GFP_KERNEL | __GFP_ZERO;its_enable_quirks (its); +if (dma_32bit_flag) + flags |=GFP_DMA32 ; +if (is_v4 (its)) {if (!(its->typer &GITS_TYPER_VMOVP )) { err =its_compute_its_list_map (its);
@@ -5260,8 +5273,7 @@ static int __init its_probe_one(struct its_node *its) } } - page =its_alloc_pages_node (its->numa_node, -GFP_KERNEL | __GFP_ZERO, + page =alloc_pages_node (its->numa_node, flags,get_order (ITS_CMD_QUEUE_SZ ));if (!page) { err = -ENOMEM ;
@@ -5577,6 +5589,8 @@ static int __init its_of_probe(struct device_node *node)continue ; } +if (of_property_read_bool (np,"dma-32bit-quirk" )) + dma_32bit_flag = true; its =its_node_init (&res, &np->fwnode,of_node_to_nid (np));if (!its)
@@ -5811,6 +5825,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,bool has_v4 = false;bool has_v4_1 = false;int err; + dma_32bit_flag = false; itt_pool =gen_pool_create (get_order (ITS_ITT_ALIGN ),-1 );if (!itt_pool)
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2.49.GIT
Marc Zyngier
maintainerQuoted 11 lines · On Fri, 16 May 2025 05:13:31 +0100, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
This patch set adds support for the address bus size limitation by allocating buffers with in a 32 bit address range.
-Add device tree binding to enable a quirk to support a limited address bus size.
(quoted diff) +0
-2-Update ITS node for Agilex5 with dma_32bit_quirk. -Add implementation to configure gfp flags to allocate buffers within32 bit addressable range when quirk is set.
No. Please join the pack of other totally broken integrations and reuse the *existing* infrastructure. You'll be in good company.
M.
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Without deviation from the norm, progress is not possible.