OpenRISC SMP Support
Stafford Horne
maintainerv2 cover OpenRISC SMP Support
Hello Again,
This series adds SMP support for OpenRISC. The OpenRISC multicore platform and SMP linux support is based on the work that Stefan Kristiansson did around 2012 implemented in Verilog and run on FPGAs. I have been working to upstream this work. I have additionally tested this on QEMU, which I patched for OpenRISC multicore support, as well as FPGA.
I have documented the architecture in the OpenRISC 1.2 specification proposal available here:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
The QEMU patches are still under review but are available here for testers and anyone interested:
https://github.com/stffrdhrn/qemu.git openrisc-smp-v1
This series contains a bit of a mix of patches to get everything working.
o First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get the architecture ready for SMP.
o The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks" add the SMP locking infrastructure as needed. Using the qspinlocks and qrwlocks as suggested by Peter Z while reviewing the original spinlocks implementation.
o The "support for ompic" adds a new irqchip device which is used for IPI communication to support SMP. (Perhaps this patch should go via another route but included here for completeness - confirmed this is ok)
o The "initial SMP support" adds smp.c and makes changes to all of the necessary data-structures to be per-cpu.
o The remaining patches are bug fixes and debug helpers which I wanted to keep separate from the "initial SMP support" in order to allow them to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic
--
Changes since v1
- refactor of timer headers to not require extern openrisc_timer_init() in smp.c
- check for power management unit when sleeping on secondary cpu wait
- fixed cpuinfo to print online CPUs only
- cleanups for the ompic suggested by Marc Zyngier and Mark Rutland
Quoted 9 lines
don't say size is arbitrary, it's 8 bytes per CPU validate register size vs cpus
add validations for all initialization failures use percpu for percpu ipi ops
remove SMP and OF #ifdefs
document details about OpenRISC implied barriers use vendor prefix openrisc,
removed #interrupt-cells as this will not be a parent added some architecture documentation into the source
- enforce shadow register usage for SMP as suggested by Geert
- DTS updates suggested by Mark Rutland
Quoted 2 lines
Add and use vendor prefix openrisc, for ompic
Use stdout-path
-Stafford
Jan Henrik Weinstock (1):
openrisc: add cacheflush support to fix icache aliasing
Stafford Horne (9):
openrisc: define CPU_BIG_ENDIAN as true
openrisc: add 1 and 2 byte cmpxchg support
openrisc: use qspinlocks and qrwlocks
dt-bindings: add openrisc to vendor prefixes list
openrisc: fix initial preempt state for secondary cpu tasks
openrisc: sleep instead of spin on secondary wait
openrisc: support framepointers and STACKTRACE_SUPPORT
openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
openrisc: add tick timer multicore sync logic
Stefan Kristiansson (4):
openrisc: use shadow registers to save regs on exception
irqchip: add initial support for ompic
openrisc: initial SMP support
openrisc: add simple_smp dts and defconfig for simulators
.../interrupt-controller/openrisc,ompic.txt | 19 ++ .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/openrisc/Kconfig | 52 ++++- arch/openrisc/boot/dts/simple_smp.dts | 58 +++++ arch/openrisc/configs/simple_smp_defconfig | 66 ++++++ arch/openrisc/include/asm/Kbuild | 5 +- arch/openrisc/include/asm/cacheflush.h | 96 ++++++++ arch/openrisc/include/asm/cmpxchg.h | 147 +++++++++--- arch/openrisc/include/asm/cpuinfo.h | 7 +- arch/openrisc/include/asm/mmu_context.h | 2 +- arch/openrisc/include/asm/pgtable.h | 18 +- arch/openrisc/include/asm/serial.h | 2 +- arch/openrisc/include/asm/smp.h | 26 +++ arch/openrisc/include/asm/spinlock.h | 12 +- arch/openrisc/include/asm/spinlock_types.h | 7 + arch/openrisc/include/asm/spr_defs.h | 14 ++ arch/openrisc/include/asm/thread_info.h | 2 +- arch/openrisc/include/asm/time.h | 23 ++ arch/openrisc/include/asm/tlbflush.h | 25 +- arch/openrisc/include/asm/unwinder.h | 20 ++ arch/openrisc/kernel/Makefile | 4 +- arch/openrisc/kernel/dma.c | 14 +- arch/openrisc/kernel/entry.S | 74 +++++- arch/openrisc/kernel/head.S | 239 ++++++++++++++++--- arch/openrisc/kernel/setup.c | 165 ++++++++----- arch/openrisc/kernel/smp.c | 259 +++++++++++++++++++++ arch/openrisc/kernel/stacktrace.c | 86 +++++++ arch/openrisc/kernel/sync-timer.c | 120 ++++++++++ arch/openrisc/kernel/time.c | 66 ++++-- arch/openrisc/kernel/traps.c | 54 +---- arch/openrisc/kernel/unwinder.c | 105 +++++++++ arch/openrisc/lib/delay.c | 2 +- arch/openrisc/mm/Makefile | 2 +- arch/openrisc/mm/cache.c | 61 +++++ arch/openrisc/mm/fault.c | 4 +- arch/openrisc/mm/init.c | 2 +- arch/openrisc/mm/tlb.c | 16 +- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 ++++++++++++++++ 40 files changed, 1850 insertions(+), 234 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 arch/openrisc/boot/dts/simple_smp.dts create mode 100644 arch/openrisc/configs/simple_smp_defconfig create mode 100644 arch/openrisc/include/asm/cacheflush.h create mode 100644 arch/openrisc/include/asm/smp.h create mode 100644 arch/openrisc/include/asm/spinlock_types.h create mode 100644 arch/openrisc/include/asm/time.h create mode 100644 arch/openrisc/include/asm/unwinder.h create mode 100644 arch/openrisc/kernel/smp.c create mode 100644 arch/openrisc/kernel/stacktrace.c create mode 100644 arch/openrisc/kernel/sync-timer.c create mode 100644 arch/openrisc/kernel/unwinder.c create mode 100644 arch/openrisc/mm/cache.c create mode 100644 drivers/irqchip/irq-ompic.c
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 1/14 openrisc: use shadow registers to save regs on exception
From: Stefan Kristiansson <[email protected]>
Previously, the area between 0x0-0x100 have been used as a "scratch" memory area to temporarily store regs during exception entry. In a multi-core environment, this will not work.
This change is to use shadow registers for nested context.
Currently only the "critical" temp load/stores are covered, the EMERGENCY_PRINT ones are left as is (when they are used, it's game over anyway), they need to be handled as well in the future.
---
Changes since v1
- Added SMP checks in Kconfig
arch/openrisc/Kconfig | 11 ++++++ arch/openrisc/kernel/head.S | 95 ++++++++++++++++++++++++++++++++------------- 2 files changed, 80 insertions(+), 26 deletions(-)
arch/openrisc/Kconfig +11 -0
@@ -121,6 +121,17 @@ config OPENRISC_NO_SPR_SR_DSX Say N here if you know that your OpenRISC processor has SPR_SR_DSX bit implemented. Say Y if you are unsure. +config OPENRISC_HAVE_SHADOW_GPRS + bool "Support for shadow gpr files" if !SMP + default y if SMP + help + Say Y here if your OpenRISC processor features shadowed + register files. They will in such case be used as a + scratch reg storage on exception entry. + + On SMP systems, this feature is mandatory. + On a unicore system it's safe to say N here if you are unsure. + config CMDLINE string "Default kernel command string" default ""
arch/openrisc/kernel/head.S +69 -26
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2.13.5
Stafford Horne
maintainerPATCH v2 2/14 openrisc: define CPU_BIG_ENDIAN as true
In reply to Stafford HorneWhile working on SMP for OpenRISC I found this is needed for qrwlocks to work correctly. OpenRISC is big endian so this should have been here already.
--- arch/openrisc/Kconfig | 3 +++ 1 file changed, 3 insertions(+)
arch/openrisc/Kconfig +3 -0
@@ -29,6 +29,9 @@ config OPENRISC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select NO_BOOTMEM +config CPU_BIG_ENDIAN + def_bool y + config MMU def_bool y
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 3/14 openrisc: add 1 and 2 byte cmpxchg support
In reply to Stafford HorneOpenRISC only supports hardware instructions that perform 4 byte atomic operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte implementations are needed. To do this we leverage the 4 byte atomic operations and shift/mask the 1 and 2 byte areas as needed.
This heavily borrows ideas and routines from sh and mips, which do something similar.
--- arch/openrisc/include/asm/cmpxchg.h | 147 ++++++++++++++++++++++++++++-------- 1 file changed, 115 insertions(+), 32 deletions(-)
arch/openrisc/include/asm/cmpxchg.h +115 -32
@@ -1,32 +1,29 @@/* +* 1,2 and 4 byte cmpxchg and xchg implementations for OpenRISC. +* * Copyright (C) 2014 Stefan Kristiansson <[email protected]> +* Copyright (C) 2017 Stafford Horne <[email protected]> * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. +* +* Note: +* The portable implementations of 1 and 2 byte xchg and cmpxchg using a 4 +* byte cmpxchg is sourced heavily from the sh and mips implementations. */ #ifndef __ASM_OPENRISC_CMPXCHG_H#define __ASM_OPENRISC_CMPXCHG_H#include <linux/types.h> - -/* -* This function doesn't exist, so you'll get a linker error -* if something tries to do an invalid cmpxchg(). -*/ -extern void __cmpxchg_called_with_bad_pointer (void ); +#include <linux/bitops.h> #define __HAVE_ARCH_CMPXCHG 1 -static inline unsigned long -__cmpxchg (volatile void *ptr,unsigned long old,unsigned long new,int size) +static inline unsigned long cmpxchg_u32 (volatile void *ptr, +unsigned long old,unsigned long new) { -if (size !=4 ) { -__cmpxchg_called_with_bad_pointer (); -return old; - } - __asm__ __volatile__("1: l.lwa %0, 0(%1) \n" " l.sfeq %0, %2 \n"
@@ -43,6 +40,97 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)return old; } +static inline unsigned long xchg_u32 (volatile void *ptr, +unsigned long val) +{ + __asm__ __volatile__( +"1: l.lwa %0, 0(%1) \n" +" l.swa 0(%1), %2 \n" +" l.bnf 1b \n" +" l.nop \n" + :"=&r" (val) + :"r" (ptr),"r" (val) + :"cc" ,"memory" ); + +return val; +} + +static inline u32 cmpxchg_small (volatile void *ptr,u32 old,u32 new, +int size) +{ +int off = (unsigned long )ptr %sizeof (u32); +volatile u32 *p = ptr - off; +#ifdef __BIG_ENDIAN +int bitoff = (sizeof (u32) - size - off) *BITS_PER_BYTE ; +#else +int bitoff = off *BITS_PER_BYTE ; +#endif +u32 bitmask = ((0x1 << size *BITS_PER_BYTE ) -1 ) << bitoff; +u32 load32, old32, new32; +u32 ret; + + load32 =READ_ONCE (*p); + +while (true) { + ret = (load32 & bitmask) >> bitoff; +if (old != ret) +return ret; + + old32 = (load32 & ~bitmask) | (old << bitoff); + new32 = (load32 & ~bitmask) | (new << bitoff); + +/* Do 32 bit cmpxchg */ + load32 =cmpxchg_u32 (p, old32, new32); +if (load32 == old32) +return old; + } +} + +/* xchg */ + +static inline u32 xchg_small (volatile void *ptr,u32 x,int size) +{ +int off = (unsigned long )ptr %sizeof (u32); +volatile u32 *p = ptr - off; +#ifdef __BIG_ENDIAN +int bitoff = (sizeof (u32) - size - off) *BITS_PER_BYTE ; +#else +int bitoff = off *BITS_PER_BYTE ; +#endif +u32 bitmask = ((0x1 << size *BITS_PER_BYTE ) -1 ) << bitoff; +u32 oldv, newv; +u32 ret; + +do { + oldv =READ_ONCE (*p); + ret = (oldv & bitmask) >> bitoff; + newv = (oldv & ~bitmask) | (x << bitoff); + }while (cmpxchg_u32 (p, oldv, newv) != oldv); + +return ret; +} + +/* +* This function doesn't exist, so you'll get a linker error +* if something tries to do an invalid cmpxchg(). +*/ +extern unsigned long __cmpxchg_called_with_bad_pointer(void) + __compiletime_error("Bad argument size for cmpxchg"); + +static inline unsigned long __cmpxchg (volatile void *ptr,unsigned long old, +unsigned long new,int size) +{ +switch (size) { +case 1 : +case 2 : +return cmpxchg_small (ptr, old, new, size); +case 4 : +return cmpxchg_u32 (ptr, old, new); +default : +return __cmpxchg_called_with_bad_pointer (); + } +} +#define cmpxchg (ptr, o, n) \ ({ \ (__typeof__(*(ptr))) __cmpxchg((ptr), \
@@ -55,32 +143,27 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)* This function doesn't exist, so you'll get a linker error if * something tries to do an invalidly-sized xchg(). */ -extern void __xchg_called_with_bad_pointer (void ); +extern unsigned long __xchg_called_with_bad_pointer(void) + __compiletime_error("Bad argument size for xchg"); -static inline unsigned long __xchg (unsigned long val,volatile void *ptr, -int size) +static inline unsigned long __xchg (volatile void *ptr,unsigned long with, +int size) { -if (size !=4 ) { -__xchg_called_with_bad_pointer (); -return val; +switch (size) { +case 1 : +case 2 : +return xchg_small (ptr, with, size); +case 4 : +return xchg_u32 (ptr, with); +default : +return __xchg_called_with_bad_pointer (); } - - __asm__ __volatile__( -"1: l.lwa %0, 0(%1) \n" -" l.swa 0(%1), %2 \n" -" l.bnf 1b \n" -" l.nop \n" - :"=&r" (val) - :"r" (ptr),"r" (val) - :"cc" ,"memory" ); - -return val; }#define xchg (ptr, with) \ ({ \ - (__typeof__(*(ptr))) __xchg((unsigned long)(with), \ - (ptr), \ + (__typeof__(*(ptr))) __xchg((ptr), \ + (unsigned long)(with), \ sizeof(*(ptr))); \ })
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 4/14 openrisc: use qspinlocks and qrwlocks
In reply to Stafford HorneEnable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.
--- arch/openrisc/Kconfig | 2 ++ arch/openrisc/include/asm/Kbuild | 4 ++++ arch/openrisc/include/asm/spinlock.h | 12 +++++++++++- arch/openrisc/include/asm/spinlock_types.h | 7 +++++++ 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 arch/openrisc/include/asm/spinlock_types.h
arch/openrisc/Kconfig +2 -0
@@ -28,6 +28,8 @@ config OPENRISC select OR1K_PIC select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 select NO_BOOTMEM + select ARCH_USE_QUEUED_SPINLOCKS + select ARCH_USE_QUEUED_RWLOCKS config CPU_BIG_ENDIAN def_bool y
arch/openrisc/include/asm/Kbuild +4 -0
@@ -28,6 +28,10 @@ generic-y += module.h generic-y += pci.h generic-y += percpu.h generic-y += preempt.h +generic-y += qspinlock_types.h +generic-y += qspinlock.h +generic-y += qrwlock_types.h +generic-y += qrwlock.h generic-y += sections.h generic-y += segment.h generic-y += string.h
arch/openrisc/include/asm/spinlock.h +11 -1
@@ -19,6 +19,16 @@#ifndef __ASM_OPENRISC_SPINLOCK_H#define __ASM_OPENRISC_SPINLOCK_H -#error "or32 doesn't do SMP yet" +#include <asm/qspinlock.h> + +#include <asm/qrwlock.h> + +#define arch_read_lock_flags (lock, flags) arch_read_lock(lock) +#define arch_write_lock_flags (lock, flags) arch_write_lock(lock) + +#define arch_spin_relax (lock) cpu_relax() +#define arch_read_relax (lock) cpu_relax() +#define arch_write_relax (lock) cpu_relax() +#endif
arch/openrisc/include/asm/spinlock_types.h new file +7 -0
@@ -0,0 +1,7 @@ +#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H +#define _ASM_OPENRISC_SPINLOCK_TYPES_H + +#include <asm/qspinlock_types.h> +#include <asm/qrwlock_types.h> + +#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 5/14 dt-bindings: add openrisc to vendor prefixes list
In reply to Stafford HorneAdd OpenRISC.io to vendor prefixes. This is reserved for softcores developed by the OpenRISC community. The OpenRISC community has separated from OpenCores.org requiring a new prefix.
---
Changes since v1
- New patch
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/vendor-prefixes.txt +1 -0
@@ -241,6 +241,7 @@ onion Onion Corporation onnn ON Semiconductor Corp. ontat On Tat Industrial Company opencores OpenCores.org +openrisc OpenRISC.io option Option NV ORCL Oracle Corporation ortustech Ortus Technology Co., Ltd.
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Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list
Am 10.09.2017 um 08:49 schrieb Stafford Horne:
Quoted 5 lines
Add OpenRISC.io to vendor prefixes. This is reserved for softcores developed by the OpenRISC community. The OpenRISC community has separated from OpenCores.org requiring a new prefix.
Signed-off-by Stafford Horne <[email protected]>
Regards,
Andreas
Signature · 3 lines
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg)
Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list
In reply to Stafford HorneQuoted 4 lines · Stafford Horne
Add OpenRISC.io to vendor prefixes. This is reserved for softcores developed by the OpenRISC community. The OpenRISC community has separated from OpenCores.org requiring a new prefix.
Quoted 8 lines
Signed-off-by Stafford Horne <[email protected]>---
Changes since v1
- New patchDocumentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+)
Stafford Horne
maintainerPATCH v2 6/14 irqchip: add initial support for ompic
In reply to Stafford HorneFrom: Stefan Kristiansson <[email protected]>
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation.
---
Changes since v1
- Added openrisc, prefix
- Clarified 8 bytes per cpu
- Removed #interrupt-cells as this will not be an irq parent
- Changed ops to be percpu
- Added DTS and intialization failure validations
.../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.c
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +19 -0
@@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +};
arch/openrisc/Kconfig +1 -0
@@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool y
drivers/irqchip/Kconfig +3 -0
@@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP select SPARSE_IRQ default y +config OMPIC + bool + config OR1K_PIC bool select IRQ_DOMAIN
drivers/irqchip/Makefile +1 -0
@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o +obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
drivers/irqchip/irq-ompic.c new file +205 -0
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Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Quoted 109 lines · Stafford Horne
From: Stefan Kristiansson <[email protected]>
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation.
Signed-off-by Stefan Kristiansson <[email protected]>[[email protected]: converted ops to bitmask, wrote commit message]Signed-off-by Stafford Horne <[email protected]>---
Changes since v1
- Added openrisc, prefix
- Clarified 8 bytes per cpu
- Removed #interrupt-cells as this will not be an irq parent
- Changed ops to be percpu
- Added DTS and intialization failure validations.../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.cDocumentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +19
-0@@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +};arch/openrisc/Kconfig +1
-0@@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool ydrivers/irqchip/Kconfig +3
-0@@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP select SPARSE_IRQ default y +config OMPIC + bool + config OR1K_PIC bool select IRQ_DOMAINdrivers/irqchip/Makefile +1
-0@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o +obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.odrivers/irqchip/irq-ompic.c new file +2
-0@@ -0,0 +1,205 @@ +/* +* Open Multi-Processor Interrupt Controller driver
drivers/irqchip/irq-ompic.c line 12
Quoted 10 lines
drivers/irqchip/irq-ompic.c new file +10
-0+* +* Copyright (C) 2014 Stefan Kristiansson <[email protected]> +* Copyright (C) 2017 Stafford Horne <[email protected]> +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +* +* The ompic device handles IPI communication because cores in mulicore +* OpenRISC systems.
Should the above read "between cores"?
Quoted 75 lines
drivers/irqchip/irq-ompic.c new file +75
-0+* +* Registers +* +* For each CPU the ompic has 2 registers. The control register for sending +* and acking IPIs and the status register for receiving IPIs. The register +* layouts are as follows: +* +* Control register +* +---------+---------+----------+---------+ +* | 31 | 30 | 29 .. 16 | 15 .. 0 | +* ----------+---------+----------+---------- +* | IRQ ACK | IRQ GEN | DST CORE | DATA | +* +---------+---------+----------+---------+ +* +* Status register +* +----------+-------------+----------+---------+ +* | 31 | 30 | 29 .. 16 | 15 .. 0 | +* -----------+-------------+----------+---------+ +* | Reserved | IRQ Pending | SRC CORE | DATA | +* +----------+-------------+----------+---------+ +* +* Architecture +* +* - The ompic generates a level interrupt to the CPU PIC when a message is +* ready. Messages are delivered via the memory bus. +* - The ompic does not have any interrupt input lines. +* - The ompic is wired to the same irq line on each core. +* - Devices are wired to the same irq line on each core. +* +* +---------+ +---------+ +* | CPU | | CPU | +* | Core 0 |<==\ (memory access) /==>| Core 1 | +* | [ PIC ]| | | | [ PIC ]| +* +----^-^--+ | | +----^-^--+ +* | | v v | | +* <====|=|=================================|=|==> (memory bus) +* | | ^ ^ | | +* (ipi | +------|---------+--------|-------|-+ (device irq) +* irq | | | | | +* core0)| +------|---------|--------|-------+ (ipi irq core1) +* | | | | | +* +----o-o-+ | +--------+ | +* | ompic |<===/ | Device |<===/ +* | IPI | +--------+ +* +--------+* +* +*/ + +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/interrupt.h> +#include <linux/smp.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> + +#include <linux/irqchip.h> + +#define OMPIC_CPUBYTES 8 +#define OMPIC_CTRL (cpu) (0x0 + (cpu * OMPIC_CPUBYTES)) +#define OMPIC_STAT (cpu) (0x4 + (cpu * OMPIC_CPUBYTES)) + +#define OMPIC_CTRL_IRQ_ACK (1 << 31) +#define OMPIC_CTRL_IRQ_GEN (1 << 30) +#define OMPIC_CTRL_DST (cpu) (((cpu) & 0x3fff) << 16) + +#define OMPIC_STAT_IRQ_PENDING (1 << 30) + +#define OMPIC_DATA (x) ((x) & 0xffff) + +DEFINE_PER_CPU(unsigned long, ops); + +static void __iomem *ompic_base; + +static inline u32 ompic_readreg (void __iomem *base,loff_t offset)
drivers/irqchip/irq-ompic.c line 97
Quoted 10 lines
drivers/irqchip/irq-ompic.c new file +10
-0+{ +return ioread32be (base + offset); +} + +static void ompic_writereg (void __iomem *base,loff_t offset,u32 data) +{ +iowrite32be (data, base + offset); +} + +void ompic_raise_softirq (const struct cpumask *mask,unsigned int ipi_msg)
Please make this static.
drivers/irqchip/irq-ompic.c line 109
Quoted 12 lines
drivers/irqchip/irq-ompic.c new file +12
-0+{ +unsigned int dst_cpu; +unsigned int src_cpu =smp_processor_id (); + +for_each_cpu (dst_cpu, mask) { +set_bit (ipi_msg, &per_cpu (ops, dst_cpu)); + +/* +* On OpenRISC the atomic set_bit() call implies a memory +* barrier. Otherwise we would need: smp_wmb(); paired +* with the read in ompic_ipi_handler. +*/
One last question on this, because the architecture document is terribly
unclear: If you have CPU0 doing an atomic operation A0, CPU1 seeing A0 and doeing another atomic A1 (the set_bit above) followed by an IPI to CPU2, is CPU2 *guaranteed* to observe both A0 *and* A1? Because that's required by the IPI semantics, and you wouldn't see that kind of issue with only two CPUs.
drivers/irqchip/irq-ompic.c line 118
Quoted 9 lines
drivers/irqchip/irq-ompic.c new file +9
-0+ +ompic_writereg (ompic_base,OMPIC_CTRL (src_cpu), +OMPIC_CTRL_IRQ_GEN | +OMPIC_CTRL_DST (dst_cpu) | +OMPIC_DATA (1 )); + } +} + +irqreturn_t ompic_ipi_handler (int irq,void *dev_id)
This should be static.
Quoted 24 lines
drivers/irqchip/irq-ompic.c new file +24
-0+{ +unsigned int cpu =smp_processor_id (); +unsigned long *pending_ops = &per_cpu (ops, cpu); +unsigned long ops; + +ompic_writereg (ompic_base,OMPIC_CTRL (cpu),OMPIC_CTRL_IRQ_ACK ); +while ((ops =xchg (pending_ops,0 )) !=0 ) { + +/* +* On OpenRISC the atomic xchg() call implies a memory +* barrier. Otherwise we may need an smp_rmb(); paired +* with the write in ompic_raise_softirq. +*/ + +do { +unsigned long ipi_msg; + + ipi_msg =__ffs (ops); + ops &= ~(1UL << ipi_msg); + +handle_IPI (ipi_msg); + }while (ops); + } +
drivers/irqchip/irq-ompic.c line 152
Quoted 10 lines
drivers/irqchip/irq-ompic.c new file +10
-0+return IRQ_HANDLED ; +} + +static struct irqaction ompi_ipi_irqaction = { + .handler = ompic_ipi_handler, + .flags =IRQF_PERCPU , + .name ="ompic_ipi" , +}; + +int __init ompic_of_init (struct device_node *node,struct device_node *parent)
static again.
Quoted 43 lines
drivers/irqchip/irq-ompic.c new file +43
-0+{ +struct resource res; +int irq; +int ret; + +/* Validate the DT */ +if (ompic_base) { +pr_err ("ompic: duplicate ompic's are not supported" ); +return -EEXIST ; + } + +if (of_address_to_resource (node,0 , &res)) { +pr_err ("ompic: reg property requires an address and size" ); +return -EINVAL ; + } + +if (resource_size (&res) < (num_possible_cpus () *OMPIC_CPUBYTES )) { +pr_err ("ompic: reg size, currently %d must be at least %d" , +resource_size (&res), + (num_possible_cpus () *OMPIC_CPUBYTES )); +return -EINVAL ; + } + +/* Setup the device */ + ompic_base =ioremap (res.start,resource_size (&res)); +if (IS_ERR (ompic_base)) { +pr_err ("ompic: unable to map registers" ); +return PTR_ERR (ompic_base); + } + + irq =irq_of_parse_and_map (node,0 ); +if (irq <=0 ) { +pr_err ("ompic: unable to parse device irq" ); + ret = -EINVAL ; + goto out_unmap; + } + + ret =setup_irq (irq, &ompi_ipi_irqaction); +if (ret) + goto out_irq_disp; + +set_smp_cross_call (ompic_raise_softirq); +
drivers/irqchip/irq-ompic.c line 205
Quoted 10 lines
drivers/irqchip/irq-ompic.c new file +10
-0+return 0 ; + +out_irq_disp: +irq_dispose_mapping (irq); +out_unmap: +iounmap (ompic_base); + ompic_base =NULL ; +return ret; +} +IRQCHIP_DECLARE (ompic,"openrisc,ompic" , ompic_of_init);
Thanks,
M.
Signature · 5 lines
Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
Stafford Horne
maintainerRe: [PATCH v2 06/14] irqchip: add initial support for ompic
Quoted 114 lines · Marc Zyngier
Quoted 113 lines · Stafford Horne
From: Stefan Kristiansson <[email protected]>
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation.
Signed-off-by Stefan Kristiansson <[email protected]>[[email protected]: converted ops to bitmask, wrote commit message]Signed-off-by Stafford Horne <[email protected]>---
Changes since v1
- Added openrisc, prefix
- Clarified 8 bytes per cpu
- Removed #interrupt-cells as this will not be an irq parent
- Changed ops to be percpu
- Added DTS and intialization failure validations.../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.cDocumentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +19
-0@@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +};arch/openrisc/Kconfig +1
-0@@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool ydrivers/irqchip/Kconfig +3
-0@@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP select SPARSE_IRQ default y +config OMPIC + bool + config OR1K_PIC bool select IRQ_DOMAINdrivers/irqchip/Makefile +1
-0@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o +obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.odrivers/irqchip/irq-ompic.c new file +6
-0@@ -0,0 +1,205 @@ +/* +* Open Multi-Processor Interrupt Controller driver +* +* Copyright (C) 2014 Stefan Kristiansson <[email protected]> +* Copyright (C) 2017 Stafford Horne <[email protected]> +*
Quoted 8 lines
drivers/irqchip/irq-ompic.c line 12
Quoted 6 lines
drivers/irqchip/irq-ompic.c new file +6
-0+* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +* +* The ompic device handles IPI communication because cores in mulicore +* OpenRISC systems. Should the above read "between cores"?
Yes, it should be, I am bad with these kind of typos.
Quoted 79 lines
Quoted 79 lines
drivers/irqchip/irq-ompic.c new file +79
-0+* +* Registers +* +* For each CPU the ompic has 2 registers. The control register for sending +* and acking IPIs and the status register for receiving IPIs. The register +* layouts are as follows: +* +* Control register +* +---------+---------+----------+---------+ +* | 31 | 30 | 29 .. 16 | 15 .. 0 | +* ----------+---------+----------+---------- +* | IRQ ACK | IRQ GEN | DST CORE | DATA | +* +---------+---------+----------+---------+ +* +* Status register +* +----------+-------------+----------+---------+ +* | 31 | 30 | 29 .. 16 | 15 .. 0 | +* -----------+-------------+----------+---------+ +* | Reserved | IRQ Pending | SRC CORE | DATA | +* +----------+-------------+----------+---------+ +* +* Architecture +* +* - The ompic generates a level interrupt to the CPU PIC when a message is +* ready. Messages are delivered via the memory bus. +* - The ompic does not have any interrupt input lines. +* - The ompic is wired to the same irq line on each core. +* - Devices are wired to the same irq line on each core. +* +* +---------+ +---------+ +* | CPU | | CPU | +* | Core 0 |<==\ (memory access) /==>| Core 1 | +* | [ PIC ]| | | | [ PIC ]| +* +----^-^--+ | | +----^-^--+ +* | | v v | | +* <====|=|=================================|=|==> (memory bus) +* | | ^ ^ | | +* (ipi | +------|---------+--------|-------|-+ (device irq) +* irq | | | | | +* core0)| +------|---------|--------|-------+ (ipi irq core1) +* | | | | | +* +----o-o-+ | +--------+ | +* | ompic |<===/ | Device |<===/ +* | IPI | +--------+ +* +--------+* +* +*/ + +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/interrupt.h> +#include <linux/smp.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> + +#include <linux/irqchip.h> + +#define OMPIC_CPUBYTES 8 +#define OMPIC_CTRL (cpu) (0x0 + (cpu * OMPIC_CPUBYTES)) +#define OMPIC_STAT (cpu) (0x4 + (cpu * OMPIC_CPUBYTES)) + +#define OMPIC_CTRL_IRQ_ACK (1 << 31) +#define OMPIC_CTRL_IRQ_GEN (1 << 30) +#define OMPIC_CTRL_DST (cpu) (((cpu) & 0x3fff) << 16) + +#define OMPIC_STAT_IRQ_PENDING (1 << 30) + +#define OMPIC_DATA (x) ((x) & 0xffff) + +DEFINE_PER_CPU(unsigned long, ops); + +static void __iomem *ompic_base; + +static inline u32 ompic_readreg (void __iomem *base,loff_t offset) +{ +return ioread32be (base + offset); +} +
Quoted 8 lines
drivers/irqchip/irq-ompic.c line 97
Quoted 6 lines
drivers/irqchip/irq-ompic.c new file +6
-0+static void ompic_writereg (void __iomem *base,loff_t offset,u32 data) +{ +iowrite32be (data, base + offset); +} + +void ompic_raise_softirq (const struct cpumask *mask,unsigned int ipi_msg)Please make this static.
OK
Quoted 11 lines
Quoted 11 lines
drivers/irqchip/irq-ompic.c new file +11
-0+{ +unsigned int dst_cpu; +unsigned int src_cpu =smp_processor_id (); + +for_each_cpu (dst_cpu, mask) { +set_bit (ipi_msg, &per_cpu (ops, dst_cpu)); + +/* +* On OpenRISC the atomic set_bit() call implies a memory +* barrier. Otherwise we would need: smp_wmb(); paired +* with the read in ompic_ipi_handler.
Quoted 8 lines
drivers/irqchip/irq-ompic.c line 109
Quoted 1 line
drivers/irqchip/irq-ompic.c new file +1
-0+*/ One last question on this, because the architecture document is terribly
unclear: If you have CPU0 doing an atomic operation A0, CPU1 seeing A0 and doeing another atomic A1 (theset_bitabove) followed by an IPI to CPU2, is CPU2 *guaranteed* to observe both A0 *and* A1? Because that's required by the IPI semantics, and you wouldn't see that kind of issue with only two CPUs.
Could you suggest an architecture document that makes this case clear?
I believe this will not be a problem, but:
1. If this needs to be clear in the architecture document I can propose changes.
2. To be clear is this the scenario you mean..
CASE1 - A0 and A1 are to different locations?
A0 - writes to some unrelated global location?
CPU0 CPU1 CPU2
A0:atomic store (global)
A1:set_bit (ops[CPU2])
IPI
read (A0,A1)OR
CASE2 - A0 and A1 are to the same location.
A0 - writes to the same location as A1
CPU0 CPU1 CPU2
A0:set_bit (ops[CPU2])
A1:set_bit (ops[CPU2])
IPI
read (A0,A1)IPI
OR - something else?
In both cases CPU2 would be able to see the results of both atomic operations. All, cpus in the OpenRISC system snoop for memory writes to enable cash coherency, so each CPU would see each write once it is synced to memory (there is a single memory bus). This is not limited to atomic operations, but the atomic operations provide a syncrhonization point accross all CPUs.
Quoted 11 lines
drivers/irqchip/irq-ompic.c line 118
Quoted 9 lines
drivers/irqchip/irq-ompic.c new file +9
-0+ +ompic_writereg (ompic_base,OMPIC_CTRL (src_cpu), +OMPIC_CTRL_IRQ_GEN | +OMPIC_CTRL_DST (dst_cpu) | +OMPIC_DATA (1 )); + } +} + +irqreturn_t ompic_ipi_handler (int irq,void *dev_id)This should be static.
OK
Quoted 28 lines
Quoted 28 lines
drivers/irqchip/irq-ompic.c new file +28
-0+{ +unsigned int cpu =smp_processor_id (); +unsigned long *pending_ops = &per_cpu (ops, cpu); +unsigned long ops; + +ompic_writereg (ompic_base,OMPIC_CTRL (cpu),OMPIC_CTRL_IRQ_ACK ); +while ((ops =xchg (pending_ops,0 )) !=0 ) { + +/* +* On OpenRISC the atomic xchg() call implies a memory +* barrier. Otherwise we may need an smp_rmb(); paired +* with the write in ompic_raise_softirq. +*/ + +do { +unsigned long ipi_msg; + + ipi_msg =__ffs (ops); + ops &= ~(1UL << ipi_msg); + +handle_IPI (ipi_msg); + }while (ops); + } + +return IRQ_HANDLED ; +} + +static struct irqaction ompi_ipi_irqaction = {
Quoted 8 lines
drivers/irqchip/irq-ompic.c line 152
Quoted 6 lines
drivers/irqchip/irq-ompic.c new file +6
-0+ .handler = ompic_ipi_handler, + .flags = IRQF_PERCPU, + .name = "ompic_ipi", +}; + +int __init ompic_of_init (struct device_node *node,struct device_node *parent)static again.
OK
Quoted 45 lines
Quoted 45 lines
drivers/irqchip/irq-ompic.c new file +45
-0+{ +struct resource res; +int irq; +int ret; + +/* Validate the DT */ +if (ompic_base) { +pr_err ("ompic: duplicate ompic's are not supported" ); +return -EEXIST ; + } + +if (of_address_to_resource (node,0 , &res)) { +pr_err ("ompic: reg property requires an address and size" ); +return -EINVAL ; + } + +if (resource_size (&res) < (num_possible_cpus () *OMPIC_CPUBYTES )) { +pr_err ("ompic: reg size, currently %d must be at least %d" , +resource_size (&res), + (num_possible_cpus () *OMPIC_CPUBYTES )); +return -EINVAL ; + } + +/* Setup the device */ + ompic_base =ioremap (res.start,resource_size (&res)); +if (IS_ERR (ompic_base)) { +pr_err ("ompic: unable to map registers" ); +return PTR_ERR (ompic_base); + } + + irq =irq_of_parse_and_map (node,0 ); +if (irq <=0 ) { +pr_err ("ompic: unable to parse device irq" ); + ret = -EINVAL ; + goto out_unmap; + } + + ret =setup_irq (irq, &ompi_ipi_irqaction); +if (ret) + goto out_irq_disp; + +set_smp_cross_call (ompic_raise_softirq); + +return 0 ; +
Quoted 9 lines
drivers/irqchip/irq-ompic.c line 205
Quoted 8 lines
drivers/irqchip/irq-ompic.c new file +8
-0+out_irq_disp: +irq_dispose_mapping (irq); +out_unmap: +iounmap (ompic_base); + ompic_base =NULL ; +return ret; +} +IRQCHIP_DECLARE (ompic,"openrisc,ompic" , ompic_of_init);
Thanks for your time!
-Stafford
ps: Frank Zappa rocks :)
--
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Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Quoted 1 line · Stafford Horne
On Wed, Sep 13, 2017 at 06:21:39PM +0100, Marc Zyngier wrote:
[...]
Quoted 42 lines
Quoted 11 lines
Quoted 11 lines
drivers/irqchip/irq-ompic.c new file +11
-0+{ +unsigned int dst_cpu; +unsigned int src_cpu =smp_processor_id (); + +for_each_cpu (dst_cpu, mask) { +set_bit (ipi_msg, &per_cpu (ops, dst_cpu)); + +/* +* On OpenRISC the atomic set_bit() call implies a memory +* barrier. Otherwise we would need: smp_wmb(); paired +* with the read in ompic_ipi_handler. Quoted 8 lines
Review
Quoted 1 line
(quoted diff) +1
-0+ */One last question on this, because the architecture document is terribly
unclear: If you have CPU0 doing an atomic operation A0, CPU1 seeing A0 and doeing another atomic A1 (theset_bitabove) followed by an IPI to CPU2, is CPU2 *guaranteed* to observe both A0 *and* A1? Because that's required by the IPI semantics, and you wouldn't see that kind of issue with only two CPUs.Could you suggest an architecture document that makes this case clear?
I believe this will not be a problem, but:
1. If this needs to be clear in the architecture document I can propose changes.
2. To be clear is this the scenario you mean..CASE1 - A0 and A1 are to different locations?
A0 - writes to some unrelated global location?CPU0 CPU1 CPU2
A0:atomic store (global)A1:set_bit (ops[CPU2]) IPI read (A0,A1)OR
CASE2 - A0 and A1 are to the same location.
A0 - writes to the same location as A1
Quoted 6 lines
CPU0 CPU1 CPU2
A0:set_bit (ops[CPU2])A1:set_bit (ops[CPU2]) IPI read (A0,A1)IPI
I think this covers both cases I had in mind.
Quoted 10 lines
OR - something else?
In both cases CPU2 would be able to see the results of both atomic operations. All, cpus in the OpenRISC system snoop for memory writes to enable cash coherency, so each CPU would see each write once it is synced to memory (there is a single memory bus). This is not limited to atomic operations, but the atomic operations provide a syncrhonization point accross all CPUs.
OK. It would be good if the architecture document had something about transitivity of writes on SMP (maybe it has, I only went through it pretty quickly). But overall, the above will work correctly.
Quoted 1 line
ps: Frank Zappa rocks :)
His music certainly does! ;-)
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny.
Rob Herring
maintainerRe: [PATCH v2 06/14] irqchip: add initial support for ompic
In reply to Stafford HorneQuoted 124 lines · Stafford Horne
Quoted 114 lines · Marc Zyngier
Quoted 113 lines · Stafford Horne
From: Stefan Kristiansson <[email protected]>
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation.
Signed-off-by Stefan Kristiansson <[email protected]>[[email protected]: converted ops to bitmask, wrote commit message]Signed-off-by Stafford Horne <[email protected]>---
Changes since v1
- Added openrisc, prefix
- Clarified 8 bytes per cpu
- Removed #interrupt-cells as this will not be an irq parent
- Changed ops to be percpu
- Added DTS and intialization failure validations.../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.cDocumentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +19
-0@@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +};arch/openrisc/Kconfig +1
-0@@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool ydrivers/irqchip/Kconfig +3
-0@@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP select SPARSE_IRQ default y +config OMPIC + bool + config OR1K_PIC bool select IRQ_DOMAINdrivers/irqchip/Makefile +1
-0@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o +obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.odrivers/irqchip/irq-ompic.c new file +6
-0@@ -0,0 +1,205 @@ +/* +* Open Multi-Processor Interrupt Controller driver +* +* Copyright (C) 2014 Stefan Kristiansson <[email protected]> +* Copyright (C) 2017 Stafford Horne <[email protected]> +* Quoted 8 lines
drivers/irqchip/irq-ompic.c line 12
Quoted 6 lines
drivers/irqchip/irq-ompic.c new file +6
-0+* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +* +* The ompic device handles IPI communication because cores in mulicore +* OpenRISC systems. Should the above read "between cores"?
Quoted 1 line
Yes, it should be, I am bad with these kind of typos.
And "multi-core"
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Stafford Horne
maintainerRe: [PATCH v2 06/14] irqchip: add initial support for ompic
Quoted 5 lines · Rob Herring
Quoted 4 lines · Stafford Horne
Quoted 3 lines · Marc Zyngier
Quoted 2 lines · Stafford Horne
From: Stefan Kristiansson <[email protected]>
[..]
Quoted 21 lines
Quoted 21 lines
Quoted 20 lines
Quoted 8 lines
drivers/irqchip/irq-ompic.c new file +2
-0@@ -0,0 +1,205 @@ +/* +* Open Multi-Processor Interrupt Controller driver drivers/irqchip/irq-ompic.c line 12
Quoted 10 lines
drivers/irqchip/irq-ompic.c new file +10
-0+* +* Copyright (C) 2014 Stefan Kristiansson <[email protected]> +* Copyright (C) 2017 Stafford Horne <[email protected]> +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +* +* The ompic device handles IPI communication because cores in mulicore +* OpenRISC systems. Should the above read "between cores"?
Quoted 3 lines
Quoted 1 line
Yes, it should be, I am bad with these kind of typos.
And "multi-core"
Thanks, and I have many s/multicore/multi-core/ issues throughout the patch series as well.
-Stafford
Rob Herring
maintainerRe: [PATCH v2 06/14] irqchip: add initial support for ompic
In reply to Stafford HorneQuoted 20 lines · Stafford Horne
From: Stefan Kristiansson <[email protected]>
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation.
Signed-off-by Stefan Kristiansson <[email protected]>[[email protected]: converted ops to bitmask, wrote commit message]Signed-off-by Stafford Horne <[email protected]>
Quoted 6 lines
---
Changes since v1
- Added openrisc, prefix
- Clarified 8 bytes per cpu
- Removed #interrupt-cells as this will not be an irq parent
You should still have #interrupt-cells as that is required with "interrupt-controller". It could be 0 though.
Quoted 22 lines
- Changed ops to be percpu
- Added DTS and intialization failure validations.../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.cDocumentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +4
-0@@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: +
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt line 14
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +10
-0+- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic {
interrupt-controller@98000000 {
Quoted 5 lines
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +5
-0+ compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +};
Stafford Horne
maintainerRe: [PATCH v2 06/14] irqchip: add initial support for ompic
Quoted 23 lines · Rob Herring
Quoted 22 lines · Stafford Horne
From: Stefan Kristiansson <[email protected]>
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation.
Signed-off-by Stefan Kristiansson <[email protected]>[[email protected]: converted ops to bitmask, wrote commit message]Signed-off-by Stafford Horne <[email protected]>---
Quoted 7 lines
Quoted 4 lines
Changes since v1
- Added openrisc, prefix
- Clarified 8 bytes per cpu
- Removed #interrupt-cells as this will not be an irq parentYou should still have #interrupt-cells as that is required with "interrupt-controller". It could be 0 though.
Thanks, I didn't notice that from reading the code. I will update it.
Quoted 26 lines
Quoted 26 lines
- Changed ops to be percpu
- Added DTS and intialization failure validations.../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.cDocumentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +8
-0@@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core.
Quoted 8 lines
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt line 14
Quoted 6 lines
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +6
-0+- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic {interrupt-controller@98000000 {
OK, I will change to the format. But I notice many other docs like this:
ompic: interrupt-controller@98000000 {Quoted 5 lines
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt line 19
Quoted 5 lines
Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file +5
-0+ compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +};
Thanks for the review.
-Stafford
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Stafford Horne
maintainerPATCH v2 7/14 openrisc: initial SMP support
In reply to Stafford HorneFrom: Stefan Kristiansson <[email protected]>
This patch introduces the SMP support for the OpenRISC architecture. The SMP architecture requires cores which have multicore features which have been introduced a few years back including:
- New SPRS SPR_COREID SPR_NUMCORES
- Shadow SPRs
- Atomic Instructions
- Cache Coherency
- A wired in IPI controller
This patch adds all of the SMP specific changes to core infrastructure, it looks big but it needs to go all together as its hard to split this one up.
Boot loader spinning of second cpu is not supported yet, it's assumed that Linux is booted straight after cpu reset.
The bulk of these changes are trivial changes to refactor to use per cpu data structures throughout. The addition of the smp.c and changes in time.c are the changes. Some specific notes:
MM changes
----------
The reason why this is created as an array, and not with DEFINE_PER_CPU is that doing it this way, we'll save a load in the tlb-miss handler (the load from __per_cpu_offset).
TLB Flush
---------
The SMP implementation of flush_tlb_* works by sending out a function-call IPI to all the non-local cpus by using the generic on_each_cpu() function.
Currently, all flush_tlb_* functions will result in a flush_tlb_all(), which has always been the behaviour in the UP case.
CPU INFO
--------
This creates a per cpu cpuinfo struct and fills it out accordingly for each activated cpu. show_cpuinfo is also updated to reflect new version information in later versions of the spec.
SMP API
-------
This imitates the arm64 implementation by having a smp_cross_call callback that can be set by set_smp_cross_call to initiate an IPI and a handle_IPI function that is expected to be called from an IPI irqchip driver.
---
Changes since v1
- Added time.h for timer initialization
- Don't crash on boot if IPI initialization fails
- Removed volatile on secondary_release flag (checkpatch report)
- Change ipi variable name from ipi_msg from
arch/openrisc/Kconfig | 17 ++- arch/openrisc/include/asm/cpuinfo.h | 7 +- arch/openrisc/include/asm/mmu_context.h | 2 +- arch/openrisc/include/asm/pgtable.h | 2 +- arch/openrisc/include/asm/serial.h | 2 +- arch/openrisc/include/asm/smp.h | 26 ++++ arch/openrisc/include/asm/spr_defs.h | 14 ++ arch/openrisc/include/asm/time.h | 15 ++ arch/openrisc/include/asm/tlbflush.h | 25 +++- arch/openrisc/kernel/Makefile | 1 + arch/openrisc/kernel/dma.c | 14 +- arch/openrisc/kernel/head.S | 97 ++++++++++++- arch/openrisc/kernel/setup.c | 165 ++++++++++++++-------- arch/openrisc/kernel/smp.c | 235 ++++++++++++++++++++++++++++++++ arch/openrisc/kernel/time.c | 51 ++++--- arch/openrisc/lib/delay.c | 2 +- arch/openrisc/mm/fault.c | 4 +- arch/openrisc/mm/init.c | 2 +- arch/openrisc/mm/tlb.c | 16 +-- 19 files changed, 584 insertions(+), 113 deletions(-) create mode 100644 arch/openrisc/include/asm/smp.h create mode 100644 arch/openrisc/include/asm/time.h create mode 100644 arch/openrisc/kernel/smp.c
arch/openrisc/Kconfig +15 -2
@@ -21,8 +21,10 @@ config OPENRISC select HAVE_UID16 select GENERIC_ATOMIC64 select GENERIC_CLOCKEVENTS + select GENERIC_CLOCKEVENTS_BROADCAST select GENERIC_STRNCPY_FROM_USER select GENERIC_STRNLEN_USER + select GENERIC_SMP_IDLE_THREAD select MODULES_USE_ELF_RELA select HAVE_DEBUG_STACKOVERFLOW select OR1K_PIC
@@ -107,8 +109,19 @@ config OPENRISC_HAVE_INST_DIV endmenu config NR_CPUS - int - default "1" + int "Maximum number of CPUs (2-32)" + range 2 32 + depends on SMP + default "2" + +config SMP + bool "Symmetric Multi-Processing support" + help + This enables support for systems with more than one CPU. If you have + a system with only one CPU, say N. If you have a system with more + than one CPU, say Y. + + If you don't know what to do here, say N. source kernel/Kconfig.hz source kernel/Kconfig.preempt
arch/openrisc/include/asm/cpuinfo.h +5 -2
@@ -19,7 +19,7 @@ #ifndef __ASM_OPENRISC_CPUINFO_H #define __ASM_OPENRISC_CPUINFO_H -struct cpuinfo { +struct cpuinfo_or1k { u32 clock_frequency; u32 icache_size;
@@ -29,8 +29,11 @@ struct cpuinfo {u32 dcache_size;u32 dcache_block_size;u32 dcache_ways; + + u16 coreid; }; -extern struct cpuinfo cpuinfo; +extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS ]; +extern void setup_cpuinfo (void );#endif /* __ASM_OPENRISC_CPUINFO_H */
arch/openrisc/include/asm/mmu_context.h +1 -1
@@ -34,7 +34,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,* registers like cr3 on the i386 */ -extern volatile pgd_t *current_pgd;/* defined in arch/openrisc/mm/fault.c */ +extern volatile pgd_t *current_pgd[];/* defined in arch/openrisc/mm/fault.c */ static inline void enter_lazy_tlb (struct mm_struct *mm,struct task_struct *tsk) {
arch/openrisc/include/asm/pgtable.h +1 -1
@@ -94,7 +94,7 @@ extern void paging_init(void);* 64 MB of vmalloc area is comparable to what's available on other arches. */ -#define VMALLOC_START (PAGE_OFFSET-0x04000000) +#define VMALLOC_START (PAGE_OFFSET-0x04000000UL)#define VMALLOC_END (PAGE_OFFSET)#define VMALLOC_VMADDR (x) ((unsigned long)(x))
arch/openrisc/include/asm/serial.h +1 -1
@@ -29,7 +29,7 @@* it needs to be correct to get the early console working. */ -#define BASE_BAUD (cpuinfo.clock_frequency/16) +#define BASE_BAUD (cpuinfo_or1k[smp_processor_id()].clock_frequency/16)#endif /* __KERNEL__ */
arch/openrisc/include/asm/smp.h new file +26 -0
@@ -0,0 +1,26 @@ +/* +* Copyright (C) 2014 Stefan Kristiansson <[email protected]> +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __ASM_OPENRISC_SMP_H +#define __ASM_OPENRISC_SMP_H + +#include <asm/spr.h> +#include <asm/spr_defs.h> + +#define raw_smp_processor_id () (current_thread_info()->cpu) +#define hard_smp_processor_id () mfspr(SPR_COREID) + +extern void smp_init_cpus (void ); + +extern void arch_send_call_function_single_ipi (int cpu); +extern void arch_send_call_function_ipi_mask (const struct cpumask *mask); + +extern void set_smp_cross_call (void (*)(const struct cpumask *,unsigned int )); +extern void handle_IPI (unsigned int ipi_msg); + +#endif /* __ASM_OPENRISC_SMP_H */
arch/openrisc/include/asm/spr_defs.h +14 -0
@@ -51,6 +51,11 @@#define SPR_ICCFGR (SPRGROUP_SYS + 6)#define SPR_DCFGR (SPRGROUP_SYS + 7)#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_VR2 (SPRGROUP_SYS + 9) +#define SPR_AVR (SPRGROUP_SYS + 10) +#define SPR_EVBAR (SPRGROUP_SYS + 11) +#define SPR_AECR (SPRGROUP_SYS + 12) +#define SPR_AESR (SPRGROUP_SYS + 13)#define SPR_NPC (SPRGROUP_SYS + 16)/* CZ 21/06/01 */ #define SPR_SR (SPRGROUP_SYS + 17)/* CZ 21/06/01 */ #define SPR_PPC (SPRGROUP_SYS + 18)/* CZ 21/06/01 */
@@ -61,6 +66,8 @@#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)#define SPR_ESR_BASE (SPRGROUP_SYS + 64)#define SPR_ESR_LAST (SPRGROUP_SYS + 79) +#define SPR_COREID (SPRGROUP_SYS + 128) +#define SPR_NUMCORES (SPRGROUP_SYS + 129)#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)/* Data MMU group */
@@ -135,12 +142,19 @@#define SPR_VR_CFG 0x00ff0000/* Processor configuration */ #define SPR_VR_RES 0x0000ffc0/* Reserved */ #define SPR_VR_REV 0x0000003f/* Processor revision */ +#define SPR_VR_UVRP 0x00000040/* Updated Version Registers Present */ #define SPR_VR_VER_OFF 24#define SPR_VR_CFG_OFF 16#define SPR_VR_REV_OFF 0/* +* Bit definitions for the Version Register 2 +*/ +#define SPR_VR2_CPUID 0xff000000/* Processor ID */ +#define SPR_VR2_VER 0x00ffffff/* Processor version */ + +/* * Bit definitions for the Unit Present Register * */
arch/openrisc/include/asm/time.h new file +15 -0
@@ -0,0 +1,15 @@ +/* +* OpenRISC timer API +* +* Copyright (C) 2017 by Stafford Horne (shorne at gmail.com) +* +* This file is subject to the terms and conditions of the GNU General Public +* License. See the file "COPYING" in the main directory of this archive +* for more details. +*/ +#ifndef __ASM_OR1K_TIME_H +#define __ASM_OR1K_TIME_H + +extern void openrisc_clockevent_init (void ); + +#endif /* __ASM_OR1K_TIME_H */
arch/openrisc/include/asm/tlbflush.h +19 -6
@@ -33,13 +33,26 @@* - flush_tlb_page(vma, vmaddr) flushes one page * - flush_tlb_range(mm, start, end) flushes a range of pages */ +extern void local_flush_tlb_all (void ); +extern void local_flush_tlb_mm (struct mm_struct *mm); +extern void local_flush_tlb_page (struct vm_area_struct *vma, +unsigned long addr); +extern void local_flush_tlb_range (struct vm_area_struct *vma, +unsigned long start, +unsigned long end); -void flush_tlb_all (void ); -void flush_tlb_mm (struct mm_struct *mm); -void flush_tlb_page (struct vm_area_struct *vma,unsigned long addr); -void flush_tlb_range (struct vm_area_struct *vma, -unsigned long start, -unsigned long end); +#ifndef CONFIG_SMP +#define flush_tlb_all local_flush_tlb_all +#define flush_tlb_mm local_flush_tlb_mm +#define flush_tlb_page local_flush_tlb_page +#define flush_tlb_range local_flush_tlb_range +#else +extern void flush_tlb_all (void ); +extern void flush_tlb_mm (struct mm_struct *mm); +extern void flush_tlb_page (struct vm_area_struct *vma,unsigned long addr); +extern void flush_tlb_range (struct vm_area_struct *vma,unsigned long start, +unsigned long end); +#endif static inline void flush_tlb (void ) {
arch/openrisc/kernel/Makefile +1 -0
@@ -8,6 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o +obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o
arch/openrisc/kernel/dma.c +9 -5
@@ -32,6 +32,7 @@ page_set_nocache(pte_t *pte, unsigned long addr, unsigned long next, struct mm_walk *walk) { unsigned long cl; +struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id ()];pte_val (*pte) |= _PAGE_CI;
@@ -42,7 +43,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,flush_tlb_page (NULL , addr);/* Flush page out of dcache */ -for (cl =__pa (addr); cl <__pa (next); cl += cpuinfo.dcache_block_size) +for (cl =__pa (addr); cl <__pa (next); cl += cpuinfo->dcache_block_size)mtspr (SPR_DCBFR , cl);return 0 ;
@@ -140,6 +141,7 @@ or1k_map_page(struct device *dev, struct page *page, {unsigned long cl;dma_addr_t addr =page_to_phys (page) + offset; +struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id ()];if (attrs &DMA_ATTR_SKIP_CPU_SYNC )return addr;
@@ -148,13 +150,13 @@ or1k_map_page(struct device *dev, struct page *page,case DMA_TO_DEVICE :/* Flush the dcache for the requested range */ for (cl = addr; cl < addr + size; - cl += cpuinfo.dcache_block_size) + cl += cpuinfo->dcache_block_size)mtspr (SPR_DCBFR , cl);break ;case DMA_FROM_DEVICE :/* Invalidate the dcache for the requested range */ for (cl = addr; cl < addr + size; - cl += cpuinfo.dcache_block_size) + cl += cpuinfo->dcache_block_size)mtspr (SPR_DCBIR , cl);break ;default :
@@ -213,9 +215,10 @@ or1k_sync_single_for_cpu(struct device *dev, {unsigned long cl;dma_addr_t addr = dma_handle; +struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id ()];/* Invalidate the dcache for the requested range */ -for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size) +for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)mtspr (SPR_DCBIR , cl); }
@@ -226,9 +229,10 @@ or1k_sync_single_for_device(struct device *dev, {unsigned long cl;dma_addr_t addr = dma_handle; +struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id ()];/* Flush the dcache for the requested range */ -for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size) +for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)mtspr (SPR_DCBFR , cl); }
arch/openrisc/kernel/head.S +92 -5
126 lines not on this page · raw message
arch/openrisc/kernel/setup.c +107 -58
247 lines not on this page · raw message
arch/openrisc/kernel/smp.c new file +235 -0
235 lines not on this page · raw message
arch/openrisc/kernel/time.c +31 -20
82 lines not on this page · raw message
arch/openrisc/lib/delay.c +1 -1
@@ -25,7 +25,7 @@int read_current_timer (unsigned long *timer_value) { - *timer_value =mfspr (SPR_TTCR ); + *timer_value =get_cycles ();return 0 ; }
arch/openrisc/mm/fault.c +2 -2
@@ -33,7 +33,7 @@ unsigned long pte_errors; /* updated by do_page_fault() *//* __PHX__ :: - check the vmalloc_fault in do_page_fault() * - also look into include/asm-or32/mmu_context.h */ -volatile pgd_t *current_pgd; +volatile pgd_t *current_pgd[NR_CPUS ];extern void die (char *,struct pt_regs *,long );
@@ -319,7 +319,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address,phx_mmu("vmalloc_fault"); */ - pgd = (pgd_t *)current_pgd + offset; + pgd = (pgd_t *)current_pgd[smp_processor_id ()] + offset; pgd_k = init_mm.pgd + offset;/* Since we're two-level, we don't need to do both
arch/openrisc/mm/init.c +1 -1
@@ -147,7 +147,7 @@ void __init paging_init(void)* (even if it is most probably not used until the next * switch_mm) */ - current_pgd = init_mm.pgd; + current_pgd[smp_processor_id ()] = init_mm.pgd; end = (unsigned long )__va (max_low_pfn *PAGE_SIZE );
arch/openrisc/mm/tlb.c +8 -8
@@ -49,7 +49,7 @@* */ -void flush_tlb_all (void ) +void local_flush_tlb_all (void ) {int i;unsigned long num_tlb_sets;
@@ -86,7 +86,7 @@ void flush_tlb_all(void)#define flush_itlb_page_no_eir (addr) \ mtspr_off(SPR_ITLBMR_BASE(0), ITLB_OFFSET(addr), 0); -void flush_tlb_page (struct vm_area_struct *vma,unsigned long addr) +void local_flush_tlb_page (struct vm_area_struct *vma,unsigned long addr) {if (have_dtlbeir)flush_dtlb_page_eir (addr);
@@ -99,8 +99,8 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)flush_itlb_page_no_eir (addr); } -void flush_tlb_range (struct vm_area_struct *vma, -unsigned long start,unsigned long end) +void local_flush_tlb_range (struct vm_area_struct *vma, +unsigned long start,unsigned long end) {int addr;bool dtlbeir;
@@ -129,13 +129,13 @@ void flush_tlb_range(struct vm_area_struct *vma,* This should be changed to loop over over mm and call flush_tlb_range. */ -void flush_tlb_mm (struct mm_struct *mm) +void local_flush_tlb_mm (struct mm_struct *mm) {/* Was seeing bugs with the mm struct passed to us. Scrapped most of this function. */ /* Several architctures do this */ -flush_tlb_all (); +local_flush_tlb_all (); }/* called in schedule() just before actually doing the switch_to */
@@ -149,14 +149,14 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,* might be invalid at points where we still need to derefer * the pgd. */ - current_pgd = next->pgd; + current_pgd[smp_processor_id ()] = next->pgd;/* We don't have context support implemented, so flush all * entries belonging to previous map */ if (prev != next) -flush_tlb_mm (prev); +local_flush_tlb_mm (prev); }
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 8/14 openrisc: fix initial preempt state for secondary cpu tasks
In reply to Stafford HorneDuring SMP testing we were getting the below warning after booting the secondary cpu:
[ 0.060000] BUG: scheduling while atomic: swapper/1/0/0x00000000
This change follows similar patterns from other architectures to start the schduler with preempt disabled.
--- arch/openrisc/include/asm/thread_info.h | 2 +- arch/openrisc/kernel/smp.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
arch/openrisc/include/asm/thread_info.h +1 -1
@@ -74,7 +74,7 @@ struct thread_info { .task = &tsk, \ .flags = 0, \ .cpu = 0, \ - .preempt_count = 1, \ + .preempt_count = INIT_PREEMPT_COUNT, \ .addr_limit = KERNEL_DS, \ .ksp = 0, \ }
arch/openrisc/kernel/smp.c +1 -0
@@ -128,6 +128,7 @@ asmlinkage __init void secondary_start_kernel(void)local_irq_enable (); +preempt_disable ();/* * OK, it's off to the idle thread for us */
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 9/14 openrisc: sleep instead of spin on secondary wait
In reply to Stafford HorneCurrently we do a spin on secondary cpus when waiting to boot. This theoretically causes issues with power consumption and does cause issues with qemu cycle burning (it starves cpu 0 from actually being able to boot.)
This change puts each secondary cpu to sleep if they have a power management unit, then signals them to wake via IPI when its time to boot. If the cpus have no power management unit they will loop as before.
Note: The wakeup IPI requires a special interrupt handler as on secondary cpu's the interrupt infrastructure is not yet established. This interrupt handler is set and reset by updating SPR_EVBAR.
---
Changes since v1
- Check if power management exists before sleeping
arch/openrisc/kernel/head.S | 51 +++++++++++++++++++++++++++++++++++++++++++-- arch/openrisc/kernel/smp.c | 5 +++++ 2 files changed, 54 insertions(+), 2 deletions(-)
arch/openrisc/kernel/head.S +49 -2
@@ -712,9 +712,45 @@ _flush_tlb: #ifdef CONFIG_SMP secondary_wait: + /* Doze the cpu until we are asked to run */ + /* If we dont have power management skip doze */ + l.mfspr r25,r0,SPR_UPR + l.andi r25,r25,SPR_UPR_PMP + l.sfeq r25,r0 + l.bf secondary_check_release + l.nop + + /* Setup special secondary exception handler */ + LOAD_SYMBOL_2_GPR(r3, _secondary_evbar) + tophys(r25,r3) + l.mtspr r0,r25,SPR_EVBAR + + /* Enable Interrupts */ + l.mfspr r25,r0,SPR_SR + l.ori r25,r25,SPR_SR_IEE + l.mtspr r0,r25,SPR_SR + + /* Unmask interrupts interrupts */ + l.mfspr r25,r0,SPR_PICMR + l.ori r25,r25,0xffff + l.mtspr r0,r25,SPR_PICMR + + /* Doze */ + l.mfspr r25,r0,SPR_PMR + LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME) + l.or r25,r25,r3 + l.mtspr r0,r25,SPR_PMR + + /* Wakeup - Restore exception handler */ + l.mtspr r0,r0,SPR_EVBAR + +secondary_check_release: + /* + * Check if we actually got the release signal, if not go-back to + * sleep. + */ l.mfspr r25,r0,SPR_COREID - l.movhi r3,hi(secondary_release) - l.ori r3,r3,lo(secondary_release) + LOAD_SYMBOL_2_GPR(r3, secondary_release) tophys(r4, r3) l.lwz r3,0(r4) l.sfeq r25,r3
@@ -1663,6 +1699,17 @@ ENTRY(_early_uart_init) l.jr r9 l.nop + .align 0x1000 + .global _secondary_evbar +_secondary_evbar: + + .space 0x800 + /* Just disable interrupts and Return */ + l.ori r3,r0,SPR_SR_SM + l.mtspr r0,r3,SPR_ESR_BASE + l.rfe + + .section .rodata _string_unhandled_exception: .string "\n\rRunarunaround: Unhandled exception 0x\0"
arch/openrisc/kernel/smp.c +5 -0
@@ -26,6 +26,7 @@ unsigned long secondary_release = -1;struct thread_info *secondary_thread_info;enum ipi_msg_type { +IPI_WAKEUP ,IPI_RESCHEDULE ,IPI_CALL_FUNC ,IPI_CALL_FUNC_SINGLE ,
@@ -42,6 +43,7 @@ static void boot_secondary(unsigned int cpu, struct task_struct *idle)spin_lock (&boot_lock); secondary_release = cpu; +smp_cross_call (cpumask_of (cpu),IPI_WAKEUP );/* * now the secondary core is starting up let it run its
@@ -140,6 +142,9 @@ void handle_IPI(unsigned int ipi_msg)unsigned int cpu =smp_processor_id ();switch (ipi_msg) { +case IPI_WAKEUP : +break ; +case IPI_RESCHEDULE :scheduler_ipi ();break ;
Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 10/14 openrisc: add cacheflush support to fix icache aliasing
In reply to Stafford HorneFrom: Jan Henrik Weinstock <[email protected]>
On OpenRISC the icache does not snoop data stores. This can cause aliasing as reported by Jan. This patch fixes the issue to ensure icache is properly synchronized when code is written to memory. It supports both SMP and UP flushing.
This supports dcache flush as well for architectures that do not support write-through caches; most OpenRISC implementations do implement write-through cache however. Dcache flushes are done only on a single core as OpenRISC dcaches all support snooping of bus stores.
--- arch/openrisc/Kconfig | 11 ++++ arch/openrisc/include/asm/Kbuild | 1 - arch/openrisc/include/asm/cacheflush.h | 96 ++++++++++++++++++++++++++++++++++ arch/openrisc/include/asm/pgtable.h | 16 +++--- arch/openrisc/kernel/smp.c | 15 ++++++ arch/openrisc/mm/Makefile | 2 +- arch/openrisc/mm/cache.c | 61 +++++++++++++++++++++ 7 files changed, 194 insertions(+), 8 deletions(-) create mode 100644 arch/openrisc/include/asm/cacheflush.h create mode 100644 arch/openrisc/mm/cache.c
arch/openrisc/Kconfig +11 -0
@@ -77,6 +77,17 @@ config OR1K_1200 endchoice +config DCACHE_WRITETHROUGH + bool "Have write through data caches" + default n + help + Select this if your implementation features write through data caches. + Selecting 'N' here will allow the kernel to force flushing of data + caches at relevant times. Most OpenRISC implementations support write- + through data caches. + + If unsure say N here + config OPENRISC_BUILTIN_DTB string "Builtin DTB" default ""
arch/openrisc/include/asm/Kbuild +0 -1
@@ -1,7 +1,6 @@ generic-y += barrier.h generic-y += bug.h generic-y += bugs.h -generic-y += cacheflush.h generic-y += checksum.h generic-y += clkdev.h generic-y += current.h
arch/openrisc/include/asm/cacheflush.h new file +96 -0
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arch/openrisc/include/asm/pgtable.h +10 -6
@@ -414,15 +414,19 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)extern pgd_t swapper_pg_dir[PTRS_PER_PGD ];/* defined in head.S */ -/* -* or32 doesn't have any external MMU info: the kernel page -* tables contain all the necessary information. -* -* Actually I am not sure on what this could be used for. -*/ +static inline void update_tlb (struct vm_area_struct *vma, +unsigned long address,pte_t *pte) +{ +} + +extern void update_cache (struct vm_area_struct *vma, +unsigned long address,pte_t *pte); +static inline void update_mmu_cache (struct vm_area_struct *vma,unsigned long address,pte_t *pte) { +update_tlb (vma, address, pte); +update_cache (vma, address, pte); }/* __PHX__ FIXME, SWAP, this probably doesn't work */
arch/openrisc/kernel/smp.c +15 -0
@@ -18,6 +18,7 @@#include <asm/cpuinfo.h> #include <asm/mmu_context.h> #include <asm/tlbflush.h> +#include <asm/cacheflush.h> #include <asm/time.h> static void (*smp_cross_call)(const struct cpumask *,unsigned int );
@@ -239,3 +240,17 @@ void flush_tlb_range(struct vm_area_struct *vma, {on_each_cpu (ipi_flush_tlb_all,NULL ,1 ); } + +/* Instruction cache invalidate - performed on each cpu */ +static void ipi_icache_page_inv (void *arg) +{ +struct page *page = arg; + +local_icache_page_inv (page); +} + +void smp_icache_page_inv (struct page *page) +{ +on_each_cpu (ipi_icache_page_inv, page,1 ); +} +EXPORT_SYMBOL (smp_icache_page_inv);
arch/openrisc/mm/Makefile +1 -1
@@ -2,4 +2,4 @@ # Makefile for the linux openrisc-specific parts of the memory manager. # -obj-y := fault.o tlb.o init.o ioremap.o +obj-y := fault.o cache.o tlb.o init.o ioremap.o
arch/openrisc/mm/cache.c new file +61 -0
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Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 11/14 openrisc: add simple_smp dts and defconfig for simulators
In reply to Stafford HorneFrom: Stefan Kristiansson <[email protected]>
Simple enough to be compatible with simulation environments, such as verilated systems, QEMU and other targets supporting OpenRISC SMP. This also supports our base FPGA SoC's if the cpu frequency is upped to 50Mhz.
---
Changes since v1
- Use openrisc, prefix for ompic
- Add stdout-path
- Remove @interrupt cells
arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++ arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/openrisc/boot/dts/simple_smp.dts create mode 100644 arch/openrisc/configs/simple_smp_defconfig
arch/openrisc/boot/dts/simple_smp.dts new file +58 -0
@@ -0,0 +1,58 @@ +/dts-v1/; +/ { + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + cpu@1 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <1>; + clock-frequency = <20000000>; + }; + }; + + ompic: ompic { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic-level"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <20000000>; + }; + +};
arch/openrisc/configs/simple_smp_defconfig new file +66 -0
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Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 12/14 openrisc: support framepointers and STACKTRACE_SUPPORT
In reply to Stafford HorneFor lockdep support a reliable stack trace mechanism is needed. This patch adds support in OpenRISC for the stacktrace framework, implemented by a simple unwinder api. The unwinder api supports both framepointer and basic stack tracing.
The unwinder is now used to replace the stack_dump() implementation as well. The new traces are inline with other architectures trace format:
Call trace: [<c0004448>] show_stack+0x3c/0x58 [<c031c940>] dump_stack+0xa8/0xe4 [<c0008104>] __cpu_up+0x64/0x130 [<c000d268>] bringup_cpu+0x3c/0x178 [<c000d038>] cpuhp_invoke_callback+0xa8/0x1fc [<c000d680>] cpuhp_up_callbacks+0x44/0x14c [<c000e400>] cpu_up+0x14c/0x1bc [<c041da60>] smp_init+0x104/0x15c [<c033843c>] ? kernel_init+0x0/0x140 [<c0415e04>] kernel_init_freeable+0xbc/0x25c [<c033843c>] ? kernel_init+0x0/0x140 [<c0338458>] kernel_init+0x1c/0x140 [<c003a174>] ? schedule_tail+0x18/0xa0 [<c0006b80>] ret_from_fork+0x1c/0x9c
--- arch/openrisc/Kconfig | 4 ++ arch/openrisc/include/asm/unwinder.h | 20 +++++++ arch/openrisc/kernel/Makefile | 3 +- arch/openrisc/kernel/stacktrace.c | 86 ++++++++++++++++++++++++++++ arch/openrisc/kernel/traps.c | 54 +++--------------- arch/openrisc/kernel/unwinder.c | 105 +++++++++++++++++++++++++++++++++++ 6 files changed, 224 insertions(+), 48 deletions(-) create mode 100644 arch/openrisc/include/asm/unwinder.h create mode 100644 arch/openrisc/kernel/stacktrace.c create mode 100644 arch/openrisc/kernel/unwinder.c
arch/openrisc/Kconfig +4 -0
@@ -33,6 +33,7 @@ config OPENRISC select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS select OMPIC if SMP + select ARCH_WANT_FRAME_POINTERS config CPU_BIG_ENDIAN def_bool y
@@ -60,6 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT config GENERIC_CSUM def_bool y +config STACKTRACE_SUPPORT + def_bool y + source "init/Kconfig" source "kernel/Kconfig.freezer"
arch/openrisc/include/asm/unwinder.h new file +20 -0
@@ -0,0 +1,20 @@ +/* +* OpenRISC unwinder.h +* +* Architecture API for unwinding stacks. +* +* Copyright (C) 2017 Stafford Horne <[email protected]> +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __ASM_OPENRISC_UNWINDER_H +#define __ASM_OPENRISC_UNWINDER_H + +void unwind_stack (void *data,unsigned long *stack, +void (*trace)(void *data,unsigned long addr, +int reliable)); + +#endif /* __ASM_OPENRISC_UNWINDER_H */
arch/openrisc/kernel/Makefile +2 -1
@@ -6,9 +6,10 @@ extra-y := head.o vmlinux.lds obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ - sys_call_table.o + sys_call_table.o unwinder.o obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o
arch/openrisc/kernel/stacktrace.c new file +86 -0
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arch/openrisc/kernel/traps.c +7 -47
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arch/openrisc/kernel/unwinder.c new file +105 -0
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Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 13/14 openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
In reply to Stafford HorneLockdep is needed for proving the spinlocks and rwlocks work fine on our platform. It also requires calling the trace_hardirqs_off() and trace_hardirqs_on() pair of routines when entering and exiting an interrupt.
For OpenRISC the interrupt stack frame does not support frame pointers, so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's build up a stack frame each time.
There is one necessary small change in _sys_call_handler to move interrupt enabling later so they can get re-enabled during syscall restart. This was done to fix lockdep warnings that are now possible due to this
patch.
--- arch/openrisc/Kconfig | 3 ++ arch/openrisc/kernel/entry.S | 74 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 74 insertions(+), 3 deletions(-)
arch/openrisc/Kconfig +3 -0
@@ -64,6 +64,9 @@ config GENERIC_CSUM config STACKTRACE_SUPPORT def_bool y +config LOCKDEP_SUPPORT + def_bool y + source "init/Kconfig" source "kernel/Kconfig.freezer"
arch/openrisc/kernel/entry.S +71 -3
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Signature · 1 line
2.13.5
Stafford Horne
maintainerPATCH v2 14/14 openrisc: add tick timer multicore sync logic
In reply to Stafford HorneIn case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from the same ttcr register on each cpu.
This synchronization routine heavily borrows from mips implementation that does something similar.
---
Changes since v1
- change from timer-sync.h header to just time.h
arch/openrisc/include/asm/time.h | 8 +++ arch/openrisc/kernel/Makefile | 2 +- arch/openrisc/kernel/smp.c | 3 + arch/openrisc/kernel/sync-timer.c | 120 ++++++++++++++++++++++++++++++++++++++ arch/openrisc/kernel/time.c | 15 ++++- 5 files changed, 145 insertions(+), 3 deletions(-) create mode 100644 arch/openrisc/kernel/sync-timer.c
arch/openrisc/include/asm/time.h +8 -0
@@ -12,4 +12,12 @@extern void openrisc_clockevent_init (void ); +extern void openrisc_timer_set (unsigned long count); +extern void openrisc_timer_set_next (unsigned long delta); + +#ifdef CONFIG_SMP +extern void synchronise_count_master (int cpu); +extern void synchronise_count_slave (int cpu); +#endif +#endif /* __ASM_OR1K_TIME_H */
arch/openrisc/kernel/Makefile +1 -1
@@ -8,7 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o unwinder.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SMP) += smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_OF) += prom.o
arch/openrisc/kernel/smp.c +3 -0
@@ -100,6 +100,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)pr_crit ("CPU%u: failed to start\n" , cpu);return -EIO ; } +synchronise_count_master (cpu);return 0 ; }
@@ -129,6 +130,8 @@ asmlinkage __init void secondary_start_kernel(void)set_cpu_online (cpu, true);complete (&cpu_running); +synchronise_count_slave (cpu); +local_irq_enable ();preempt_disable ();
arch/openrisc/kernel/sync-timer.c new file +120 -0
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arch/openrisc/kernel/time.c +13 -2
@@ -27,8 +27,14 @@#include <asm/cpuinfo.h> -static int openrisc_timer_set_next_event (unsigned long delta, -struct clock_event_device *dev) +/* Test the timer ticks to count, used in sync routine */ +inline void openrisc_timer_set (unsigned long count) +{ +mtspr (SPR_TTCR , count); +} + +/* Set the timer to trigger in delta cycles */ +inline void openrisc_timer_set_next (unsigned long delta) {u32 c;
@@ -44,7 +50,12 @@ static int openrisc_timer_set_next_event(unsigned long delta,* Keep timer in continuous mode always. */ mtspr (SPR_TTMR ,SPR_TTMR_CR |SPR_TTMR_IE | c); +} +static int openrisc_timer_set_next_event (unsigned long delta, +struct clock_event_device *dev) +{ +openrisc_timer_set_next (delta);return 0 ; }
Signature · 1 line
2.13.5