ARM64: dts: marvell: armada37xx: DT fixes and enablements

I finally got a chance to spend some time with an Armada-3720-based Espressobin, and immediately faced a number of issues which would make the system of limited use for me. Fortunately, these are pretty easy to fix:

- The first patch (already posted a couple of weeks ago, and included here for completeness) fixes what is probably a copy-paste issue between GICv2 and GICv3-based platforms, where a cpu-mask is wrongly applied to PPIs.

- The following two patches add missing properties that are required for enabling virtualisation support (GIC maintenance interrupt, MMIO regions for GICv2 guest compatibility). KVM now runs correctly on this HW.

- The following patch exposes the CPUs' PMUv3, making perf work. Hey, for once it is wired correctly, without anything funky breaking the interrupt routing! Let's not miss this once in a lifetime opportunity!

- The last patch enables the USB2 interface on the Espressobin. OK, not very useful, but since it works...

This has been tested on -next as of this yesterday.

	M.

Marc Zyngier (5):
ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
ARM64: dts: marvell: armada37xx: Fix GIC maintenance interrupt
ARM64: dts: marvell: armada37xx: Enable memory-mapped GIC CPU
interface
ARM64: dts: marvell: armada37xx: Wire PMUv3
ARM64: dts: marvell: armada37xx: Enable USB2 on espressobin

 .../boot/dts/marvell/armada-3720-espressobin.dts   |  5 +++++
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi       | 23 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

2.11.0

Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult.

---
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

index b4d27857c61b..dbcc3d4e2ed5 100644
@@ -75,14 +75,10 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	soc {

2.11.0

The GIC-500 integrated in the Armada-37xx SoCs is compliant with the GICv3 architecture, and thus provides a maintenance interrupt that is required for hypervisors to function correctly.

With the interrupt provided in the DT, KVM now works as it should. Tested on an Espressobin system.

---
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
 1 file changed, 1 insertion(+)

index dbcc3d4e2ed5..506aee2e796b 100644
@@ -323,6 +323,7 @@
 				interrupt-controller;
 				reg = <0x1d00000 0x10000>, /* GICD */
 				      <0x1d40000 0x40000>; /* GICR */
+				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
 

2.11.0

The Cortex-A53s that power the Armada-37xx SoCs are equipped with a GIC CPU interface that gets enabled when coupled with a GICv3 interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables (among other things) GICv2 guests to run under a hypervisor such as KVM.

---
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

index 506aee2e796b..2dfc09501f9f 100644
@@ -322,7 +322,10 @@
 				#interrupt-cells = <3>;
 				interrupt-controller;
 				reg = <0x1d00000 0x10000>, /* GICD */
-				      <0x1d40000 0x40000>; /* GICR */
+				      <0x1d40000 0x40000>, /* GICR */
+				      <0x1d80000 0x2000>,  /* GICC */
+				      <0x1d90000 0x2000>,  /* GICH */
+				      <0x1da0000 0x20000>; /* GICV */
 				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};

2.11.0

The Cortex-A53s that power the Armada-37xx SoCs are equipped with a PMUv3, just like most ARMv8 cores.

Advertise the PMUv3 presence in the device tree, and wire its interrupt. This allows the perf subsystem to work correctly.

---
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

index 2dfc09501f9f..d6a060d9f083 100644
@@ -81,6 +81,11 @@
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;

2.11.0

The Espressobin SBC has a USB2 interface available on J8. Let's enable it.

---
 arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 5 +++++
 1 file changed, 5 insertions(+)

index e3a136ed77b0..b1af3f988b29 100644
@@ -81,6 +81,11 @@
 	status = "okay";
 };
 
+/* J8 */
+&usb2 {
+	status = "okay";
+};
+
 &mdio {
 	switch0: switch0 at 1 {
 		compatible = "marvell,mv88e6085";

2.11.0

Hi Marc,

All applied on mvebu/dt64-for-4.14

Thanks,

Gregory

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com