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ARM: OMAP2+: AM33XX: Misc fixes/updates

PATCH Superseded Vaibhav Bedia 2 participants 13 messages Jan 29, 2013

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures OMAP2+ support +3 more subsystems

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Vaibhav Bedia

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#0 lore raw

v2 cover ARM: OMAP2+: AM33XX: Misc fixes/updates

Hi,

The following patches were earlier posted as part the AM33XX suspend-resume support series [1]. Based on the suggestion from Santosh Shilimkar <[email protected]> i have split out the changes which update the various data files related to AM33XX support. This version addresses the comments received from Sergei Shtylyov and Peter Korsgaard on the earlier patchset [2].

These patches apply on top of v3.8-rc5

Regards,
Vaibhav

[1] http://marc.info/?l=linux-arm-kernel&m=135698501821074&w=2
[2] http://marc.info/?l=linux-omap&m=135849360005657&w=2

Vaibhav Bedia (9):
ARM: OMAP2+: AM33XX: CM: Get rid of unnecessary header inclusions
ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files
ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags
ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry
ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status
bit
ARM: OMAP2+: AM33XX: Update the hardreset API
ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3
ARM: OMAP2+: AM33XX: control: Add some control module registers and
APIs

 arch/arm/boot/dts/am33xx.dtsi              | 14 +++++++++
 arch/arm/mach-omap2/cm33xx.h               |  9 ++----
 arch/arm/mach-omap2/control.c              | 20 ++++++++++++
 arch/arm/mach-omap2/control.h              | 41 ++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod.c           |  5 +--
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 50 +++++++++++++++++-------------
 arch/arm/mach-omap2/prm33xx.c              | 11 ++++---
 arch/arm/mach-omap2/prm33xx.h              |  4 ++-
 8 files changed, 118 insertions(+), 36 deletions(-)
Signature · 1 line
1.8.1
author
#1 lore raw

PATCH v2 1/9 ARM: OMAP2+: AM33XX: CM: Get rid of unnecessary header inclusions

cm33xx.h unnecessarily includes a lot of header files. Get rid of these and directly include "iomap.h" which is needed to keep things compiling.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: Reword the changelog

 arch/arm/mach-omap2/cm33xx.h | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)
arch/arm/mach-omap2/cm33xx.h +1 -6
index 5fa0b62..8009e13 100644
@@ -17,16 +17,11 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
 #include "common.h"
 
 #include "cm.h"
 #include "cm-regbits-33xx.h"
-#include "cm33xx.h"
+#include "iomap.h"
 
 /* CM base address */
 #define AM33XX_CM_BASE		0x44e00000
Signature · 1 line
1.8.1
author
#2 lore raw

PATCH v2 2/9 ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files

In reply to Vaibhav Bedia

This is necessary to ensure that macros declared here can be reused from assembly files.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: No change

 arch/arm/mach-omap2/cm33xx.h  | 2 ++
 arch/arm/mach-omap2/prm33xx.h | 2 ++
 2 files changed, 4 insertions(+)
arch/arm/mach-omap2/cm33xx.h +2 -0
index 8009e13..64f4baf 100644
@@ -376,6 +376,7 @@
 #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
 
 
+#ifndef __ASSEMBLER__
 extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);

@@ -412,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
 }
 #endif
 
+#endif /* ASSEMBLER */
 #endif
arch/arm/mach-omap2/prm33xx.h +2 -0
index 3f25c56..1c40373 100644
@@ -117,6 +117,7 @@
 #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
 #define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
 
+#ifndef __ASSEMBLER__
 extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
 extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
 extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);

@@ -126,4 +127,5 @@ extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
 extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
 extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
 		u16 rstctrl_offs, u16 rstst_offs);
+#endif /* ASSEMBLER */
 #endif
Signature · 1 line
1.8.1
author
#3 lore raw

PATCH v2 3/9 ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod

In reply to Vaibhav Bedia

OCMC RAM lies in the PER power domain and this memory support retention.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: No change

 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 47 +++++++++++++++++-------------
 1 file changed, 27 insertions(+), 20 deletions(-)
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +27 -20
index 646c14d..8280f11 100644
@@ -414,7 +414,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *    - cEFUSE (doesn't fall under any ocp_if)
  *    - clkdiv32k
  *    - debugss
- *    - ocmc ram
  *    - ocp watch point
  *    - aes0
  *    - sha0

@@ -481,25 +480,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
 	},
 };
 
-/* ocmcram */
-static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
-	.name = "ocmcram",
-};
-
-static struct omap_hwmod am33xx_ocmcram_hwmod = {
-	.name		= "ocmcram",
-	.class		= &am33xx_ocmcram_hwmod_class,
-	.clkdm_name	= "l3_clkdm",
-	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-	.main_clk	= "l3_gclk",
-	.prcm		= {
-		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
-};
-
 /* ocpwp */
 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 	.name		= "ocpwp",

@@ -570,6 +550,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
 
 #endif
 
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+	.name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+	.name		= "ocmcram",
+	.class		= &am33xx_ocmcram_hwmod_class,
+	.clkdm_name	= "l3_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.main_clk	= "l3_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 	.name		= "smartreflex",

@@ -3328,6 +3327,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
 	.flags		= OCPIF_SWSUP_IDLE,
 };
 
+/* l3 main -> ocmc */
+static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
+	.master		= &am33xx_l3_main_hwmod,
+	.slave		= &am33xx_ocmcram_hwmod,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l4_fw__emif_fw,
 	&am33xx_l3_main__emif,

@@ -3398,6 +3404,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l3_main__tptc0,
 	&am33xx_l3_main__tptc1,
 	&am33xx_l3_main__tptc2,
+	&am33xx_l3_main__ocmc,
 	&am33xx_l3_s__usbss,
 	&am33xx_l4_hs__cpgmac0,
 	&am33xx_cpgmac0__mdio,
Signature · 1 line
1.8.1
author
#4 lore raw

PATCH v2 4/9 ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags

In reply to Vaibhav Bedia

Third Party Transfer Controller (TPTC0) needs to be idled and put to standby under SW control. Add the appropriate flags in the TPTC0 hwmod entry.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: Drop unnecessary parens

 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +1 -0
index 8280f11..94254e8 100644
@@ -1823,6 +1823,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
 	.class		= &am33xx_tptc_hwmod_class,
 	.clkdm_name	= "l3_clkdm",
 	.mpu_irqs	= am33xx_tptc0_irqs,
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
Signature · 1 line
1.8.1
author
#5 lore raw

PATCH v2 5/9 ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry

In reply to Vaibhav Bedia

The current HWMOD code expects the memory region with the IP's SYSCONFIG register to be marked with ADDR_TYPE_RT flag.

CPGMAC0 hwmod entry specifies two memory regions and marks both with the flag ADDR_TYPE_RT although only the 2nd region has the SYSCONFIG register. This leads to the HWMOD code accessing the wrong memory address for idle and standby operations. Fix this by removing the ADDR_TYPE_RT flag from the 1st memory region in CPGMAC0 hwmod entry.

Signed-off-by Vaibhav Bedia <[email protected]>

---
v2: No change

 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 -
 1 file changed, 1 deletion(-)
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +0 -1
index 94254e8..40bfde3 100644
@@ -2496,7 +2496,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
 	{
 		.pa_start	= 0x4a100000,
 		.pa_end		= 0x4a100000 + SZ_2K - 1,
-		.flags		= ADDR_TYPE_RT,
 	},
 	/* cpsw wr */
 	{
Signature · 1 line
1.8.1
author
#6 lore raw

PATCH v2 6/9 ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status bit

In reply to Vaibhav Bedia

WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST) Update the WKUP-M3 hwmod data to reflect the same.

Signed-off-by Vaibhav Bedia <[email protected]>

---
v2: No change

 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +1 -0
index 40bfde3..9e34d4c 100644
@@ -269,6 +269,7 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 		.omap4	= {
 			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
 			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+			.rstst_offs	= AM33XX_RM_WKUP_RSTST_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},
Signature · 1 line
1.8.1
author
#7 lore raw

PATCH v2 7/9 ARM: OMAP2+: AM33XX: Update the hardreset API

In reply to Vaibhav Bedia

WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST) Update the hardreset API to ensure that the reset line properly deasserted.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: No change

 arch/arm/mach-omap2/omap_hwmod.c |  5 +----
 arch/arm/mach-omap2/prm33xx.c    | 11 +++++++----
 arch/arm/mach-omap2/prm33xx.h    |  2 +-
 3 files changed, 9 insertions(+), 9 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +1 -4
index 4653efb..6549439 100644
@@ -3041,11 +3041,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
 static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
 				     struct omap_hwmod_rst_info *ohri)
 {
-	if (ohri->st_shift)
-		pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
-		       oh->name, ohri->name);
-
 	return am33xx_prm_deassert_hardreset(ohri->rst_shift,
+				ohri->st_shift,
 				oh->clkdm->pwrdm.ptr->prcm_offs,
 				oh->prcm.omap4.rstctrl_offs,
 				oh->prcm.omap4.rstst_offs);
arch/arm/mach-omap2/prm33xx.c +7 -4
index 1ac7388..44c0d72 100644
@@ -110,11 +110,11 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
  * of reset, or -EBUSY if the submodule did not exit reset promptly.
  */
-int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
 		u16 rstctrl_offs, u16 rstst_offs)
 {
 	int c;
-	u32 mask = 1 << shift;
+	u32 mask = 1 << st_shift;
 
 	/* Check the current status to avoid  de-asserting the line twice */
 	if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)

@@ -122,11 +122,14 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
 
 	/* Clear the reset status by writing 1 to the status bit */
 	am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
+
 	/* de-assert the reset control line */
+	mask = 1 << shift;
+
 	am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
-	/* wait the status to be set */
 
-	omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+	/* wait the status to be set */
+	omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
 							   rstst_offs),
 			  MAX_MODULE_HARDRESET_WAIT, c);
arch/arm/mach-omap2/prm33xx.h +1 -1
index 1c40373..9b9918d 100644
@@ -125,7 +125,7 @@ extern void am33xx_prm_global_warm_sw_reset(void);
 extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
 		u16 rstctrl_offs);
 extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
-extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
 		u16 rstctrl_offs, u16 rstst_offs);
 #endif /* ASSEMBLER */
 #endif
Signature · 1 line
1.8.1
author
#8 lore raw

PATCH v2 8/9 ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3

In reply to Vaibhav Bedia

Since AM33XX supports only DT-boot, this is needed for the appropriate device nodes to be created.

Note: OCMC RAM is part of the PER power domain and supports retention. The assembly code for low power entry/exit will run from OCMC RAM. To ensure that the OMAP PM code does not attempt to disable the clock to OCMC RAM as part of the suspend process add the no_idle_on_suspend flag.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: Add reg property

 arch/arm/boot/dts/am33xx.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm/boot/dts/am33xx.dtsi +14 -0
index c2f14e8..423f898 100644
@@ -385,5 +385,19 @@
 				mac-address = [ 00 00 00 00 00 00 ];
 			};
 		};
+
+		ocmcram: ocmcram at 40300000 {
+			compatible = "ti,ocmcram";
+			reg = <0x40300000 0x10000>;
+			ti,hwmods = "ocmcram";
+			ti,no_idle_on_suspend;
+		};
+
+		wkup_m3: wkup_m3 at 44d00000 {
+			compatible = "ti,wkup_m3";
+			reg = <0x44d00000 0x4000	/* M3 UMEM */
+			       0x44d80000 0x2000>;	/* M3 DMEM */
+			ti,hwmods = "wkup_m3";
+		};
 	};
 };
Signature · 1 line
1.8.1
#9 lore raw

PATCH v2 8/9 ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3

Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line

"Vaibhav" == Vaibhav Bedia <[email protected]> writes:

Vaibhav> Since AM33XX supports only DT-boot, this is needed Vaibhav> for the appropriate device nodes to be created.

Vaibhav> Note: OCMC RAM is part of the PER power domain and supports Vaibhav> retention. The assembly code for low power entry/exit will Vaibhav> run from OCMC RAM. To ensure that the OMAP PM code does not Vaibhav> attempt to disable the clock to OCMC RAM as part of the Vaibhav> suspend process add the no_idle_on_suspend flag.

Vaibhav> Signed-off-by: Vaibhav Bedia <[email protected]> Vaibhav> Acked-by: Santosh Shilimkar <[email protected]> Vaibhav> ---
Vaibhav> v2: Add reg property

 Vaibhav>  arch/arm/boot/dts/am33xx.dtsi | 14 +++++++++++++

Vaibhav> 1 file changed, 14 insertions(+)

Vaibhav> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi Vaibhav> index c2f14e8..423f898 100644
Vaibhav> --- a/arch/arm/boot/dts/am33xx.dtsi
Vaibhav> +++ b/arch/arm/boot/dts/am33xx.dtsi
Vaibhav> @@ -385,5 +385,19 @@

 Vaibhav>  				mac-address = [ 00 00 00 00 00 00 ];
 Vaibhav>  			};
 Vaibhav>  		};

Vaibhav> +
Vaibhav> + ocmcram: ocmcram at 40300000 {
Vaibhav> + compatible = "ti,ocmcram";
Vaibhav> + reg = <0x40300000 0x10000>;
Vaibhav> + ti,hwmods = "ocmcram";
Vaibhav> + ti,no_idle_on_suspend;
Vaibhav> + };
Vaibhav> +
Vaibhav> + wkup_m3: wkup_m3 at 44d00000 {
Vaibhav> + compatible = "ti,wkup_m3";

Both of these compatible properties should probably use less generic names, like:

ti,am3352-ocmcram
ti,am3352-wkup-m3 ('-' instead of '_')

Signature · 1 line
Bye, Peter Korsgaard
author
#10 lore raw

PATCH v2 8/9 ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3

Quoted 39 lines · Peter Korsgaard
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line

"Vaibhav" == Vaibhav Bedia <[email protected]> writes:

Vaibhav> Since AM33XX supports only DT-boot, this is needed Vaibhav> for the appropriate device nodes to be created.

Vaibhav> Note: OCMC RAM is part of the PER power domain and supports Vaibhav> retention. The assembly code for low power entry/exit will Vaibhav> run from OCMC RAM. To ensure that the OMAP PM code does not Vaibhav> attempt to disable the clock to OCMC RAM as part of the Vaibhav> suspend process add the no_idle_on_suspend flag.

Vaibhav> Signed-off-by: Vaibhav Bedia <[email protected]> Vaibhav> Acked-by: Santosh Shilimkar <[email protected]> Vaibhav> ---
Vaibhav> v2: Add reg property

 Vaibhav>  arch/arm/boot/dts/am33xx.dtsi | 14 +++++++++++++

Vaibhav> 1 file changed, 14 insertions(+)

Vaibhav> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi Vaibhav> index c2f14e8..423f898 100644
Vaibhav> --- a/arch/arm/boot/dts/am33xx.dtsi
Vaibhav> +++ b/arch/arm/boot/dts/am33xx.dtsi
Vaibhav> @@ -385,5 +385,19 @@

 Vaibhav>  				mac-address = [ 00 00 00 00 00 00 ];
 Vaibhav>  			};
 Vaibhav>  		};

Vaibhav> +
Vaibhav> + ocmcram: ocmcram at 40300000 {
Vaibhav> + compatible = "ti,ocmcram";
Vaibhav> + reg = <0x40300000 0x10000>;
Vaibhav> + ti,hwmods = "ocmcram";
Vaibhav> + ti,no_idle_on_suspend;
Vaibhav> + };
Vaibhav> +
Vaibhav> + wkup_m3: wkup_m3 at 44d00000 {
Vaibhav> + compatible = "ti,wkup_m3";

Quoted 6 lines

Both of these compatible properties should probably use less generic names, like:

ti,am3352-ocmcram
ti,am3352-wkup-m3 ('-' instead of '_')

Ok. Will do.

Thanks,
Vaibhav

author
#11 lore raw

PATCH v2 9/9 ARM: OMAP2+: AM33XX: control: Add some control module registers and APIs

In reply to Vaibhav Bedia

Add minimal APIs for writing to the IPC and the M3_TXEV registers in the Control module. These will be used in a subsequent patch which adds suspend-resume support for AM33XX.

Signed-off-by Vaibhav Bedia <[email protected]>
Acked-by Santosh Shilimkar <[email protected]>

---
v2: No change

 arch/arm/mach-omap2/control.c | 20 ++++++++++++++++++++
 arch/arm/mach-omap2/control.h | 41 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+)
arch/arm/mach-omap2/control.c +20 -0
index 2adb268..c5d54ae 100644
@@ -604,3 +604,23 @@ int omap3_ctrl_save_padconf(void)
 }
 
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+
+#if defined(CONFIG_SOC_AM33XX) && defined(CONFIG_PM)
+void am33xx_txev_eoi(void)
+{
+	omap_ctrl_writel(AM33XX_M3_TXEV_ACK, AM33XX_CONTROL_M3_TXEV_EOI);
+}
+
+void am33xx_txev_enable(void)
+{
+	omap_ctrl_writel(AM33XX_M3_TXEV_ENABLE, AM33XX_CONTROL_M3_TXEV_EOI);
+}
+
+void am33xx_wkup_m3_ipc_cmd(struct am33xx_ipc_data *data)
+{
+	omap_ctrl_writel(data->resume_addr, AM33XX_CONTROL_IPC_MSG_REG0);
+	omap_ctrl_writel(data->sleep_mode, AM33XX_CONTROL_IPC_MSG_REG1);
+	omap_ctrl_writel(data->param1, AM33XX_CONTROL_IPC_MSG_REG2);
+	omap_ctrl_writel(data->param2, AM33XX_CONTROL_IPC_MSG_REG3);
+}
+#endif /* CONFIG_SOC_AM33XX && CONFIG_PM */
arch/arm/mach-omap2/control.h +41 -0

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1.8.1
#12 lore raw

v2 cover ARM: OMAP2+: AM33XX: Misc fixes/updates

In reply to Vaibhav Bedia
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"Vaibhav" == Vaibhav Bedia <[email protected]> writes:

Vaibhav> Hi,
Vaibhav> The following patches were earlier posted as part the AM33XX Vaibhav> suspend-resume support series [1]. Based on the suggestion Vaibhav> from Santosh Shilimkar <[email protected]> i have split Vaibhav> out the changes which update the various data files related Vaibhav> to AM33XX support. This version addresses the comments Vaibhav> received from Sergei Shtylyov and Peter Korsgaard on the earlier Vaibhav> patchset [2].

Vaibhav> These patches apply on top of v3.8-rc5

Besides the dt compatible property names in patch 8, this series looks good to me:

Acked-by Peter Korsgaard <[email protected]>
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Bye, Peter Korsgaard