drm/i915: consider the source max DP lane count too

1/3

---
 drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)
index 104998e..19537a6 100644
@@ -120,6 +120,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	return max_link_bw;
 }
 
+static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	u8 source_max, sink_max;
+
+	source_max = 4;
+	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
+	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
+		source_max = 2;
+
+	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+
+	return min(source_max, sink_max);
+}
+
 /*
  * The units on the numbers in the next two are... bizarre.  Examples will
  * make it clearer; this one parallels an example in the eDP spec.

@@ -170,7 +186,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	}
 
 	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
-	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+	max_lanes = intel_dp_max_lane_count(intel_dp);
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);

@@ -764,7 +780,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_crtc *intel_crtc = encoder->new_crtc;
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
-	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+	int max_lane_count = intel_dp_max_lane_count(intel_dp);
 	/* Conveniently, the link BW constants become indices with a shift...*/
 	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;

1.9.0
---
 drivers/gpu/drm/i915/intel_dp.c | 94 +++++++++++++++++++++++++++--------------
 1 file changed, 63 insertions(+), 31 deletions(-)
index 19537a6..884166b 100644
@@ -768,6 +768,52 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 }
 
+static bool link_config_is_possible(int mode_rate, int lanes, int bw)
+{
+	int link_clock, link_avail;
+
+	link_clock = drm_dp_bw_code_to_link_rate(bw);
+	link_avail = intel_dp_max_data_rate(link_clock, lanes);
+
+	DRM_DEBUG_KMS("DP link avail with 0x%x bw and %d lanes: %d. Required: %d (%d%%)\n",
+		      bw, lanes, link_avail, mode_rate,
+		      mode_rate * 100 / link_avail);
+
+	return (mode_rate <= link_avail);
+}
+
+/*
+ * This function tries to find the minimal number of lanes and BW required based
+ * on the parameters given. If not possible, it returns false.
+ */
+static bool intel_dp_compute_link_config(int mode_clock, int bpp,
+					 int min_lanes, int max_lanes,
+					 int min_bw, int max_bw,
+					 int *lanes_used, int *bw_used)
+{
+	/* Conveniently, the link BW constants become indices with a shift...*/
+	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
+	int min_bw_index = min_bw >> 3;
+	int max_bw_index = max_bw >> 3;
+	int mode_rate;
+	int lanes, bw_it;
+
+	mode_rate = intel_dp_link_required(mode_clock, bpp);
+
+	for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+		for (bw_it = min_bw_index; bw_it <= max_bw_index; bw_it++)
+			if (link_config_is_possible(mode_rate, lanes,
+						    bws[bw_it]))
+				goto found;
+
+	return false;
+
+found:
+	*lanes_used = lanes;
+	*bw_used = bws[bw_it];
+	return true;
+}
+
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_config *pipe_config)

@@ -779,13 +825,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	enum port port = dp_to_dig_port(intel_dp)->port;
 	struct intel_crtc *intel_crtc = encoder->new_crtc;
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
-	int lane_count, clock;
+	int lanes_used, bw_used;
 	int max_lane_count = intel_dp_max_lane_count(intel_dp);
-	/* Conveniently, the link BW constants become indices with a shift...*/
-	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
-	int bpp, mode_rate;
-	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
-	int link_avail, link_clock;
+	int max_bw = intel_dp_max_link_bw(intel_dp);
+	int bpp;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;

@@ -808,7 +851,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
 		      "max bw %02x pixel clock %iKHz\n",
-		      max_lane_count, bws[max_clock],
+		      max_lane_count, max_bw,
 		      adjusted_mode->crtc_clock);
 
 	/* Walk through all bpp values. Luckily they're all nicely spaced with 2

@@ -821,26 +864,17 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		bpp = dev_priv->vbt.edp_bpp;
 	}
 
-	for (; bpp >= 6*3; bpp -= 2*3) {
-		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
-						   bpp);
-
-		for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
-			for (clock = 0; clock <= max_clock; clock++) {
-				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
-				link_avail = intel_dp_max_data_rate(link_clock,
-								    lane_count);
-
-				if (mode_rate <= link_avail) {
-					goto found;
-				}
-			}
-		}
-	}
+	for (; bpp >= 6*3; bpp -= 2*3)
+		if (intel_dp_compute_link_config(adjusted_mode->crtc_clock, bpp,
+						 1, max_lane_count,
+						 DP_LINK_BW_1_62,
+						 max_bw,
+						 &lanes_used, &bw_used))
+			break;
 
-	return false;
+	if (bpp < 6*3)
+		return false;
 
-found:
 	if (intel_dp->color_range_auto) {
 		/*
 		 * See:

@@ -856,25 +890,23 @@ found:
 	if (intel_dp->color_range)
 		pipe_config->limited_color_range = true;
 
-	intel_dp->link_bw = bws[clock];
-	intel_dp->lane_count = lane_count;
+	intel_dp->link_bw = bw_used;
+	intel_dp->lane_count = lanes_used;
 	pipe_config->pipe_bpp = bpp;
 	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 
 	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 		      intel_dp->link_bw, intel_dp->lane_count,
 		      pipe_config->port_clock, bpp);
-	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
-		      mode_rate, link_avail);
 
-	intel_link_compute_m_n(bpp, lane_count,
+	intel_link_compute_m_n(bpp, lanes_used,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n);
 
 	if (intel_connector->panel.downclock_mode != NULL &&
 		intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
-			intel_link_compute_m_n(bpp, lane_count,
+			intel_link_compute_m_n(bpp, lanes_used,
 				intel_connector->panel.downclock_mode->clock,
 				pipe_config->port_clock,
 				&pipe_config->dp_m2_n2);

1.9.0
---
 drivers/gpu/drm/i915/i915_drv.h    |  1 +
 drivers/gpu/drm/i915/i915_params.c |  8 ++++++++
 drivers/gpu/drm/i915/intel_dp.c    | 39 ++++++++++++++++++++++++++++++++++----
 3 files changed, 44 insertions(+), 4 deletions(-)
index 7d6acb4..d5ae8dc 100644
@@ -1941,6 +1941,7 @@ struct i915_params {
 	bool reset;
 	bool disable_display;
 	bool disable_vtd_wa;
+	int dp_link_train_policy;
 };
 extern struct i915_params i915 __read_mostly;
 

index d05a2af..8c358e7 100644
@@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = {
 	.disable_display = 0,
 	.enable_cmd_parser = 1,
 	.disable_vtd_wa = 0,
+	.dp_link_train_policy = 0,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);

@@ -156,3 +157,10 @@ MODULE_PARM_DESC(disable_vtd_wa, "Disable all VT-d workarounds (default: false)"
 module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
 MODULE_PARM_DESC(enable_cmd_parser,
 		 "Enable command parsing (1=enabled [default], 0=disabled)");
+
+module_param_named(dp_link_train_policy, i915.dp_link_train_policy, int, 0600);
+MODULE_PARM_DESC(dp_link_train_policy,
+	"Choose strategy for DP link training "
+	"(0=narrow and fast [default], 1=wide and slow. For other values, "
+	"bits 11:8 are for the BW and bits 7:4 are for the nubmer of lanes, "
+	"check intel_dp_compute_link_config() for more details.)");

index 884166b..25f7e1c 100644
@@ -800,11 +800,42 @@ static bool intel_dp_compute_link_config(int mode_clock, int bpp,
 
 	mode_rate = intel_dp_link_required(mode_clock, bpp);
 
-	for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+	switch (i915.dp_link_train_policy) {
+	case 0: /* Narrow and fast. */
+		for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+			for (bw_it = min_bw_index; bw_it <= max_bw_index;
+			     bw_it++)
+				if (link_config_is_possible(mode_rate, lanes,
+							    bws[bw_it]))
+					goto found;
+	case 1: /* Wide and slow. */
 		for (bw_it = min_bw_index; bw_it <= max_bw_index; bw_it++)
-			if (link_config_is_possible(mode_rate, lanes,
-						    bws[bw_it]))
-				goto found;
+			for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+				if (link_config_is_possible(mode_rate, lanes,
+							    bws[bw_it]))
+					goto found;
+	default: /* Bits 11:8 contain the index of the bws array.
+		  * Bits 7:4 contain the number of lanes.
+		  * Example: i915.dp_link_train_policy=0x140 uses
+		  * DP_LINK_BW_2_7 and 4 lanes. */
+		bw_it = (i915.dp_link_train_policy >> 8) & 0xF;
+		lanes = (i915.dp_link_train_policy >> 4) & 0xF;
+
+		if (bw_it < min_bw_index || bw_it > max_bw_index) {
+			DRM_ERROR("Invalid BW index\n");
+			return false;
+		}
+
+		if (lanes < min_lanes || lanes > max_lanes ||
+		    /* Not a power of two. */
+		    !(lanes != 0 && (lanes & (lanes - 1)) == 0)) {
+			DRM_ERROR("Invalid number of lanes.\n");
+			return false;
+		}
+
+		if (link_config_is_possible(mode_rate, lanes, bws[bw_it]))
+			goto found;
+	}
 
 	return false;
 

1.9.0
---
 drivers/gpu/drm/i915/i915_drv.h    |  1 +
 drivers/gpu/drm/i915/i915_params.c |  8 ++++++++
 drivers/gpu/drm/i915/intel_dp.c    | 39 ++++++++++++++++++++++++++++++++++----
 3 files changed, 44 insertions(+), 4 deletions(-)
index 7d6acb4..d5ae8dc 100644

@@ -1941,6 +1941,7 @@ struct i915_params {
 	bool reset;
 	bool disable_display;
 	bool disable_vtd_wa;
+	int dp_link_train_policy;

 };
 extern struct i915_params i915 __read_mostly;
 

index d05a2af..8c358e7 100644
@@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = {
 	.disable_display = 0,
 	.enable_cmd_parser = 1,
 	.disable_vtd_wa = 0,
+	.dp_link_train_policy = 0,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);

@@ -156,3 +157,10 @@ MODULE_PARM_DESC(disable_vtd_wa, "Disable all VT-d workarounds (default: false)"
 module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
 MODULE_PARM_DESC(enable_cmd_parser,
 		 "Enable command parsing (1=enabled [default], 0=disabled)");
+
+module_param_named(dp_link_train_policy, i915.dp_link_train_policy, int, 0600);
+MODULE_PARM_DESC(dp_link_train_policy,
+	"Choose strategy for DP link training "
+	"(0=narrow and fast [default], 1=wide and slow. For other values, "
+	"bits 11:8 are for the BW and bits 7:4 are for the nubmer of lanes, "
+	"check intel_dp_compute_link_config() for more details.)");

index 884166b..25f7e1c 100644
@@ -800,11 +800,42 @@ static bool intel_dp_compute_link_config(int mode_clock, int bpp,
 
 	mode_rate = intel_dp_link_required(mode_clock, bpp);
 
-	for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+	switch (i915.dp_link_train_policy) {
+	case 0: /* Narrow and fast. */
+		for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+			for (bw_it = min_bw_index; bw_it <= max_bw_index;
+			     bw_it++)
+				if (link_config_is_possible(mode_rate, lanes,
+							    bws[bw_it]))
+					goto found;
+	case 1: /* Wide and slow. */
 		for (bw_it = min_bw_index; bw_it <= max_bw_index; bw_it++)
-			if (link_config_is_possible(mode_rate, lanes,
-						    bws[bw_it]))
-				goto found;
+			for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1)
+				if (link_config_is_possible(mode_rate, lanes,
+							    bws[bw_it]))
+					goto found;
+	default: /* Bits 11:8 contain the index of the bws array.
+		  * Bits 7:4 contain the number of lanes.
+		  * Example: i915.dp_link_train_policy=0x140 uses
+		  * DP_LINK_BW_2_7 and 4 lanes. */
+		bw_it = (i915.dp_link_train_policy >> 8) & 0xF;
+		lanes = (i915.dp_link_train_policy >> 4) & 0xF;
+
+		if (bw_it < min_bw_index || bw_it > max_bw_index) {
+			DRM_ERROR("Invalid BW index\n");
+			return false;
+		}
+
+		if (lanes < min_lanes || lanes > max_lanes ||
+		    /* Not a power of two. */
+		    !(lanes != 0 && (lanes & (lanes - 1)) == 0)) {
+			DRM_ERROR("Invalid number of lanes.\n");
+			return false;
+		}
+
+		if (link_config_is_possible(mode_rate, lanes, bws[bw_it]))
+			goto found;
+	}
 
 	return false;
 

1.9.0

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
Jani Nikula, Intel Open Source Technology Center
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
Jani Nikula, Intel Open Source Technology Center
Paulo Zanoni
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
---
 drivers/gpu/drm/i915/i915_drv.h    |  1 +
 drivers/gpu/drm/i915/i915_params.c |  8 ++++++++
 drivers/gpu/drm/i915/intel_dp.c    | 39
++++++++++++++++++++++++++++++++++----
 3 files changed, 44 insertions(+), 4 deletions(-)
@@ -1941,6 +1941,7 @@ struct i915_params {
 	bool reset;
 	bool disable_display;
 	bool disable_vtd_wa;
+	int dp_link_train_policy;
 };
 extern struct i915_params i915 __read_mostly;
 

index d05a2af..8c358e7 100644
@@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = {
 	.disable_display = 0,
 	.enable_cmd_parser = 1,
 	.disable_vtd_wa = 0,
+	.dp_link_train_policy = 0,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400); @@ -156,3
+157,10 @@ MODULE_PARM_DESC(disable_vtd_wa, "Disable all VT-d

+
+module_param_named(dp_link_train_policy, i915.dp_link_train_policy,
+int, 0600); MODULE_PARM_DESC(dp_link_train_policy,
+	"Choose strategy for DP link training "
+	"(0=narrow and fast [default], 1=wide and slow. For other values, "
+	"bits 11:8 are for the BW and bits 7:4 are for the nubmer of lanes, "
+	"check intel_dp_compute_link_config() for more details.)");

---
 drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)
index 104998e..19537a6 100644
@@ -120,6 +120,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	return max_link_bw;
 }
 

+static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	u8 source_max, sink_max;
+
+	source_max = 4;
+	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
+	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
+		source_max = 2;

+
+	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+
+	return min(source_max, sink_max);
+}
+
 /*
  * The units on the numbers in the next two are... bizarre.  Examples will
  * make it clearer; this one parallels an example in the eDP spec.

@@ -170,7 +186,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	}
 
 	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
-	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+	max_lanes = intel_dp_max_lane_count(intel_dp);
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);

@@ -764,7 +780,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_crtc *intel_crtc = encoder->new_crtc;
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
-	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+	int max_lane_count = intel_dp_max_lane_count(intel_dp);
 	/* Conveniently, the link BW constants become indices with a shift...*/
 	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;

1.9.0

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jani Nikula, Intel Open Source Technology Center

drm/i915: consider the source max DP lane count too

Paulo Zanoni

Paulo Zanoni

Paulo Zanoni

Daniel Vetter

Daniel Vetter

Jani Nikula

Daniel Vetter

Jani Nikula

Barbalho, Rafael

Paulo Zanoni

Daniel Vetter

Barbalho, Rafael

Jani Nikula