Enable NAND on Armada-7040-DB board

PATCH New Miquel Raynal 3 participants 7 messages Sep 25, 2017 – Oct 12, 2017

Subsystems (4)

Device tree bindings Memory technology devices (MTD) NAND flash Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support

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Miquel Raynal

author

2017-09-25 14:53 UTC #0 lore raw

cover Enable NAND on Armada-7040-DB board

Hi,

This series adds support for NAND on Armada-7040-DB board.

Besides standard NAND node addition, it also introduces a new compatible string for the pxa3xx_nand driver to support the subitilities of A7k/A8k SoCs, as well as a new property used by the pxa3xx_nand driver to grab a phandle on the system control node in order to enable the NAND controller itself.

Regards,
Miquel

Gregory CLEMENT (1):
arm64: dts: marvell: add NAND support on the 7040-DB board

Miquel Raynal (2):
Documentation: devicetree: add pxa3xx compatible and syscon property
mtd: nand: pxa3xx: enable NAND controller if the SoC needs it

 .../devicetree/bindings/mtd/pxa3xx-nand.txt        |  4 +++
 arch/arm64/boot/dts/marvell/armada-7040-db.dts     | 24 +++++++++++++
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       | 14 ++++++++
 .../boot/dts/marvell/armada-cp110-master.dtsi      |  3 +-
 drivers/mtd/nand/pxa3xx_nand.c                     | 41 +++++++++++++++++++---
 5 files changed, 81 insertions(+), 5 deletions(-)

Signature · 1 line

2.11.0

Miquel Raynal

author

2017-09-25 14:53 UTC #1 lore raw

PATCH 1/3 Documentation: devicetree: add pxa3xx compatible and syscon property

Document the new pxa3xx_nand driver compatible string for A7k/A8k SoCs that need to access system controller registers in order to enable the NAND controller through the use of a phandle pointed to by the 'marvell,system-controller' property.

Signed-off-by Miquel Raynal <[email protected]>

---
 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 4 ++++
 1 file changed, 4 insertions(+)

Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt +4 -0

index d9b655f11048..d4ee4da58463 100644
@@ -5,9 +5,13 @@ Required properties:
  - compatible:		Should be set to one of the following:
 			marvell,pxa3xx-nand
 			marvell,armada370-nand
+			marvell,armada-8k-nand
  - reg: 		The register base for the controller
  - interrupts:		The interrupt to map
  - #address-cells:	Set to <1> if the node includes partitions
+ - marvell,system-controller: Set to retrieve the syscon node that handles
+			NAND controller related registers (only required
+			with marvell,armada-8k-nand compatible).
 
 Optional properties:

Signature · 1 line

2.11.0

Miquel Raynal

author

2017-09-25 14:53 UTC #2 lore raw

PATCH 2/3 mtd: nand: pxa3xx: enable NAND controller if the SoC needs it

In reply to Miquel Raynal

Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices.

This change is needed to stay bootloader independent.

Signed-off-by Miquel Raynal <[email protected]>

---
 drivers/mtd/nand/pxa3xx_nand.c | 41 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)

drivers/mtd/nand/pxa3xx_nand.c +37 -4

index 85cff68643e0..90b9a9ccbe60 100644
@@ -30,6 +30,8 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/platform_data/mtd-nand-pxa3xx.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #define	CHIP_DELAY_TIMEOUT	msecs_to_jiffies(200)
 #define NAND_STOP_DELAY		msecs_to_jiffies(40)

@@ -45,6 +47,10 @@
  */
 #define INIT_BUFFER_SIZE	2048
 
+/* System control register and bit to enable NAND on some SoCs */
+#define GENCONF_SOC_DEVICE_MUX	0x208
+#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
+
 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
 #define NDTR0CS0	(0x04) /* Timing Parameter 0 for CS0 */

@@ -174,6 +180,7 @@ enum {
 enum pxa3xx_nand_variant {
 	PXA3XX_NAND_VARIANT_PXA,
 	PXA3XX_NAND_VARIANT_ARMADA370,
+	PXA3XX_NAND_VARIANT_ARMADA_8K,
 };
 
 struct pxa3xx_nand_host {

@@ -425,6 +432,10 @@ static const struct of_device_id pxa3xx_nand_dt_ids[] = {
 		.compatible = "marvell,armada370-nand",
 		.data       = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
 	},
+	{
+		.compatible = "marvell,armada-8k-nand",
+		.data       = (void *)PXA3XX_NAND_VARIANT_ARMADA_8K,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);

@@ -825,7 +836,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 		info->retcode = ERR_UNCORERR;
 	if (status & NDSR_CORERR) {
 		info->retcode = ERR_CORERR;
-		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
+		if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+		     info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
 		    info->ecc_bch)
 			info->ecc_err_cnt = NDSR_ERR_CNT(status);
 		else

@@ -888,7 +900,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 		nand_writel(info, NDCB0, info->ndcb2);
 
 		/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
-		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
+		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+		    info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}

@@ -1671,7 +1684,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
 		chip->options |= NAND_BUSWIDTH_16;
 
 	/* Device detection must be done with ECC disabled */
-	if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
+	if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+	    info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
 		nand_writel(info, NDECCCTRL, 0x0);
 
 	if (pdata->flash_bbt)

@@ -1709,7 +1723,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
 	 * (aka splitted) command handling,
 	 */
 	if (mtd->writesize > PAGE_CHUNK_SIZE) {
-		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
+		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+		    info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
 			chip->cmdfunc = nand_cmdfunc_extended;
 		} else {
 			dev_err(&info->pdev->dev,

@@ -1928,6 +1943,24 @@ static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
 	if (!of_id)
 		return 0;
 
+	/*
+	 * Some SoCs like A7k/A8k need to enable manually the NAND
+	 * controller to avoid being bootloader dependent. This is done
+	 * through the use of a single bit in the System Functions registers.
+	 */
+	if (pxa3xx_nand_get_variant(pdev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {
+		struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(
+			pdev->dev.of_node, "marvell,system-controller");
+		u32 reg;
+
+		if (IS_ERR(sysctrl_base))
+			return PTR_ERR(sysctrl_base);
+
+		regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
+		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
+		regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
+	}
+
 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 	if (!pdata)
 		return -ENOMEM;

Signature · 1 line

2.11.0

Miquel Raynal

author

2017-09-25 14:53 UTC #3 lore raw

PATCH 3/3 arm64: dts: marvell: add NAND support on the 7040-DB board

In reply to Miquel Raynal

From: Gregory CLEMENT <[email protected]>

The NAND controller used in A7K/A8K is present on the CP110 master part. It is compatible with the pxa3xx_nand driver but requires the use of the marvell,armada-8k-nand compatible string due to the need to first enable the NAND controller.

Add properties to the NAND node to fit the bindings constraints of the pxa3xx_nand driver and enable the NAND controller.

Add the 'marvell,system-controller' property to the cp110 master NAND node with a reference to the syscon node. This is new compared to other boards using the pxa3xx_nand driver and it is needed to be bootloader independent and enable the NAND controller from the NAND controller driver itself by writing in these syscon registers.

Signed-off-by Gregory CLEMENT <[email protected]>

[miquel.raynal at free-electrons.com: add NAND ready/busy MPP subnode, change compatible string to fit the needs of the A7k/A8k SoCs and add the system controller property]

Signed-off-by Miquel Raynal <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts     | 24 ++++++++++++++++++++++
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       | 14 +++++++++++++
 .../boot/dts/marvell/armada-cp110-master.dtsi      |  3 ++-
 3 files changed, 40 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/marvell/armada-7040-db.dts +24 -0

index 9c3bdf87e543..b98cf265bae5 100644
@@ -144,6 +144,30 @@
 	};
 };
 
+&cpm_nand {
+	status = "okay";
+	num-cs = <1>;
+	pinctrl-0 = <&nand_pins>, <&nand_rb>;
+	pinctrl-names = "default";
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+	marvell,nand-enable-arbiter;
+	nand-on-flash-bbt;
+
+	partition at 0 {
+		label = "U-Boot";
+		reg = <0 0x200000>;
+	};
+	partition at 200000 {
+		label = "Linux";
+		reg = <0x200000 0xe00000>;
+	};
+	partition at 1000000 {
+		label = "Filesystem";
+		reg = <0x1000000 0x3f000000>;
+	};
+};
+
 &cpm_spi1 {
 	status = "okay";

arch/arm64/boot/dts/marvell/armada-70x0.dtsi +14 -0

index 860b6ae9dcc5..0e1a1e5be399 100644
@@ -64,5 +64,19 @@
 &cpm_syscon0 {
 	cpm_pinctrl: pinctrl {
 		compatible = "marvell,armada-7k-pinctrl";
+
+		nand_pins: nand-pins {
+			marvell,pins =
+			"mpp15", "mpp16", "mpp17", "mpp18",
+			"mpp19", "mpp20", "mpp21", "mpp22",
+			"mpp23", "mpp24", "mpp25", "mpp26",
+			"mpp27";
+			marvell,function = "dev";
+		};
+
+		nand_rb: nand-rb {
+			marvell,pins = "mpp13";
+			marvell,function = "nf";
+		};
 	};
 };

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +2 -1

index 8263a8a504a8..d41b41b613ec 100644
@@ -274,12 +274,13 @@
 				 * this controller is only usable on the CPM
 				 * for A7K and on the CPS for A8K.
 				 */
-				compatible = "marvell,armada370-nand";
+				compatible = "marvell,armada-8k-nand";
 				reg = <0x720000 0x54>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_clk 1 2>;
+				marvell,system-controller = <&cpm_syscon0>;
 				status = "disabled";
 			};

Signature · 1 line

2.11.0

Gregory CLEMENT

2017-09-25 15:06 UTC #4 lore raw

PATCH 3/3 arm64: dts: marvell: add NAND support on the 7040-DB board

Hi Miquel,

Quoted 91 lines · Miquel Raynal

From: Gregory CLEMENT <[email protected]>
The NAND controller used in A7K/A8K is present on the CP110 master part. It is compatible with the pxa3xx_nand driver but requires the use of the marvell,armada-8k-nand compatible string due to the need to first enable the NAND controller.
Add properties to the NAND node to fit the bindings constraints of the pxa3xx_nand driver and enable the NAND controller.
Add the 'marvell,system-controller' property to the cp110 master NAND node with a reference to the syscon node. This is new compared to other boards using the pxa3xx_nand driver and it is needed to be bootloader independent and enable the NAND controller from the NAND controller driver itself by writing in these syscon registers.
Signed-off-by Gregory CLEMENT <[email protected]>
[miquel.raynal at free-electrons.com: add NAND ready/busy MPP subnode, change compatible string to fit the needs of the A7k/A8k SoCs and add the system controller property]
Signed-off-by Miquel Raynal <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts     | 24 ++++++++++++++++++++++
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       | 14 +++++++++++++
 .../boot/dts/marvell/armada-cp110-master.dtsi      |  3 ++-
 3 files changed, 40 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/marvell/armada-7040-db.dts +24 -0
index 9c3bdf87e543..b98cf265bae5 100644
@@ -144,6 +144,30 @@
 	};
 };
 
+&cpm_nand {
+	status = "okay";
+	num-cs = <1>;
+	pinctrl-0 = <&nand_pins>, <&nand_rb>;
+	pinctrl-names = "default";
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+	marvell,nand-enable-arbiter;
+	nand-on-flash-bbt;
+
+	partition at 0 {
+		label = "U-Boot";
+		reg = <0 0x200000>;
+	};
+	partition at 200000 {
+		label = "Linux";
+		reg = <0x200000 0xe00000>;
+	};
+	partition at 1000000 {
+		label = "Filesystem";
+		reg = <0x1000000 0x3f000000>;
+	};
+};
+
 &cpm_spi1 {
 	status = "okay";
 
arch/arm64/boot/dts/marvell/armada-70x0.dtsi +14 -0
index 860b6ae9dcc5..0e1a1e5be399 100644
@@ -64,5 +64,19 @@
 &cpm_syscon0 {
 	cpm_pinctrl: pinctrl {
 		compatible = "marvell,armada-7k-pinctrl";
+
+		nand_pins: nand-pins {
+			marvell,pins =
+			"mpp15", "mpp16", "mpp17", "mpp18",
+			"mpp19", "mpp20", "mpp21", "mpp22",
+			"mpp23", "mpp24", "mpp25", "mpp26",
+			"mpp27";
+			marvell,function = "dev";
+		};
+
+		nand_rb: nand-rb {
+			marvell,pins = "mpp13";
+			marvell,function = "nf";
+		};
 	};
 };
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +0 -0
index 8263a8a504a8..d41b41b613ec 100644

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi line 277

Quoted 5 lines

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -1

@@ -274,12 +274,13 @@
 				 * this controller is only usable on the CPM
 				 * for A7K and on the CPS for A8K.
 				 */
-				compatible = "marvell,armada370-nand";
+				compatible = "marvell,armada-8k-nand";

the controller on cp110 remains compatible with the one on Armada 370 (even if it needs more initialization steps), so we should keep it also and having instead the following line:

compatible = "marvell,armada-8k-nand", "marvell,armada370-nand";

You don't have to send a new version, unless someone is against it, I will amend it when applying on the mvebu branches.

Thanks,

Gregory

Quoted 17 lines

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -0

 				reg = <0x720000 0x54>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_clk 1 2>;
+				marvell,system-controller = <&cpm_syscon0>;
 				status = "disabled";
 			};

Signature · 7 lines

2.11.0


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linux-arm-kernel at lists.infradead.org
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Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Gregory CLEMENT

2017-10-12 14:30 UTC #5 lore raw

PATCH 3/3 arm64: dts: marvell: add NAND support on the 7040-DB board

Hi Miquel,

Quoted 105 lines · Gregory CLEMENT

Hi Miquel,
Quoted 91 lines · Miquel Raynal
From: Gregory CLEMENT <[email protected]>
The NAND controller used in A7K/A8K is present on the CP110 master part. It is compatible with the pxa3xx_nand driver but requires the use of the marvell,armada-8k-nand compatible string due to the need to first enable the NAND controller.
Add properties to the NAND node to fit the bindings constraints of the pxa3xx_nand driver and enable the NAND controller.
Add the 'marvell,system-controller' property to the cp110 master NAND node with a reference to the syscon node. This is new compared to other boards using the pxa3xx_nand driver and it is needed to be bootloader independent and enable the NAND controller from the NAND controller driver itself by writing in these syscon registers.
Signed-off-by Gregory CLEMENT <[email protected]>
[miquel.raynal at free-electrons.com: add NAND ready/busy MPP subnode, change compatible string to fit the needs of the A7k/A8k SoCs and add the system controller property]
Signed-off-by Miquel Raynal <[email protected]>
---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts     | 24 ++++++++++++++++++++++
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       | 14 +++++++++++++
 .../boot/dts/marvell/armada-cp110-master.dtsi      |  3 ++-
 3 files changed, 40 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/marvell/armada-7040-db.dts +24 -0
index 9c3bdf87e543..b98cf265bae5 100644
@@ -144,6 +144,30 @@
 	};
 };
 
+&cpm_nand {
+	status = "okay";
+	num-cs = <1>;
+	pinctrl-0 = <&nand_pins>, <&nand_rb>;
+	pinctrl-names = "default";
+	nand-ecc-strength = <4>;
+	nand-ecc-step-size = <512>;
+	marvell,nand-enable-arbiter;
+	nand-on-flash-bbt;
+
+	partition at 0 {
+		label = "U-Boot";
+		reg = <0 0x200000>;
+	};
+	partition at 200000 {
+		label = "Linux";
+		reg = <0x200000 0xe00000>;
+	};
+	partition at 1000000 {
+		label = "Filesystem";
+		reg = <0x1000000 0x3f000000>;
+	};
+};
+
 &cpm_spi1 {
 	status = "okay";
 
arch/arm64/boot/dts/marvell/armada-70x0.dtsi +14 -0
index 860b6ae9dcc5..0e1a1e5be399 100644
@@ -64,5 +64,19 @@
 &cpm_syscon0 {
 	cpm_pinctrl: pinctrl {
 		compatible = "marvell,armada-7k-pinctrl";
+
+		nand_pins: nand-pins {
+			marvell,pins =
+			"mpp15", "mpp16", "mpp17", "mpp18",
+			"mpp19", "mpp20", "mpp21", "mpp22",
+			"mpp23", "mpp24", "mpp25", "mpp26",
+			"mpp27";
+			marvell,function = "dev";
+		};
+
+		nand_rb: nand-rb {
+			marvell,pins = "mpp13";
+			marvell,function = "nf";
+		};
 	};
 };
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +0 -0
index 8263a8a504a8..d41b41b613ec 100644
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi line 277
Quoted 5 lines
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -1
@@ -274,12 +274,13 @@
 				 * this controller is only usable on the CPM
 				 * for A7K and on the CPS for A8K.
 				 */
-				compatible = "marvell,armada370-nand";
+				compatible = "marvell,armada-8k-nand";
the controller on cp110 remains compatible with the one on Armada 370 (even if it needs more initialization steps), so we should keep it also and having instead the following line:

Quoted 4 lines

compatible = "marvell,armada-8k-nand", "marvell,armada370-nand";
You don't have to send a new version, unless someone is against it, I will amend it when applying on the mvebu branches.

Now applied on mvebu/dt64 with the changes I mentioned,

Thanks,

Gregory

Quoted 34 lines

Thanks,

Gregory

Quoted 17 lines

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -0

 				reg = <0x720000 0x54>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&cpm_clk 1 2>;
+				marvell,system-controller = <&cpm_syscon0>;
 				status = "disabled";
 			};

Signature · 7 lines

2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 9 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Boris Brezillon

2017-10-05 12:53 UTC #6 lore raw

cover Enable NAND on Armada-7040-DB board

In reply to Miquel Raynal

Quoted 14 lines · On Mon, 25 Sep 2017 16:53:49 +0200 Miquel Raynal…

Hi,
This series adds support for NAND on Armada-7040-DB board.
Besides standard NAND node addition, it also introduces a new compatible string for the pxa3xx_nand driver to support the subitilities of A7k/A8k SoCs, as well as a new property used by the pxa3xx_nand driver to grab a phandle on the system control node in order to enable the NAND controller itself.
Regards,
Miquel

Quoted 6 lines

Gregory CLEMENT (1):
arm64: dts: marvell: add NAND support on the 7040-DB board
Miquel Raynal (2):
Documentation: devicetree: add pxa3xx compatible and syscon property
mtd: nand: pxa3xx: enable NAND controller if the SoC needs it

Applied patch 1 and 2.

Thanks,

Boris

Quoted 8 lines

 .../devicetree/bindings/mtd/pxa3xx-nand.txt        |  4 +++
 arch/arm64/boot/dts/marvell/armada-7040-db.dts     | 24 +++++++++++++
 arch/arm64/boot/dts/marvell/armada-70x0.dtsi       | 14 ++++++++
 .../boot/dts/marvell/armada-cp110-master.dtsi      |  3 +-
 drivers/mtd/nand/pxa3xx_nand.c                     | 41 +++++++++++++++++++---
 5 files changed, 81 insertions(+), 5 deletions(-)