ASoC: pxa-ssp: remove .set_pll() and .set_clkdiv() callbacks

The .set_pll() and .set_clkdiv() callbacks are considered legacy and should not be used anymore. In order to support PXA boards on DT platforms, remove them and let the code figure out the correct dividers and PLL base frequencies itself.

---

I'd appreciate some review of this one. The only PXA3xx based platform I have access to uses the EXTCLK clocking source, but this patch changes the way the internal audio PLL works. Hence, I could only complile-test it for now.

The PLL lookup table is taken from the datasheet, so it should be fine, but I'm not sure whether I got the mclk/bclk/fs calculations right, so a 2nd pair of eyes would help to avoid regressions.

Given that the PXA platform has very little active mainline users, another option would be to just merge it and fix regressions if someone reports them.

Once this is applied, I'll post another patch that removes the calculations and the calls to snd_soc_dai_set_{clkdiv,pll} from the zylonite and magician machine drivers.

Thanks,
Daniel

 include/linux/pxa2xx_ssp.h |   8 ++
 sound/soc/pxa/pxa-ssp.c    | 146 ++++++++++++++++++-------------------
 2 files changed, 81 insertions(+), 73 deletions(-)

index 03a7ca46735b..13b4244d44c1 100644
@@ -171,6 +171,14 @@
 #define SSACD_SCDB		(1 << 3)	/* SSPSYSCLK Divider Bypass */
 #define SSACD_ACPS(x)		((x) << 4)	/* Audio clock PLL select */
 #define SSACD_ACDS(x)		((x) << 0)	/* Audio clock divider select */
+#define SSACD_ACDS_1		(0)
+#define SSACD_ACDS_2		(1)
+#define SSACD_ACDS_4		(2)
+#define SSACD_ACDS_8		(3)
+#define SSACD_ACDS_16		(4)
+#define SSACD_ACDS_32		(5)
+#define SSACD_SCDB_4X		(0)
+#define SSACD_SCDB_1X		(1)
 #define SSACD_SCDX8		(1 << 7)	/* SYSCLK division ratio select */
 
 /* LPSS SSP */

2.17.1

If the zylonite platform is a target, I can try. Nevertheless, I'd be inclined to use the approach "merge first, fix if there are regressions next".

I must admit that due to hot weather conditions in south France, and the electrical outages, my inverter decided to commit suicide ... As a true hero, he protected my boards, but now I must order a new one before attempting to use my lubbock/mainstone/zylonite again.

Cheers.

--
Robert

The patch

ASoC: pxa-ssp: remove .set_pll() and .set_clkdiv() callbacks

has been applied to the asoc tree at

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

From: Daniel Mack <[email protected]>
Date: Fri, 29 Jun 2018 14:59:40 +0200
Subject: [PATCH] ASoC: pxa-ssp: remove .set_pll() and .set_clkdiv() callbacks

The .set_pll() and .set_clkdiv() callbacks are considered legacy and should not be used anymore. In order to support PXA boards on DT platforms, remove them and let the code figure out the correct dividers and PLL base frequencies itself.

---
 include/linux/pxa2xx_ssp.h |   8 ++
 sound/soc/pxa/pxa-ssp.c    | 146 ++++++++++++++++++-------------------
 2 files changed, 81 insertions(+), 73 deletions(-)

index 03a7ca46735b..13b4244d44c1 100644
@@ -171,6 +171,14 @@
 #define SSACD_SCDB		(1 << 3)	/* SSPSYSCLK Divider Bypass */
 #define SSACD_ACPS(x)		((x) << 4)	/* Audio clock PLL select */
 #define SSACD_ACDS(x)		((x) << 0)	/* Audio clock divider select */
+#define SSACD_ACDS_1		(0)
+#define SSACD_ACDS_2		(1)
+#define SSACD_ACDS_4		(2)
+#define SSACD_ACDS_8		(3)
+#define SSACD_ACDS_16		(4)
+#define SSACD_ACDS_32		(5)
+#define SSACD_SCDB_4X		(0)
+#define SSACD_SCDB_1X		(1)
 #define SSACD_SCDX8		(1 << 7)	/* SYSCLK division ratio select */
 
 /* LPSS SSP */

2.18.0.rc2