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arm64: dts: marvell: cp110: enable the crypto engine at the SoC level

PATCH New Antoine Tenart 2 participants 6 messages Jun 15, 2017

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#0 lore raw

PATCH v2 1/3 arm64: dts: marvell: cp110: enable the crypto engine at the SoC level

Enable the cryptographic engine at the SoC level on the master cp110. This engine is always present and do not depends on any pinmux configuration.

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 -
 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +0 -1
index c4294403276b..54cc3fc7b6a4 100644
@@ -245,7 +245,6 @@
 				"ring2", "ring3", "eip";
 				clocks = <&cpm_syscon0 1 26>;
 				dma-mask = <0xff 0xffffffff>;
-				status = "disabled";
 			};
 		};
 
Signature · 1 line
2.9.4
#1 lore raw

PATCH v2 2/3 arm64: dts: marvell: remove cpm crypto nodes from dts files

The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it.

---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ----
 arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ----
 2 files changed, 8 deletions(-)
arch/arm64/boot/dts/marvell/armada-7040-db.dts +0 -4
index 771311051421..92c761c380d3 100644
@@ -187,7 +187,3 @@
 	phy = <&phy1>;
 	phy-mode = "rgmii-id";
 };
-
-&cpm_crypto {
-	status = "okay";
-};
arch/arm64/boot/dts/marvell/armada-8040-db.dts +0 -4
index 6af3c39bbb99..1e8f7242ed6f 100644
@@ -142,10 +142,6 @@
 	phy-mode = "rgmii-id";
 };
 
-&cpm_crypto {
-	status = "okay";
-};
-
 /* CON5 on CP1 expansion */
 &cps_pcie2 {
 	status = "okay";
Signature · 1 line
2.9.4
#2 lore raw

PATCH v2 2/3 arm64: dts: marvell: remove cpm crypto nodes from dts files

Hi Antoine,

Quoted 4 lines · Antoine Tenart

The cryptographic engine on the master cp110 is now enabled by default at the SoC level. Remove its dts nodes that were only enabling it.

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 35 lines
---
 arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ----
 arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ----
 2 files changed, 8 deletions(-)
arch/arm64/boot/dts/marvell/armada-7040-db.dts +0 -4
index 771311051421..92c761c380d3 100644
@@ -187,7 +187,3 @@
 	phy = <&phy1>;
 	phy-mode = "rgmii-id";
 };
-
-&cpm_crypto {
-	status = "okay";
-};
arch/arm64/boot/dts/marvell/armada-8040-db.dts +0 -4
index 6af3c39bbb99..1e8f7242ed6f 100644
@@ -142,10 +142,6 @@
 	phy-mode = "rgmii-id";
 };
 
-&cpm_crypto {
-	status = "okay";
-};
-
 /* CON5 on CP1 expansion */
 &cps_pcie2 {
 	status = "okay";
Signature · 1 line
2.9.4
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#3 lore raw

PATCH v2 3/3 arm64: dts: marvell: add a comment on the cp110 slave node status

In reply to Antoine Tenart

The cryptographic engine found on the cp110 slave is disabled by default because of some known limitations. Add a comment to explain why it is disabled by default.

---
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +7 -0
index 7e98c155cc6a..385ac30d6012 100644
@@ -234,6 +234,13 @@
 						  "ring2", "ring3", "eip";
 				clocks = <&cps_syscon0 1 26>;
 				dma-mask = <0xff 0xffffffff>;
+				/*
+				 * The cryptographic engine found on the cp110
+				 * master is enabled by default at the SoC
+				 * level. Because it is not possible as of now
+				 * to enable two cryptographic engines in
+				 * parallel, disable this one by default.
+				 */
 				status = "disabled";
 			};
 		};
Signature · 1 line
2.9.4
#4 lore raw

PATCH v2 3/3 arm64: dts: marvell: add a comment on the cp110 slave node status

Hi Antoine,

Quoted 5 lines · Antoine Tenart

The cryptographic engine found on the cp110 slave is disabled by default because of some known limitations. Add a comment to explain why it is disabled by default.

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 25 lines
---
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +7 -0
index 7e98c155cc6a..385ac30d6012 100644
@@ -234,6 +234,13 @@
 						  "ring2", "ring3", "eip";
 				clocks = <&cps_syscon0 1 26>;
 				dma-mask = <0xff 0xffffffff>;
+				/*
+				 * The cryptographic engine found on the cp110
+				 * master is enabled by default at the SoC
+				 * level. Because it is not possible as of now
+				 * to enable two cryptographic engines in
+				 * parallel, disable this one by default.
+				 */
 				status = "disabled";
 			};
 		};
Signature · 1 line
2.9.4
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#5 lore raw

PATCH v2 1/3 arm64: dts: marvell: cp110: enable the crypto engine at the SoC level

In reply to Antoine Tenart

Hi Antoine,

Quoted 5 lines · Antoine Tenart

Enable the cryptographic engine at the SoC level on the master cp110. This engine is always present and do not depends on any pinmux configuration.

Applied on mvebu/dt64

Thanks,

Gregory

Quoted 19 lines
---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 -
 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +0 -1
index c4294403276b..54cc3fc7b6a4 100644
@@ -245,7 +245,6 @@
 				"ring2", "ring3", "eip";
 				clocks = <&cpm_syscon0 1 26>;
 				dma-mask = <0xff 0xffffffff>;
-				status = "disabled";
 			};
 		};
 
Signature · 1 line
2.9.4
Signature · 4 lines
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com