ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Subsystems (2)
PATCH 1/1 ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult.
--- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)
arch/arm64/boot/dts/marvell/armada-37xx.dtsi +4 -8
@@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc {
Signature · 1 line
2.11.0
PATCH 1/1 ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Hi Marc,
Quoted 6 lines · Marc Zyngier
Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult.
Signed-off-by Marc Zyngier <[email protected]>
Applied on mvebu/fixes
Thanks,
Gregory
Quoted 30 lines
--- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)arch/arm64/boot/dts/marvell/armada-37xx.dtsi +4
-8@@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc {Signature · 1 line
2.11.0
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH 1/1 ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Hi,
Quoted 4 lines · Gregory CLEMENT
Hi Marc,
On mer., juin 21 2017, Marc Zyngier <[email protected]> wrote:
Quoted 8 lines
Quoted 6 lines
Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult.
Signed-off-by Marc Zyngier <[email protected]>Applied on mvebu/fixes
As I missed the end of the merge window for 4.12, I've just moved this patch on mvebu/dt64 wit the hope that it can be applied on a late dt branch on arm-soc for 4.13.
I also added the "Fixes" and "CC: stable" tags in order to propagate the fix on older kernel.
Gregory
Quoted 42 lines
Quoted 31 lines
--- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)arch/arm64/boot/dts/marvell/armada-37xx.dtsi +4
-8@@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc {Signature · 1 line
2.11.0Signature · 9 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH 1/1 ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers
Hi Gregory,
Quoted 15 lines · Gregory CLEMENT
Hi,
Quoted 11 lines · Gregory CLEMENT
Hi Marc,
Quoted 6 lines · Marc Zyngier
Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult.
Signed-off-by Marc Zyngier <[email protected]>
Quoted 8 lines
Quoted 1 line
Applied on mvebu/fixes
As I missed the end of the merge window for 4.12, I've just moved this patch on mvebu/dt64 wit the hope that it can be applied on a late dt branch on arm-soc for 4.13.
I also added the "Fixes" and "CC: stable" tags in order to propagate the fix on older kernel.
While you're at it, you could also add the couple of GIC-related fixes I've posted on Saturday (which are equally important).
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...