Disable automatic load CCS load balancing
Subsystems (3)
cover Disable automatic load CCS load balancing
Hi,
this series does basically two things:
1. Disables automatic load balancing as adviced by the hardware workaround.
2. Forces the sharing of the load submitted to CCS among all the CCS available (as of now only DG2 has more than one CCS). This way the user, when sending a query, will see only one CCS available.
Andi
Andi Shyti (2):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Set default CCS mode '1'
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 5 files changed, 40 insertions(+), 2 deletions(-)
Signature · 1 line
2.43.0
PATCH 1/2 drm/i915/gt: Disable HW load balancing for CCS
The hardware should not dynamically balance the load between CCS engines. Wa_16016805146 recommends disabling it across all platforms.
--- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 2 files changed, 7 insertions(+)
drivers/gpu/drm/i915/gt/intel_gt_regs.h +1 -0
@@ -1478,6 +1478,7 @@#define GEN12_RCU_MODE _MMIO(0x14800)#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)#define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)#define CHV_FGT_DISABLE_SS0 (1 << 10)
drivers/gpu/drm/i915/gt/intel_workarounds.c +6 -0
@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_liwa_mcr_masked_en (wal,GEN8_HALF_SLICE_CHICKEN1 ,GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE ); } + +/* +* Wa_16016805146: disable the CCS load balancing +* indiscriminately for all the platforms +*/ +wa_masked_en (wal,GEN12_RCU_MODE ,XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE ); } static void
Signature · 1 line
2.43.0
PATCH 2/2 drm/i915/gt: Set default CCS mode '1'
In reply to Andi ShytiSince CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/gt/intel_gt.c +11 -0
@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;
@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which
drivers/gpu/drm/i915/gt/intel_gt_regs.h +2 -0
@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)
drivers/gpu/drm/i915/i915_drv.h +17 -0
@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)
drivers/gpu/drm/i915/i915_query.c +3 -2
@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)
@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);
@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Signature · 1 line
2.43.0
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 3 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Erm *all* CSS engines work together..
Quoted 2 lines
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
... *one* CCS engine.
Quoted 71 lines
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +7
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* +* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'.
drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 415
Quoted 10 lines
drivers/gpu/drm/i915/i915_drv.h +10
-0+* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \ + for_each_uabi_engine(engine__, i915__) \ + if ((IS_DG2(i915__)) && \ + ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ + ((engine__)->uabi_instance)) { } \ + else +
I thought the plan was to simply not register the engine. Like that it would be a simpler patch.
drivers/gpu/drm/i915/i915_query.c static int query_geometry_subslices(struct drm_i915_private *i915, · line 127
Quoted 12 lines
drivers/gpu/drm/i915/i915_drv.h +0
-0#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +1
-0@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +
!
Quoted 13 lines
drivers/gpu/drm/i915/i915_query.c +1
-1static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);
drivers/gpu/drm/i915/i915_query.c query_engine_info(struct drm_i915_private *i915, · line 162
Quoted 8 lines
drivers/gpu/drm/i915/i915_query.c +1
-1@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
I thought you agreed that this still misses to hide the engine on direct lookup from userspace such as context map, PMU, SSEU. All of those would automatically be handled by not registering the engine.
Regards,
Tvrtko
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Quoted 6 lines · Tvrtko Ursulin
Quoted 3 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Quoted 6 lines
Erm *all* CSS engines work together..
Quoted 2 lines
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
... *one* CCS engine.
ops... I sent V1 again!
Sorry, I will send v2 now
Thanks!
Andi
Jani Nikula
maintainerRe: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
In reply to Andi ShytiQuoted 71 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/*
drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 409
Quoted 10 lines
drivers/gpu/drm/i915/i915_drv.h +10
-0+* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \
Hrmh, I've been trying to pester folks to move the existing engine iterator macros away from i915_drv.h, so not happy to see more.
But since this is Cc: stable, better do that in a follow-up. Please?
drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 414
Quoted 5 lines
drivers/gpu/drm/i915/i915_drv.h +5
-0+ for_each_uabi_engine(engine__, i915__) \ +if ((IS_DG2 (i915__)) && \ + ((engine__)->uabi_class ==I915_ENGINE_CLASS_COMPUTE ) && \ + ((engine__)->uabi_instance)) { } \ +else
We have for_each_if for this.
drivers/gpu/drm/i915/i915_query.c static int query_geometry_subslices(struct drm_i915_private *i915, · line 127
Quoted 13 lines
drivers/gpu/drm/i915/i915_drv.h +1
-0+#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +1
-0@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +
Superfluous newline change.
Quoted 21 lines
drivers/gpu/drm/i915/i915_query.c +2
-2static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;
Signature · 1 line
Jani Nikula, Intel
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
Hi Jani,
thanks, there has been a v2 after this and your comments have been addressed somehow.
There will be a v3, as well.
Thanks,
Andi
Quoted 136 lines · Jani Nikula
Quoted 71 lines · Andi Shyti
Since CCS automatic load balancing is disabled, we will impose a fixed balancing policy that involves setting all the CCS engines to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the actual number. As of now, this change affects only DG2.
Fixes d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")Signed-off-by Andi Shyti <[email protected]>Cc Chris Wilson <[email protected]>Cc Joonas Lahtinen <[email protected]>Cc Matt Roper <[email protected]>Cc <[email protected]> # v6.2+--- drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 4 files changed, 33 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gt/intel_gt.c +11
-0@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode (struct intel_gt *gt) +{ +if (!IS_DG2 (gt->i915)) +return ; + +intel_uncore_write (gt->uncore,XEHP_CCS_MODE ,0 ); +} +int intel_gt_init_hw (struct intel_gt *gt) {struct drm_i915_private *i915 = gt->i915;@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)intel_gt_init_swizzling (gt); +/* Configure CCS mode */ +intel_gt_apply_ccs_mode (gt); +/* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which drivers/gpu/drm/i915/gt/intel_gt_regs.h +2
-0@@ -1605,6 +1605,8 @@#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)#define GEN12_CAGF_MASK REG_GENMASK(19, 11) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define GEN11_GT_INTR_DW (x) _MMIO(0x190018 + ((x) * 4))#define GEN11_CSME (31)#define GEN12_HECI_2 (30)drivers/gpu/drm/i915/i915_drv.h +1
-0@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +/* drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 409
Quoted 10 lines
drivers/gpu/drm/i915/i915_drv.h +10
-0+* Exclude unavailable engines. +* +* Only the first CCS engine is utilized due to the disabling of CCS auto load +* balancing. As a result, all CCS engines operate collectively, functioning +* essentially as a single CCS engine, hence the count of active CCS engines is +* considered '1'. +* Currently, this applies to platforms with more than one CCS engine, +* specifically DG2. +*/ +#define for_each_available_uabi_engine (engine__, i915__) \Hrmh, I've been trying to pester folks to move the existing engine iterator macros away from
i915_drv.h, so not happy to see more.But since this is Cc: stable, better do that in a follow-up. Please?
drivers/gpu/drm/i915/i915_drv.h static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) · line 414
Quoted 5 lines
drivers/gpu/drm/i915/i915_drv.h +5
-0+ for_each_uabi_engine(engine__, i915__) \ +if ((IS_DG2 (i915__)) && \ + ((engine__)->uabi_class ==I915_ENGINE_CLASS_COMPUTE ) && \ + ((engine__)->uabi_instance)) { } \ +else We have
for_each_iffor this.drivers/gpu/drm/i915/i915_query.c static int query_geometry_subslices(struct drm_i915_private *i915, · line 127
Quoted 13 lines
drivers/gpu/drm/i915/i915_drv.h +1
-0+#define INTEL_INFO (i915) ((i915)->__info)#define RUNTIME_INFO (i915) (&(i915)->__runtime)#define DRIVER_CAPS (i915) (&(i915)->caps)drivers/gpu/drm/i915/i915_query.c +1
-0@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,return fill_topology_info (sseu, query_item, sseu->geometry_subslice_mask); } +Superfluous newline change.
Quoted 21 lines
drivers/gpu/drm/i915/i915_query.c +2
-2static int query_engine_info (struct drm_i915_private *i915,struct drm_i915_query_item *query_item)@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,if (query_item->flags)return -EINVAL ; -for_each_uabi_engine (engine, i915) +for_each_available_uabi_engine (engine, i915) num_uabi_engines++; len =struct_size (query_ptr, engines, num_uabi_engines);@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915, info_ptr = &query_ptr->engines[0 ]; -for_each_uabi_engine (engine, i915) { +for_each_available_uabi_engine (engine, i915) { info.engine.engine_class = engine->uabi_class; info.engine.engine_instance = engine->uabi_instance; info.flags =I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE ;Signature · 1 line
Jani Nikula, Intel
Hi,
I'm sorry, I forgot to add the changelog. Here it is:
v1 -> v2
========
- In Patch 1 use the correct workaround number (thanks Matt).
- In Patch 2 do not add the extra CCS engines to the exposed UABI engine list and adapt the engine counting accordingly (thanks Tvrtko).
- Reword the commit of Patch 2 (thanks John).
Quoted 27 lines · Andi Shyti
Hi,
this series does basically two things:
1. Disables automatic load balancing as adviced by the hardware workaround.
2. Forces the sharing of the load submitted to CCS among all the CCS available (as of now only DG2 has more than one CCS). This way the user, when sending a query, will see only one CCS available.
Andi
Andi Shyti (2):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Set default CCS mode '1'drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 5 files changed, 40 insertions(+), 2 deletions(-)Signature · 1 line
2.43.0
Please, ignore, I sent V1 again.
Sorry about the noise!
Andi
Quoted 27 lines · Andi Shyti
Hi,
this series does basically two things:
1. Disables automatic load balancing as adviced by the hardware workaround.
2. Forces the sharing of the load submitted to CCS among all the CCS available (as of now only DG2 has more than one CCS). This way the user, when sending a query, will see only one CCS available.
Andi
Andi Shyti (2):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Set default CCS mode '1'drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_query.c | 5 +++-- 5 files changed, 40 insertions(+), 2 deletions(-)Signature · 1 line
2.43.0
Patchwork
CI✗ Fi.CI.CHECKPATCH: warning for Disable automatic load CCS load balancing (rev2)
In reply to Andi Shyti== Series Details ==
== Series Details ==
Series: Disable automatic load CCS load balancing (rev2)
URL : https://patchwork.freedesktop.org/series/129951/
State : warning
== Summary ==
Error: dim checkpatch failed2065c72a8acd drm/i915/gt: Disable HW load balancing for CCS5e600e4db29b drm/i915/gt: Set default CCS mode '1'
-:80: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #80: FILE: drivers/gpu/drm/i915/i915_drv.h:409:
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects? #80: FILE: drivers/gpu/drm/i915/i915_drv.h:409:
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915__' - possible side-effects? #80: FILE: drivers/gpu/drm/i915/i915_drv.h:409:
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
-:82: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line #82: FILE: drivers/gpu/drm/i915/i915_drv.h:411:
+ if ((IS_DG2(i915__)) && \
[...]
+ ((engine__)->uabi_instance)) { } \
-:98: CHECK:LINE_SPACING: Please don't use multiple blank lines #98: FILE: drivers/gpu/drm/i915/i915_query.c:127:
+
total: 2 errors, 0 warnings, 3 checks, 77 lines checked
Patchwork
CI✗ Fi.CI.SPARSE: warning for Disable automatic load CCS load balancing (rev2)
In reply to Andi Shyti== Series Details ==
== Series Details ==
Series: Disable automatic load CCS load balancing (rev2)
URL : https://patchwork.freedesktop.org/series/129951/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Patchwork
CI✗ Fi.CI.BAT: failure for Disable automatic load CCS load balancing (rev2)
In reply to Andi Shyti== Series Details ==
== Series Details ==
Series: Disable automatic load CCS load balancing (rev2)
URL : https://patchwork.freedesktop.org/series/129951/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14300 -> Patchwork_129951v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_129951v2 absolutely need to be verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_129951v2, please notify your bug team ([email protected]) to allow them to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/index.html
Participating hosts (40 -> 38)
------------------------------
Missing (2): fi-glk-j4005 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_129951v2:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- fi-bsw-n3050: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-bsw-n3050/igt@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-bsw-n3050/igt@[email protected]
- fi-skl-6600u: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-skl-6600u/igt@[email protected]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-skl-6600u/igt@[email protected]
- fi-apl-guc: NOTRUN -> [ABORT][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-apl-guc/igt@[email protected]
- fi-skl-guc: [PASS][6] -> [ABORT][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-skl-guc/igt@[email protected]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-skl-guc/igt@[email protected]
- fi-kbl-7567u: [PASS][8] -> [ABORT][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-kbl-7567u/igt@[email protected]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-kbl-7567u/igt@[email protected]
- fi-cfl-8700k: [PASS][10] -> [ABORT][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-cfl-8700k/igt@[email protected]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-cfl-8700k/igt@[email protected]
- fi-bsw-nick: [PASS][12] -> [ABORT][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-bsw-nick/igt@[email protected]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-bsw-nick/igt@[email protected]
- bat-kbl-2: [PASS][14] -> [ABORT][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/bat-kbl-2/igt@[email protected]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/bat-kbl-2/igt@[email protected]
- fi-cfl-guc: [PASS][16] -> [ABORT][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-cfl-guc/igt@[email protected]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-cfl-guc/igt@[email protected]
- fi-kbl-x1275: [PASS][18] -> [ABORT][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-kbl-x1275/igt@[email protected]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-kbl-x1275/igt@[email protected]
- fi-cfl-8109u: [PASS][20] -> [ABORT][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-cfl-8109u/igt@[email protected]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-cfl-8109u/igt@[email protected]
- fi-ivb-3770: [PASS][22] -> [ABORT][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-ivb-3770/igt@[email protected]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-ivb-3770/igt@[email protected]
- fi-kbl-guc: [PASS][24] -> [ABORT][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-kbl-guc/igt@[email protected]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-kbl-guc/igt@[email protected]
* igt@i915_selftest@live@client:
- fi-elk-e7500: [PASS][26] -> [DMESG-WARN][27] +42 other tests dmesg-warn
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-elk-e7500/igt@i915_selftest@[email protected]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-elk-e7500/igt@i915_selftest@[email protected]
* igt@i915_selftest@live@coherency:
- bat-jsl-3: [PASS][28] -> [DMESG-WARN][29] +40 other tests dmesg-warn
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/bat-jsl-3/igt@i915_selftest@[email protected]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/bat-jsl-3/igt@i915_selftest@[email protected]
* igt@i915_selftest@live@gt_contexts:
- fi-ilk-650: [PASS][30] -> [DMESG-WARN][31] +42 other tests dmesg-warn
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html
* igt@i915_selftest@live@gt_pm:
- bat-jsl-1: [PASS][32] -> [DMESG-WARN][33] +40 other tests dmesg-warn
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/bat-jsl-1/igt@i915_selftest@live@gt_pm.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/bat-jsl-1/igt@i915_selftest@live@gt_pm.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.
* igt@runner@aborted:
- {bat-arls-2}: [FAIL][34] ([i915#10237]) -> [FAIL][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/bat-arls-2/igt@[email protected]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/bat-arls-2/igt@[email protected]
Known issues
------------
Here are the changes found in Patchwork_129951v2 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-apl-guc: [FAIL][36] ([i915#8293]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/fi-apl-guc/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/fi-apl-guc/boot.html
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- bat-jsl-3: [PASS][38] -> [DMESG-WARN][39] ([i915#1982])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/bat-jsl-3/igt@[email protected]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/bat-jsl-3/igt@[email protected]
- bat-jsl-1: [PASS][40] -> [DMESG-WARN][41] ([i915#1982])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14300/bat-jsl-1/igt@[email protected]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/bat-jsl-1/igt@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10237]: https://gitlab.freedesktop.org/drm/intel/issues/10237
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
Build changes
-------------
* Linux: CI_DRM_14300 -> Patchwork_129951v2
CI-20190529: 20190529
CI_DRM_14300: e2b02e89746d8eff8c244f938eecd0f1db8eb805 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7718: 40e8b9122853f455c84afcfa56469a6bc9a0d564 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129951v2: e2b02e89746d8eff8c244f938eecd0f1db8eb805 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
26221b83843a drm/i915/gt: Set default CCS mode '1' c1e3306767c1 drm/i915/gt: Disable HW load balancing for CCS
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129951v2/index.html