mtd: add driver for Intel discrete graphics

PATCH Applied Alexander Usyskin 4 participants 28 messages Mar 26, 2025 – May 12, 2025

Subsystems (5)

DRM drivers Intel i915 Memory technology devices (MTD) Intel xe +1 more subsystems

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Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #0 lore raw

v7 cover mtd: add driver for Intel discrete graphics

Add driver for access to Intel discrete graphics card internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and provide mtd driver to register this device with MTD framework.

This is a rewrite of "drm/i915/spi: spi access for discrete graphics" and "spi: add driver for Intel discrete graphics"
series with connection to the Xe driver and splitting
the spi driver part to separate module in mtd subsystem.

This series intended to be pushed through drm-xe-next.

V2: Replace dev_* prints with drm_* prints in drm (xe and i915) patches.
Enable NVM device on Battlemage HW (xe driver patch)
Fix overwrite register address (xe driver patch)
Add Rodrigo's r-b

V3: Use devm_pm_runtime_enable to simplify flow.
Drop print in i915 unload that was accidentally set as error. Drop HAS_GSC_NVM macro in line with latest Xe changes. Add more Rodrigo's r-b and Miquel's ack.

V4: Add patch that always creates mtd master device
and adjust mtd-intel-dg power management to use this device.

V5: Fix master device creation to accomodate for devices without
partitions (create partitoned master in this case) Rebase over latest drm-xe-next
Add ack's
V6: Fix master device release (use rigth idr in release)
Rebase over latest drm-xe-next
Grammar and style fixes

V7: Add patch with non-posted erase support (fix hang on BMG)
Rebase over latest drm-xe-next

Abliyev, Reuven (1):
drm/xe/nvm: add support for non-posted erase

Alexander Usyskin (11):
mtd: core: always create master device
mtd: add driver for intel graphics non-volatile memory device
mtd: intel-dg: implement region enumeration
mtd: intel-dg: implement access functions
mtd: intel-dg: register with mtd
mtd: intel-dg: align 64bit read and write
mtd: intel-dg: wake card on operations drm/i915/nvm: add nvm device for discrete graphics drm/i915/nvm: add support for access mode drm/xe/nvm: add on-die non-volatile memory device drm/xe/nvm: add support for access mode

 MAINTAINERS                           |   7 +
 drivers/gpu/drm/i915/Makefile         |   4 +
 drivers/gpu/drm/i915/i915_driver.c    |   6 +
 drivers/gpu/drm/i915/i915_drv.h       |   3 +
 drivers/gpu/drm/i915/i915_reg.h       |   1 +
 drivers/gpu/drm/i915/intel_nvm.c      | 115 ++++
 drivers/gpu/drm/i915/intel_nvm.h      |  15 +
 drivers/gpu/drm/xe/Makefile           |   1 +
 drivers/gpu/drm/xe/regs/xe_gsc_regs.h |   4 +
 drivers/gpu/drm/xe/xe_device.c        |   5 +
 drivers/gpu/drm/xe/xe_device_types.h  |   6 +
 drivers/gpu/drm/xe/xe_heci_gsc.c      |   5 +-
 drivers/gpu/drm/xe/xe_nvm.c           | 161 +++++
 drivers/gpu/drm/xe/xe_nvm.h           |  15 +
 drivers/gpu/drm/xe/xe_pci.c           |   6 +
 drivers/mtd/devices/Kconfig           |  11 +
 drivers/mtd/devices/Makefile          |   1 +
 drivers/mtd/devices/mtd_intel_dg.c    | 884 ++++++++++++++++++++++++++
 drivers/mtd/mtdcore.c                 | 141 ++--
 drivers/mtd/mtdcore.h                 |   2 +-
 drivers/mtd/mtdpart.c                 |  17 +-
 include/linux/intel_dg_nvm_aux.h      |  29 +
 22 files changed, 1385 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.c
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.h
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.c
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.h
 create mode 100644 drivers/mtd/devices/mtd_intel_dg.c
 create mode 100644 include/linux/intel_dg_nvm_aux.h

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #1 lore raw

PATCH v7 1/12 mtd: core: always create master device

Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.

This streamlines device tree and allows to anchor runtime power management on master device in all cases.

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/mtd/mtdcore.c | 141 +++++++++++++++++++++++++++++-------------
 drivers/mtd/mtdcore.h |   2 +-
 drivers/mtd/mtdpart.c |  17 ++---
 3 files changed, 110 insertions(+), 50 deletions(-)

drivers/mtd/mtdcore.c +99 ~~-42~~

index 724f917f91ba..d0e7fb027eb6 100644
@@ -68,7 +68,13 @@ static struct class mtd_class = {
 	.pm = MTD_CLS_PM_OPS,
 };
 
+static struct class mtd_master_class = {
+	.name = "mtd_master",
+	.pm = MTD_CLS_PM_OPS,
+};
+
 static DEFINE_IDR(mtd_idr);
+static DEFINE_IDR(mtd_master_idr);
 
 /* These are exported solely for the purpose of mtd_blkdevs.c. You
    should not use them for _anything_ else */

@@ -83,8 +89,9 @@ EXPORT_SYMBOL_GPL(__mtd_next_device);
 
 static LIST_HEAD(mtd_notifiers);
 
-
+#define MTD_MASTER_DEVS 255
 #define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2)
+static dev_t mtd_master_devt;
 
 /* REVISIT once MTD uses the driver model better, whoever allocates
  * the mtd_info will probably want to use the release() hook...

@@ -104,6 +111,17 @@ static void mtd_release(struct device *dev)
 	device_destroy(&mtd_class, index + 1);
 }
 
+static void mtd_master_release(struct device *dev)
+{
+	struct mtd_info *mtd = dev_get_drvdata(dev);
+
+	idr_remove(&mtd_master_idr, mtd->index);
+	of_node_put(mtd_get_of_node(mtd));
+
+	if (mtd_is_partition(mtd))
+		release_mtd_partition(mtd);
+}
+
 static void mtd_device_release(struct kref *kref)
 {
 	struct mtd_info *mtd = container_of(kref, struct mtd_info, refcnt);

@@ -367,6 +385,11 @@ static const struct device_type mtd_devtype = {
 	.release	= mtd_release,
 };
 
+static const struct device_type mtd_master_devtype = {
+	.name		= "mtd_master",
+	.release	= mtd_master_release,
+};
+
 static bool mtd_expert_analysis_mode;
 
 #ifdef CONFIG_DEBUG_FS

@@ -634,13 +657,13 @@ static void mtd_check_of_node(struct mtd_info *mtd)
 /**
  *	add_mtd_device - register an MTD device
  *	@mtd: pointer to new MTD device info structure
+ *	@partitioned: create partitioned device
  *
  *	Add a device to the list of MTD devices present in the system, and
  *	notify each currently active MTD 'user' of its arrival. Returns
  *	zero on success or non-zero on failure.
  */
-
-int add_mtd_device(struct mtd_info *mtd)
+int add_mtd_device(struct mtd_info *mtd, bool partitioned)
 {
 	struct device_node *np = mtd_get_of_node(mtd);
 	struct mtd_info *master = mtd_get_master(mtd);

@@ -687,10 +710,17 @@ int add_mtd_device(struct mtd_info *mtd)
 	ofidx = -1;
 	if (np)
 		ofidx = of_alias_get_id(np, "mtd");
-	if (ofidx >= 0)
-		i = idr_alloc(&mtd_idr, mtd, ofidx, ofidx + 1, GFP_KERNEL);
-	else
-		i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL);
+	if (partitioned) {
+		if (ofidx >= 0)
+			i = idr_alloc(&mtd_idr, mtd, ofidx, ofidx + 1, GFP_KERNEL);
+		else
+			i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL);
+	} else {
+		if (ofidx >= 0)
+			i = idr_alloc(&mtd_master_idr, mtd, ofidx, ofidx + 1, GFP_KERNEL);
+		else
+			i = idr_alloc(&mtd_master_idr, mtd, 0, 0, GFP_KERNEL);
+	}
 	if (i < 0) {
 		error = i;
 		goto fail_locked;

@@ -738,15 +768,23 @@ int add_mtd_device(struct mtd_info *mtd)
 	/* Caller should have set dev.parent to match the
 	 * physical device, if appropriate.
 	 */
-	mtd->dev.type = &mtd_devtype;
-	mtd->dev.class = &mtd_class;
-	mtd->dev.devt = MTD_DEVT(i);
-	dev_set_name(&mtd->dev, "mtd%d", i);
+	if (partitioned) {
+		mtd->dev.type = &mtd_devtype;
+		mtd->dev.class = &mtd_class;
+		mtd->dev.devt = MTD_DEVT(i);
+		dev_set_name(&mtd->dev, "mtd%d", i);
+	} else {
+		mtd->dev.type = &mtd_master_devtype;
+		mtd->dev.class = &mtd_master_class;
+		mtd->dev.devt = MKDEV(MAJOR(mtd_master_devt), i);
+		dev_set_name(&mtd->dev, "mtd_master%d", i);
+	}
 	dev_set_drvdata(&mtd->dev, mtd);
 	mtd_check_of_node(mtd);
 	of_node_get(mtd_get_of_node(mtd));
 	error = device_register(&mtd->dev);
 	if (error) {
+		pr_err("mtd: %s device_register fail %d\n", mtd->name, error);
 		put_device(&mtd->dev);
 		goto fail_added;
 	}

@@ -758,10 +796,13 @@ int add_mtd_device(struct mtd_info *mtd)
 
 	mtd_debugfs_populate(mtd);
 
-	device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
-		      "mtd%dro", i);
+	if (partitioned) {
+		device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
+			      "mtd%dro", i);
+	}
 
-	pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name);
+	pr_debug("mtd: Giving out %spartitioned device %d to %s\n",
+		 partitioned ? "" : "un-", i, mtd->name);
 	/* No need to get a refcount on the module containing
 	   the notifier, since we hold the mtd_table_mutex */
 	list_for_each_entry(not, &mtd_notifiers, list)

@@ -769,13 +810,16 @@ int add_mtd_device(struct mtd_info *mtd)
 
 	mutex_unlock(&mtd_table_mutex);
 
-	if (of_property_read_bool(mtd_get_of_node(mtd), "linux,rootfs")) {
-		if (IS_BUILTIN(CONFIG_MTD)) {
-			pr_info("mtd: setting mtd%d (%s) as root device\n", mtd->index, mtd->name);
-			ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index);
-		} else {
-			pr_warn("mtd: can't set mtd%d (%s) as root device - mtd must be builtin\n",
-				mtd->index, mtd->name);
+	if (partitioned) {
+		if (of_property_read_bool(mtd_get_of_node(mtd), "linux,rootfs")) {
+			if (IS_BUILTIN(CONFIG_MTD)) {
+				pr_info("mtd: setting mtd%d (%s) as root device\n",
+					mtd->index, mtd->name);
+				ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index);
+			} else {
+				pr_warn("mtd: can't set mtd%d (%s) as root device - mtd must be builtin\n",
+					mtd->index, mtd->name);
+			}
 		}
 	}

@@ -790,7 +834,10 @@ int add_mtd_device(struct mtd_info *mtd)
 	device_unregister(&mtd->dev);
 fail_added:
 	of_node_put(mtd_get_of_node(mtd));
-	idr_remove(&mtd_idr, i);
+	if (partitioned)
+		idr_remove(&mtd_idr, i);
+	else
+		idr_remove(&mtd_master_idr, i);
 fail_locked:
 	mutex_unlock(&mtd_table_mutex);
 	return error;

@@ -808,12 +855,14 @@ int add_mtd_device(struct mtd_info *mtd)
 
 int del_mtd_device(struct mtd_info *mtd)
 {
-	int ret;
 	struct mtd_notifier *not;
+	struct idr *idr;
+	int ret;
 
 	mutex_lock(&mtd_table_mutex);
 
-	if (idr_find(&mtd_idr, mtd->index) != mtd) {
+	idr = mtd->dev.class == &mtd_class ? &mtd_idr : &mtd_master_idr;
+	if (idr_find(idr, mtd->index) != mtd) {
 		ret = -ENODEV;
 		goto out_error;
 	}

@@ -1061,12 +1110,6 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 	if (ret)
 		goto out;
 
-	if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) {
-		ret = add_mtd_device(mtd);
-		if (ret)
-			goto out;
-	}
-
 	/* Prefer parsed partitions over driver-provided fallback */
 	ret = parse_mtd_partitions(mtd, types, parser_data);
 	if (ret == -EPROBE_DEFER)

@@ -1076,10 +1119,8 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 		ret = 0;
 	else if (nr_parts)
 		ret = add_mtd_partitions(mtd, parts, nr_parts);
-	else if (!device_is_registered(&mtd->dev))
-		ret = add_mtd_device(mtd);
 	else
-		ret = 0;
+		ret = add_mtd_device(mtd, true);
 
 	if (ret)
 		goto out;

@@ -1099,13 +1140,14 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 		register_reboot_notifier(&mtd->reboot_notifier);
 	}
 
+	return 0;
 out:
-	if (ret) {
-		nvmem_unregister(mtd->otp_user_nvmem);
-		nvmem_unregister(mtd->otp_factory_nvmem);
-	}
+	nvmem_unregister(mtd->otp_user_nvmem);
+	nvmem_unregister(mtd->otp_factory_nvmem);
 
-	if (ret && device_is_registered(&mtd->dev))
+	del_mtd_partitions(mtd);
+
+	if (device_is_registered(&mtd->dev))
 		del_mtd_device(mtd);
 
 	return ret;

@@ -1261,8 +1303,7 @@ int __get_mtd_device(struct mtd_info *mtd)
 		mtd = mtd->parent;
 	}
 
-	if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER))
-		kref_get(&master->refcnt);
+	kref_get(&master->refcnt);
 
 	return 0;
 }

@@ -1356,8 +1397,7 @@ void __put_mtd_device(struct mtd_info *mtd)
 		mtd = parent;
 	}
 
-	if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER))
-		kref_put(&master->refcnt, mtd_device_release);
+	kref_put(&master->refcnt, mtd_device_release);
 
 	module_put(master->owner);

@@ -2524,6 +2564,16 @@ static int __init init_mtd(void)
 	if (ret)
 		goto err_reg;
 
+	ret = class_register(&mtd_master_class);
+	if (ret)
+		goto err_reg2;
+
+	ret = alloc_chrdev_region(&mtd_master_devt, 0, MTD_MASTER_DEVS, "mtd_master");
+	if (ret < 0) {
+		pr_err("unable to allocate char dev region\n");
+		goto err_chrdev;
+	}
+
 	mtd_bdi = mtd_bdi_init("mtd");
 	if (IS_ERR(mtd_bdi)) {
 		ret = PTR_ERR(mtd_bdi);

@@ -2548,6 +2598,10 @@ static int __init init_mtd(void)
 	bdi_unregister(mtd_bdi);
 	bdi_put(mtd_bdi);
 err_bdi:
+	unregister_chrdev_region(mtd_master_devt, MTD_MASTER_DEVS);
+err_chrdev:
+	class_unregister(&mtd_master_class);
+err_reg2:
 	class_unregister(&mtd_class);
 err_reg:
 	pr_err("Error registering mtd class or bdi: %d\n", ret);

@@ -2561,9 +2615,12 @@ static void __exit cleanup_mtd(void)
 	if (proc_mtd)
 		remove_proc_entry("mtd", NULL);
 	class_unregister(&mtd_class);
+	class_unregister(&mtd_master_class);
+	unregister_chrdev_region(mtd_master_devt, MTD_MASTER_DEVS);
 	bdi_unregister(mtd_bdi);
 	bdi_put(mtd_bdi);
 	idr_destroy(&mtd_idr);
+	idr_destroy(&mtd_master_idr);
 }
 
 module_init(init_mtd);

drivers/mtd/mtdcore.h +1 -1

index b014861a06a6..2258d31c5aa6 100644
@@ -8,7 +8,7 @@ extern struct mutex mtd_table_mutex;
 extern struct backing_dev_info *mtd_bdi;
 
 struct mtd_info *__mtd_next_device(int i);
-int __must_check add_mtd_device(struct mtd_info *mtd);
+int __must_check add_mtd_device(struct mtd_info *mtd, bool partitioned);
 int del_mtd_device(struct mtd_info *mtd);
 int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
 int del_mtd_partitions(struct mtd_info *);

drivers/mtd/mtdpart.c +10 -7

index 6811a714349d..97505b132313 100644
@@ -86,8 +86,7 @@ static struct mtd_info *allocate_partition(struct mtd_info *parent,
 	 * parent conditional on that option. Note, this is a way to
 	 * distinguish between the parent and its partitions in sysfs.
 	 */
-	child->dev.parent = IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd_is_partition(parent) ?
-			    &parent->dev : parent->dev.parent;
+	child->dev.parent = &parent->dev;
 	child->dev.of_node = part->of_node;
 	child->parent = parent;
 	child->part.offset = part->offset;

@@ -276,7 +275,7 @@ int mtd_add_partition(struct mtd_info *parent, const char *name,
 	list_add_tail(&child->part.node, &parent->partitions);
 	mutex_unlock(&master->master.partitions_lock);
 
-	ret = add_mtd_device(child);
+	ret = add_mtd_device(child, true);
 	if (ret)
 		goto err_remove_part;

@@ -402,6 +401,12 @@ int add_mtd_partitions(struct mtd_info *parent,
 	printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n",
 	       nbparts, parent->name);
 
+	if (!mtd_is_partition(parent)) {
+		ret = add_mtd_device(parent, IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER));
+		if (ret)
+			return ret;
+	}
+
 	for (i = 0; i < nbparts; i++) {
 		child = allocate_partition(parent, parts + i, i, cur_offset);
 		if (IS_ERR(child)) {

@@ -413,7 +418,7 @@ int add_mtd_partitions(struct mtd_info *parent,
 		list_add_tail(&child->part.node, &parent->partitions);
 		mutex_unlock(&master->master.partitions_lock);
 
-		ret = add_mtd_device(child);
+		ret = add_mtd_device(child, true);
 		if (ret) {
 			mutex_lock(&master->master.partitions_lock);
 			list_del(&child->part.node);

@@ -590,9 +595,6 @@ static int mtd_part_of_parse(struct mtd_info *master,
 	int ret, err = 0;
 
 	dev = &master->dev;
-	/* Use parent device (controller) if the top level MTD is not registered */
-	if (!IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) && !mtd_is_partition(master))
-		dev = master->dev.parent;
 
 	np = mtd_get_of_node(master);
 	if (mtd_is_partition(master))

@@ -712,6 +714,7 @@ int parse_mtd_partitions(struct mtd_info *master, const char *const *types,
 		if (ret < 0 && !err)
 			err = ret;
 	}
+
 	return err;
 }

Signature · 1 line

2.43.0

Miquel Raynal

maintainer

2025-04-01 15:00 UTC #2 lore raw

Re: [PATCH v7 01/12] mtd: core: always create master device

Hello Alexander,

Quoted 7 lines · Alexander Usyskin

Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.
This streamlines device tree and allows to anchor runtime power management on master device in all cases.
Signed-off-by Alexander Usyskin <[email protected]>

I successfully tested it, this patch will be applied at -rc1 to the mtd/next tree.

I was wondering, do you think it would be possible to keep the creation of mtd_master and make it a symbolic link to mtdx when MTD_PARTITIONED_MASTER=y or when there is no partition? In short, always having mtd_masterx, because I fear at some point we'll have problems otherwise :-)

Right now we have:

- Without partition:
mtd0 (mtd0ro mtdblock0)
- With partition and MTD_PARTITIONED_MASTER=n
mtd0 (mtd0ro mtdblock0)
mtd_master0
- With partition and MTD_PARTITIONED_MASTER=y
mtd0 (mtd0ro mtdblock0) [this is the master]
mtd1 (mtd1ro mtdblock1)

I am suggesting:
- Without partition:
mtd0 (mtd0ro mtdblock0)
mtd_master0 -> link to mtd0
- With partition and MTD_PARTITIONED_MASTER=n
mtd0 (mtd0ro mtdblock0)
mtd_master0
- With partition and MTD_PARTITIONED_MASTER=y
mtd0 (mtd0ro mtdblock0) [this is the master]
mtd1 (mtd1ro mtdblock1)
mtd_master0 -> link to mtd0

What do you think? Or maybe even always mtd_master in the first place.

Richard, your point of view on this?

Thanks,
Miquèl

Usyskin, Alexander

author maintainer

2025-04-07 12:47 UTC #3 lore raw

RE: [PATCH v7 01/12] mtd: core: always create master device

Quoted 43 lines

Quoted 7 lines · Alexander Usyskin
Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.
This streamlines device tree and allows to anchor runtime power management on master device in all cases.
Signed-off-by Alexander Usyskin <[email protected]>
I successfully tested it, this patch will be applied at -rc1 to the mtd/next tree.
I was wondering, do you think it would be possible to keep the creation of mtd_master and make it a symbolic link to mtdx when MTD_PARTITIONED_MASTER=y or when there is no partition? In short, always having mtd_masterx, because I fear at some point we'll have problems otherwise :-)
Right now we have:
- Without partition:
mtd0 (mtd0ro mtdblock0)
- With partition and MTD_PARTITIONED_MASTER=n
mtd0 (mtd0ro mtdblock0)
mtd_master0
- With partition and MTD_PARTITIONED_MASTER=y
mtd0 (mtd0ro mtdblock0) [this is the master]
mtd1 (mtd1ro mtdblock1)
I am suggesting:
- Without partition:
mtd0 (mtd0ro mtdblock0)
mtd_master0 -> link to mtd0
- With partition and MTD_PARTITIONED_MASTER=n
mtd0 (mtd0ro mtdblock0)
mtd_master0
- With partition and MTD_PARTITIONED_MASTER=y
mtd0 (mtd0ro mtdblock0) [this is the master]
mtd1 (mtd1ro mtdblock1)
mtd_master0 -> link to mtd0

Quoted 6 lines

What do you think? Or maybe even always mtd_master in the first place.
Richard, your point of view on this?
Thanks,
Miquèl

The mtd_master is completely different class to avoid mtd tree disturbances. It is real kernel device object, I'm not sure how we can do 'link to' magic here.

About MTD_PARTITIONED_MASTER - we can treat it as another partition and create master device plus whole device partition as it's child with all other partitions as children of master device.
For unpartitioned device this mean that we create master device and partition regardless of MTD_PARTITIONED_MASTER flag.

We also can always add master device and add whole device partition as it's child, while adding real partition as children of this whole device.
This will create three layers of devices and sounds too complicated.

- -
Thanks,
Sasha

Miquel Raynal

maintainer

2025-04-09 10:00 UTC #4 lore raw

Re: [PATCH v7 01/12] mtd: core: always create master device

Hello,

Quoted 3 lines

The mtd_master is completely different class to avoid mtd tree disturbances. It is real kernel device object, I'm not sure how we can do 'link to' magic here.

Maybe we can add that later if someone needs.

Quoted 5 lines

About MTD_PARTITIONED_MASTER - we can treat it as another partition and create master device plus whole device partition as it's child with all other partitions as children of master device.
For unpartitioned device this mean that we create master device and partition regardless of MTD_PARTITIONED_MASTER flag.

I am not sure I follow you. I am proposing to create the mtd_master device in all cases. I believe this is the future-proof approach. Can you make this change?

Regarding the hierarchy, I indeed agree with what you propose:
mtd_master parent of whole partition device (if any) parent of partitions.

Thanks,
Miquèl

Usyskin, Alexander

author maintainer

2025-04-10 09:44 UTC #5 lore raw

RE: [PATCH v7 01/12] mtd: core: always create master device

Quoted 16 lines

Hello,
Quoted 3 lines
The mtd_master is completely different class to avoid mtd tree disturbances. It is real kernel device object, I'm not sure how we can do 'link to' magic here.
Maybe we can add that later if someone needs.
Quoted 1 line
About MTD_PARTITIONED_MASTER - we can treat it as another partition
and
Quoted 3 lines
create master device plus whole device partition as it's child with all other partitions as children of master device.
For unpartitioned device this mean that we create master device and
partition
Quoted 1 line
regardless of MTD_PARTITIONED_MASTER flag.

Quoted 8 lines

I am not sure I follow you. I am proposing to create the mtd_master device in all cases. I believe this is the future-proof approach. Can you make this change?
Regarding the hierarchy, I indeed agree with what you propose:
mtd_master parent of whole partition device (if any) parent of partitions.

To be sure:

You want to have this hierarchy without MTD_PARTITIONED_MASTER:
mtd_master
\/
|->partition1
|->partition2

With MTD_PARTITIONED_MASTER flag:

mtd_master
\/
|->master_partition
\/
|->partition1
|->partition2

- -
Thanks,
Sasha

Quoted 2 lines

Thanks,
Miquèl

Usyskin, Alexander

author maintainer

2025-04-10 14:12 UTC #6 lore raw

RE: [PATCH v7 01/12] mtd: core: always create master device

Quoted 38 lines

Subject: RE: [PATCH v7 01/12] mtd: core: always create master device
Hi
Quoted 3 lines
Hello,
Quoted 1 line
The mtd_master is completely different class to avoid mtd tree
disturbances.
Quoted 13 lines
Quoted 2 lines
It is real kernel device object, I'm not sure how we can do 'link to' magic here.
Maybe we can add that later if someone needs.
Quoted 1 line
About MTD_PARTITIONED_MASTER - we can treat it as another partition
and
Quoted 3 lines
create master device plus whole device partition as it's child with all other partitions as children of master device.
For unpartitioned device this mean that we create master device and
partition
Quoted 1 line
regardless of MTD_PARTITIONED_MASTER flag.
Quoted 8 lines
I am not sure I follow you. I am proposing to create the mtd_master device in all cases. I believe this is the future-proof approach. Can you make this change?
Regarding the hierarchy, I indeed agree with what you propose:
mtd_master parent of whole partition device (if any) parent of partitions.
To be sure:
You want to have this hierarchy without MTD_PARTITIONED_MASTER:
mtd_master
\/
|->partition1
|->partition2

Quoted 9 lines

With MTD_PARTITIONED_MASTER flag:
mtd_master
\/
|->master_partition
\/
|->partition1
|->partition2

Like this?

drivers/mtd/mtdchar.c +1 -1

index 8dc4f5c493fc..391d81ad960c 100644
@@ -559,7 +559,7 @@ static int mtdchar_blkpg_ioctl(struct mtd_info *mtd,
 		/* Sanitize user input */
 		p.devname[BLKPG_DEVNAMELTH - 1] = '\0';
 
-		return mtd_add_partition(mtd, p.devname, p.start, p.length);
+		return mtd_add_partition(mtd, p.devname, p.start, p.length, NULL);
 
 	case BLKPG_DEL_PARTITION:

drivers/mtd/mtdcore.c +19 -4

index ee46766d74f1..a32cea0ba535 100644
@@ -1108,6 +1108,7 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 			      const struct mtd_partition *parts,
 			      int nr_parts)
 {
+	struct mtd_info *parent;
 	int ret, err;
 
 	mtd_set_dev_defaults(mtd);

@@ -1116,17 +1117,31 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 	if (ret)
 		goto out;
 
+	ret = add_mtd_device(mtd, false);
+	if (ret)
+		goto out;
+
+	if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER))
+	{
+		ret = mtd_add_partition(mtd, dev_name(&mtd->dev), 0, MTDPART_SIZ_FULL, &parent);
+		if (ret)
+			goto out;
+
+	} else {
+		parent = mtd;
+	}
+
 	/* Prefer parsed partitions over driver-provided fallback */
-	ret = parse_mtd_partitions(mtd, types, parser_data);
+	ret = parse_mtd_partitions(parent, types, parser_data);
 	if (ret == -EPROBE_DEFER)
 		goto out;
 
 	if (ret > 0)
 		ret = 0;
 	else if (nr_parts)
-		ret = add_mtd_partitions(mtd, parts, nr_parts);
-	else
-		ret = add_mtd_device(mtd, true);
+		ret = add_mtd_partitions(parent, parts, nr_parts);
+	else if (!IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER))
+		ret = mtd_add_partition(parent, dev_name(&mtd->dev), 0, MTDPART_SIZ_FULL, NULL);
 
 	if (ret)
 		goto out;

drivers/mtd/mtdpart.c +4 -7

index 8a019cf0360d..cd5ae919b80c 100644
@@ -242,7 +242,7 @@ static int mtd_add_partition_attrs(struct mtd_info *new)
 }
 
 int mtd_add_partition(struct mtd_info *parent, const char *name,
-		      long long offset, long long length)
+		      long long offset, long long length, struct mtd_info **out)
 {
 	struct mtd_info *master = mtd_get_master(parent);
 	u64 parent_size = mtd_is_partition(parent) ?

@@ -281,6 +281,9 @@ int mtd_add_partition(struct mtd_info *parent, const char *name,
 
 	mtd_add_partition_attrs(child);
 
+	if (*out)
+		*out = child;
+
 	return 0;
 
 err_remove_part:

@@ -401,12 +404,6 @@ int add_mtd_partitions(struct mtd_info *parent,
 	printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n",
 	       nbparts, parent->name);
 
-	if (!mtd_is_partition(parent)) {
-		ret = add_mtd_device(parent, IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER));
-		if (ret)
-			return ret;
-	}
-
 	for (i = 0; i < nbparts; i++) {
 		child = allocate_partition(parent, parts + i, i, cur_offset);
 		if (IS_ERR(child)) {

include/linux/mtd/partitions.h +1 -1

index b74a539ec581..5daf80df9e89 100644
@@ -108,7 +108,7 @@ extern void deregister_mtd_parser(struct mtd_part_parser *parser);
 		      deregister_mtd_parser)
 
 int mtd_add_partition(struct mtd_info *master, const char *name,
-		      long long offset, long long length);
+		      long long offset, long long length, struct mtd_info **part);
 int mtd_del_partition(struct mtd_info *master, int partno);
 uint64_t mtd_get_device_size(const struct mtd_info *mtd);

Miquel Raynal

maintainer Applied

2025-04-29 09:23 UTC #7 lore raw

Re: [PATCH v7 01/12] mtd: core: always create master device

In reply to Alexander Usyskin

Quoted 7 lines · Alexander Usyskin

Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.
This streamlines device tree and allows to anchor runtime power management on master device in all cases.
Signed-off-by Alexander Usyskin <[email protected]>

Applied to mtd/next. Thanks!

Miquèl

Usyskin, Alexander

author maintainer

2025-05-06 11:07 UTC #8 lore raw

RE: [PATCH v7 01/12] mtd: core: always create master device

Quoted 7 lines

Quoted 3 lines · Alexander Usyskin
Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.

Quoted 8 lines

Quoted 4 lines
This streamlines device tree and allows to anchor runtime power management on master device in all cases.
Signed-off-by Alexander Usyskin <[email protected]>
Applied to mtd/next. Thanks!
Miquèl

Thanks a lot!

Miquel, would you pick patches from this series for files that are in the mtd tree?
I can send separate patch series for this.
In this case the i915/Xe patches can be merged in parallel via Xe tree.

- -
Thanks,
Sasha

Miquel Raynal

maintainer

2025-05-12 08:25 UTC #9 lore raw

Re: [PATCH v7 01/12] mtd: core: always create master device

Hello Alexander,

Quoted 16 lines · Alexander

Quoted 7 lines
Quoted 3 lines · Alexander Usyskin
Create master device without partition when
CONFIG_MTD_PARTITIONED_MASTER flag is unset.
Quoted 8 lines
Quoted 4 lines
This streamlines device tree and allows to anchor runtime power management on master device in all cases.
Signed-off-by Alexander Usyskin <[email protected]>
Applied to mtd/next. Thanks!
Miquèl

Quoted 7 lines

Thanks a lot!
Miquel, would you pick patches from this series for files that are in the mtd tree?
I can send separate patch series for this.
In this case the i915/Xe patches can be merged in parallel via Xe tree.

I read several times that these patches should go through drm somehow, so I provided my Ack. I do not think build would be broken if patch 1 goes through mtd and the others through drm anyway, especially since drm has some structural slowness which means once applied to drm-misc(-next) they may be part of the main tree a release later (iiuc).

However, I might drop this patch and reapply the one from v9, because I apparently messed up with the version count. There is no action required on your side.

Thanks,
Miquèl

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #10 lore raw

PATCH v7 2/12 mtd: add driver for intel graphics non-volatile memory device

In reply to Alexander Usyskin

Add auxiliary driver for intel discrete graphics
non-volatile memory device.

CC Lucas De Marchi <[email protected]>

Reviewed-by Rodrigo Vivi <[email protected]>

Acked-by Miquel Raynal <[email protected]>

Co-developed-by Tomas Winkler <[email protected]>

Signed-off-by Tomas Winkler <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 MAINTAINERS                        |   7 ++
 drivers/mtd/devices/Kconfig        |  11 +++
 drivers/mtd/devices/Makefile       |   1 +
 drivers/mtd/devices/mtd_intel_dg.c | 138 +++++++++++++++++++++++++++++
 include/linux/intel_dg_nvm_aux.h   |  27 ++++++
 5 files changed, 184 insertions(+)
 create mode 100644 drivers/mtd/devices/mtd_intel_dg.c
 create mode 100644 include/linux/intel_dg_nvm_aux.h

MAINTAINERS +7 -0

index 1554908c94cc..6b6c8cdafc16 100644
@@ -11594,6 +11594,13 @@ L:	[email protected]
 S:	Supported
 F:	arch/x86/include/asm/intel-family.h
 
+INTEL DISCRETE GRAPHICS NVM MTD DRIVER
+M:	Alexander Usyskin <[email protected]>
+L:	[email protected]
+S:	Supported
+F:	drivers/mtd/devices/mtd_intel_dg.c
+F:	include/linux/intel_dg_nvm_aux.h
+
 INTEL DRM DISPLAY FOR XE AND I915 DRIVERS
 M:	Jani Nikula <[email protected]>
 M:	Rodrigo Vivi <[email protected]>

drivers/mtd/devices/Kconfig +11 -0

index ff2f9e55ef28..59be6d3f0d32 100644
@@ -183,6 +183,17 @@ config MTD_POWERNV_FLASH
 	  platforms from Linux. This device abstracts away the
 	  firmware interface for flash access.
 
+config MTD_INTEL_DG
+	tristate "Intel Discrete Graphics non-volatile memory driver"
+	depends on AUXILIARY_BUS
+	depends on MTD
+	help
+	  This provides an MTD device to access Intel Discrete Graphics
+	  non-volatile memory.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called mtd-intel-dg.
+
 comment "Disk-On-Chip Device Drivers"
 
 config MTD_DOCG3

drivers/mtd/devices/Makefile +1 -0

index d11eb2b8b6f8..9fe4ce9cffde 100644
@@ -18,6 +18,7 @@ obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
 obj-$(CONFIG_MTD_BCM47XXSFLASH)	+= bcm47xxsflash.o
 obj-$(CONFIG_MTD_ST_SPI_FSM)    += st_spi_fsm.o
 obj-$(CONFIG_MTD_POWERNV_FLASH)	+= powernv_flash.o
+obj-$(CONFIG_MTD_INTEL_DG)	+= mtd_intel_dg.o
 
 
 CFLAGS_docg3.o			+= -I$(src)

drivers/mtd/devices/mtd_intel_dg.c new file +138 -0

138 lines not on this page · raw message

include/linux/intel_dg_nvm_aux.h new file +27 -0

new file mode 100644
index 000000000000..68df634c994c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2025, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_DG_NVM_AUX_H__
+#define __INTEL_DG_NVM_AUX_H__
+
+#include <linux/auxiliary_bus.h>
+
+#define INTEL_DG_NVM_REGIONS 13
+
+struct intel_dg_nvm_region {
+	const char *name;
+};
+
+struct intel_dg_nvm_dev {
+	struct auxiliary_device aux_dev;
+	bool writable_override;
+	struct resource bar;
+	const struct intel_dg_nvm_region *regions;
+};
+
+#define auxiliary_dev_to_intel_dg_nvm_dev(auxiliary_dev) \
+	container_of(auxiliary_dev, struct intel_dg_nvm_dev, aux_dev)
+
+#endif /* __INTEL_DG_NVM_AUX_H__ */

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #11 lore raw

PATCH v7 3/12 mtd: intel-dg: implement region enumeration

In reply to Alexander Usyskin

In intel-dg, there is no access to the spi controller, the information is extracted from the descriptor region.

CC Lucas De Marchi <[email protected]>

Reviewed-by Rodrigo Vivi <[email protected]>

Acked-by Miquel Raynal <[email protected]>

Co-developed-by Tomas Winkler <[email protected]>

Signed-off-by Tomas Winkler <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/mtd/devices/mtd_intel_dg.c | 198 +++++++++++++++++++++++++++++
 1 file changed, 198 insertions(+)

drivers/mtd/devices/mtd_intel_dg.c +198 -0

index 963a88cacc6c..ba1c720e717b 100644
@@ -3,6 +3,8 @@
  * Copyright(c) 2019-2025, Intel Corporation. All rights reserved.
  */
 
+#include <linux/bitfield.h>
+#include <linux/bits.h>
 #include <linux/device.h>
 #include <linux/intel_dg_nvm_aux.h>
 #include <linux/io.h>

@@ -22,9 +24,199 @@ struct intel_dg_nvm {
 		u8 id;
 		u64 offset;
 		u64 size;
+		unsigned int is_readable:1;
+		unsigned int is_writable:1;
 	} regions[] __counted_by(nregions);
 };
 
+#define NVM_TRIGGER_REG       0x00000000
+#define NVM_VALSIG_REG        0x00000010
+#define NVM_ADDRESS_REG       0x00000040
+#define NVM_REGION_ID_REG     0x00000044
+/*
+ * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K
+ * [23:16]-Reserved
+ * [31:24]-Erase MEM RegionID
+ */
+#define NVM_ERASE_REG         0x00000048
+#define NVM_ACCESS_ERROR_REG  0x00000070
+#define NVM_ADDRESS_ERROR_REG 0x00000074
+
+/* Flash Valid Signature */
+#define NVM_FLVALSIG          0x0FF0A55A
+
+#define NVM_MAP_ADDR_MASK     GENMASK(7, 0)
+#define NVM_MAP_ADDR_SHIFT    0x00000004
+
+#define NVM_REGION_ID_DESCRIPTOR  0
+/* Flash Region Base Address */
+#define NVM_FRBA      0x40
+/* Flash Region __n - Flash Descriptor Record */
+#define NVM_FLREG(__n) (NVM_FRBA + ((__n) * 4))
+/*  Flash Map 1 Register */
+#define NVM_FLMAP1_REG  0x18
+#define NVM_FLMSTR4_OFFSET 0x00C
+
+#define NVM_ACCESS_ERROR_PCIE_MASK 0x7
+
+#define NVM_FREG_BASE_MASK GENMASK(15, 0)
+#define NVM_FREG_ADDR_MASK GENMASK(31, 16)
+#define NVM_FREG_ADDR_SHIFT 12
+#define NVM_FREG_MIN_REGION_SIZE 0xFFF
+
+static inline void idg_nvm_set_region_id(struct intel_dg_nvm *nvm, u8 region)
+{
+	iowrite32((u32)region, nvm->base + NVM_REGION_ID_REG);
+}
+
+static inline u32 idg_nvm_error(struct intel_dg_nvm *nvm)
+{
+	void __iomem *base = nvm->base;
+
+	u32 reg = ioread32(base + NVM_ACCESS_ERROR_REG) & NVM_ACCESS_ERROR_PCIE_MASK;
+
+	/* reset error bits */
+	if (reg)
+		iowrite32(reg, base + NVM_ACCESS_ERROR_REG);
+
+	return reg;
+}
+
+static inline u32 idg_nvm_read32(struct intel_dg_nvm *nvm, u32 address)
+{
+	void __iomem *base = nvm->base;
+
+	iowrite32(address, base + NVM_ADDRESS_REG);
+
+	return ioread32(base + NVM_TRIGGER_REG);
+}
+
+static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_map)
+{
+	u32 flmap1;
+	u32 fmba;
+	u32 fmstr4;
+	u32 fmstr4_addr;
+
+	idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR);
+
+	flmap1 = idg_nvm_read32(nvm, NVM_FLMAP1_REG);
+	if (idg_nvm_error(nvm))
+		return -EIO;
+	/* Get Flash Master Baser Address (FMBA) */
+	fmba = (FIELD_GET(NVM_MAP_ADDR_MASK, flmap1) << NVM_MAP_ADDR_SHIFT);
+	fmstr4_addr = fmba + NVM_FLMSTR4_OFFSET;
+
+	fmstr4 = idg_nvm_read32(nvm, fmstr4_addr);
+	if (idg_nvm_error(nvm))
+		return -EIO;
+
+	*access_map = fmstr4;
+	return 0;
+}
+
+static bool idg_nvm_region_readable(u32 access_map, u8 region)
+{
+	if (region < 12)
+		return access_map & BIT(region + 8); /* [19:8] */
+	else
+		return access_map & BIT(region - 12); /* [3:0] */
+}
+
+static bool idg_nvm_region_writable(u32 access_map, u8 region)
+{
+	if (region < 12)
+		return access_map & BIT(region + 20); /* [31:20] */
+	else
+		return access_map & BIT(region - 8); /* [7:4] */
+}
+
+static int idg_nvm_is_valid(struct intel_dg_nvm *nvm)
+{
+	u32 is_valid;
+
+	idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR);
+
+	is_valid = idg_nvm_read32(nvm, NVM_VALSIG_REG);
+	if (idg_nvm_error(nvm))
+		return -EIO;
+
+	if (is_valid != NVM_FLVALSIG)
+		return -ENODEV;
+
+	return 0;
+}
+
+static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *device)
+{
+	int ret;
+	unsigned int i, n;
+	u32 access_map = 0;
+
+	/* clean error register, previous errors are ignored */
+	idg_nvm_error(nvm);
+
+	ret = idg_nvm_is_valid(nvm);
+	if (ret) {
+		dev_err(device, "The MEM is not valid %d\n", ret);
+		return ret;
+	}
+
+	if (idg_nvm_get_access_map(nvm, &access_map))
+		return -EIO;
+
+	for (i = 0, n = 0; i < nvm->nregions; i++) {
+		u32 address, base, limit, region;
+		u8 id = nvm->regions[i].id;
+
+		address = NVM_FLREG(id);
+		region = idg_nvm_read32(nvm, address);
+
+		base = FIELD_GET(NVM_FREG_BASE_MASK, region) << NVM_FREG_ADDR_SHIFT;
+		limit = (FIELD_GET(NVM_FREG_ADDR_MASK, region) << NVM_FREG_ADDR_SHIFT) |
+			NVM_FREG_MIN_REGION_SIZE;
+
+		dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n",
+			id, nvm->regions[i].name, region, base, limit);
+
+		if (base >= limit || (i > 0 && limit == 0)) {
+			dev_dbg(device, "[%d] %s: disabled\n",
+				id, nvm->regions[i].name);
+			nvm->regions[i].is_readable = 0;
+			continue;
+		}
+
+		if (nvm->size < limit)
+			nvm->size = limit;
+
+		nvm->regions[i].offset = base;
+		nvm->regions[i].size = limit - base + 1;
+		/* No write access to descriptor; mask it out*/
+		nvm->regions[i].is_writable = idg_nvm_region_writable(access_map, id);
+
+		nvm->regions[i].is_readable = idg_nvm_region_readable(access_map, id);
+		dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld rd=%d wr=%d\n",
+			nvm->regions[i].name,
+			nvm->regions[i].id,
+			nvm->regions[i].offset,
+			nvm->regions[i].size,
+			nvm->regions[i].is_readable,
+			nvm->regions[i].is_writable);
+
+		if (nvm->regions[i].is_readable)
+			n++;
+	}
+
+	dev_dbg(device, "Registered %d regions\n", n);
+
+	/* Need to add 1 to the amount of memory
+	 * so it is reported as an even block
+	 */
+	nvm->size += 1;
+
+	return n;
+}
+
 static void intel_dg_nvm_release(struct kref *kref)
 {
 	struct intel_dg_nvm *nvm = container_of(kref, struct intel_dg_nvm, refcnt);

@@ -88,6 +280,12 @@ static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev,
 		goto err;
 	}
 
+	ret = intel_dg_nvm_init(nvm, device);
+	if (ret < 0) {
+		dev_err(device, "cannot initialize nvm %d\n", ret);
+		goto err;
+	}
+
 	dev_set_drvdata(&aux_dev->dev, nvm);
 
 	return 0;

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #12 lore raw

PATCH v7 4/12 mtd: intel-dg: implement access functions

In reply to Alexander Usyskin

Implement read(), erase() and write() functions.

CC Lucas De Marchi <[email protected]>

CC Rodrigo Vivi <[email protected]>

Acked-by Miquel Raynal <[email protected]>

Co-developed-by Tomas Winkler <[email protected]>

Signed-off-by Tomas Winkler <[email protected]>

Co-developed-by Vitaly Lubart <[email protected]>

Signed-off-by Vitaly Lubart <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/mtd/devices/mtd_intel_dg.c | 197 +++++++++++++++++++++++++++++
 1 file changed, 197 insertions(+)

drivers/mtd/devices/mtd_intel_dg.c +197 -0

index ba1c720e717b..6f67cf966d05 100644
@@ -5,13 +5,16 @@
 
 #include <linux/bitfield.h>
 #include <linux/bits.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/intel_dg_nvm_aux.h>
 #include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/string.h>
 #include <linux/slab.h>
+#include <linux/sizes.h>
 #include <linux/types.h>
 
 struct intel_dg_nvm {

@@ -91,6 +94,33 @@ static inline u32 idg_nvm_read32(struct intel_dg_nvm *nvm, u32 address)
 	return ioread32(base + NVM_TRIGGER_REG);
 }
 
+static inline u64 idg_nvm_read64(struct intel_dg_nvm *nvm, u32 address)
+{
+	void __iomem *base = nvm->base;
+
+	iowrite32(address, base + NVM_ADDRESS_REG);
+
+	return readq(base + NVM_TRIGGER_REG);
+}
+
+static void idg_nvm_write32(struct intel_dg_nvm *nvm, u32 address, u32 data)
+{
+	void __iomem *base = nvm->base;
+
+	iowrite32(address, base + NVM_ADDRESS_REG);
+
+	iowrite32(data, base + NVM_TRIGGER_REG);
+}
+
+static void idg_nvm_write64(struct intel_dg_nvm *nvm, u32 address, u64 data)
+{
+	void __iomem *base = nvm->base;
+
+	iowrite32(address, base + NVM_ADDRESS_REG);
+
+	writeq(data, base + NVM_TRIGGER_REG);
+}
+
 static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_map)
 {
 	u32 flmap1;

@@ -147,6 +177,173 @@ static int idg_nvm_is_valid(struct intel_dg_nvm *nvm)
 	return 0;
 }
 
+__maybe_unused
+static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, loff_t from)
+{
+	unsigned int i;
+
+	for (i = 0; i < nvm->nregions; i++) {
+		if ((nvm->regions[i].offset + nvm->regions[i].size - 1) > from &&
+		    nvm->regions[i].offset <= from &&
+		    nvm->regions[i].size != 0)
+			break;
+	}
+
+	return i;
+}
+
+static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to,
+				       loff_t offset, size_t len, const u32 *newdata)
+{
+	u32 data = idg_nvm_read32(nvm, to);
+
+	if (idg_nvm_error(nvm))
+		return -EIO;
+
+	memcpy((u8 *)&data + offset, newdata, len);
+
+	idg_nvm_write32(nvm, to, data);
+	if (idg_nvm_error(nvm))
+		return -EIO;
+
+	return len;
+}
+
+__maybe_unused
+static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
+			 loff_t to, size_t len, const unsigned char *buf)
+{
+	size_t i;
+	size_t len8;
+	size_t len4;
+	size_t to4;
+	size_t to_shift;
+	size_t len_s = len;
+	ssize_t ret;
+
+	idg_nvm_set_region_id(nvm, region);
+
+	to4 = ALIGN_DOWN(to, sizeof(u32));
+	to_shift = min(sizeof(u32) - ((size_t)to - to4), len);
+	if (to - to4) {
+		ret = idg_nvm_rewrite_partial(nvm, to4, to - to4, to_shift, (uint32_t *)&buf[0]);
+		if (ret < 0)
+			return ret;
+
+		buf += to_shift;
+		to += to_shift;
+		len_s -= to_shift;
+	}
+
+	len8 = ALIGN_DOWN(len_s, sizeof(u64));
+	for (i = 0; i < len8; i += sizeof(u64)) {
+		u64 data;
+
+		memcpy(&data, &buf[i], sizeof(u64));
+		idg_nvm_write64(nvm, to + i, data);
+		if (idg_nvm_error(nvm))
+			return -EIO;
+	}
+
+	len4 = len_s - len8;
+	if (len4 >= sizeof(u32)) {
+		u32 data;
+
+		memcpy(&data, &buf[i], sizeof(u32));
+		idg_nvm_write32(nvm, to + i, data);
+		if (idg_nvm_error(nvm))
+			return -EIO;
+		i += sizeof(u32);
+		len4 -= sizeof(u32);
+	}
+
+	if (len4 > 0) {
+		ret = idg_nvm_rewrite_partial(nvm, to + i, 0, len4, (uint32_t *)&buf[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	return len;
+}
+
+__maybe_unused
+static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,
+			loff_t from, size_t len, unsigned char *buf)
+{
+	size_t i;
+	size_t len8;
+	size_t len4;
+	size_t from4;
+	size_t from_shift;
+	size_t len_s = len;
+
+	idg_nvm_set_region_id(nvm, region);
+
+	from4 = ALIGN_DOWN(from, sizeof(u32));
+	from_shift = min(sizeof(u32) - ((size_t)from - from4), len);
+
+	if (from - from4) {
+		u32 data = idg_nvm_read32(nvm, from4);
+
+		if (idg_nvm_error(nvm))
+			return -EIO;
+		memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift);
+		len_s -= from_shift;
+		buf += from_shift;
+		from += from_shift;
+	}
+
+	len8 = ALIGN_DOWN(len_s, sizeof(u64));
+	for (i = 0; i < len8; i += sizeof(u64)) {
+		u64 data = idg_nvm_read64(nvm, from + i);
+
+		if (idg_nvm_error(nvm))
+			return -EIO;
+
+		memcpy(&buf[i], &data, sizeof(data));
+	}
+
+	len4 = len_s - len8;
+	if (len4 >= sizeof(u32)) {
+		u32 data = idg_nvm_read32(nvm, from + i);
+
+		if (idg_nvm_error(nvm))
+			return -EIO;
+		memcpy(&buf[i], &data, sizeof(data));
+		i += sizeof(u32);
+		len4 -= sizeof(u32);
+	}
+
+	if (len4 > 0) {
+		u32 data = idg_nvm_read32(nvm, from + i);
+
+		if (idg_nvm_error(nvm))
+			return -EIO;
+		memcpy(&buf[i], &data, len4);
+	}
+
+	return len;
+}
+
+__maybe_unused
+static ssize_t
+idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_addr)
+{
+	u64 i;
+	const u32 block = 0x10;
+	void __iomem *base = nvm->base;
+
+	for (i = 0; i < len; i += SZ_4K) {
+		iowrite32(from + i, base + NVM_ADDRESS_REG);
+		iowrite32(region << 24 | block, base + NVM_ERASE_REG);
+		/* Since the writes are via sguint
+		 * we cannot do back to back erases.
+		 */
+		msleep(50);
+	}
+	return len;
+}
+
 static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *device)
 {
 	int ret;

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #13 lore raw

PATCH v7 5/12 mtd: intel-dg: register with mtd

In reply to Alexander Usyskin

Register the on-die nvm device with the mtd subsystem. Refcount nvm object on _get and _put mtd callbacks. For erase operation address and size should be 4K aligned. For write operation address and size has to be 4bytes aligned.

CC Rodrigo Vivi <[email protected]>

CC Lucas De Marchi <[email protected]>

Acked-by Miquel Raynal <[email protected]>

Co-developed-by Tomas Winkler <[email protected]>

Signed-off-by Tomas Winkler <[email protected]>

Co-developed-by Vitaly Lubart <[email protected]>

Signed-off-by Vitaly Lubart <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/mtd/devices/mtd_intel_dg.c | 230 ++++++++++++++++++++++++++++-
 1 file changed, 226 insertions(+), 4 deletions(-)

drivers/mtd/devices/mtd_intel_dg.c +226 -4

index 6f67cf966d05..4023f2ebc344 100644
@@ -5,6 +5,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/bits.h>
+#include <linux/cleanup.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/intel_dg_nvm_aux.h>

@@ -12,6 +13,8 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/sizes.h>

@@ -19,6 +22,8 @@
 
 struct intel_dg_nvm {
 	struct kref refcnt;
+	struct mtd_info mtd;
+	struct mutex lock; /* region access lock */
 	void __iomem *base;
 	size_t size;
 	unsigned int nregions;

@@ -177,7 +182,6 @@ static int idg_nvm_is_valid(struct intel_dg_nvm *nvm)
 	return 0;
 }
 
-__maybe_unused
 static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, loff_t from)
 {
 	unsigned int i;

@@ -209,7 +213,6 @@ static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to,
 	return len;
 }
 
-__maybe_unused
 static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
 			 loff_t to, size_t len, const unsigned char *buf)
 {

@@ -266,7 +269,6 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
 	return len;
 }
 
-__maybe_unused
 static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,
 			loff_t from, size_t len, unsigned char *buf)
 {

@@ -325,7 +327,6 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,
 	return len;
 }
 
-__maybe_unused
 static ssize_t
 idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_addr)
 {

@@ -414,6 +415,147 @@ static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *device)
 	return n;
 }
 
+static int intel_dg_mtd_erase(struct mtd_info *mtd, struct erase_info *info)
+{
+	struct intel_dg_nvm *nvm = mtd->priv;
+	unsigned int idx;
+	u8 region;
+	u64 addr;
+	ssize_t bytes;
+	loff_t from;
+	size_t len;
+	size_t total_len;
+
+	if (WARN_ON(!nvm))
+		return -EINVAL;
+
+	if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) {
+		dev_err(&mtd->dev, "unaligned erase %llx %llx\n",
+			info->addr, info->len);
+		info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+		return -EINVAL;
+	}
+
+	total_len = info->len;
+	addr = info->addr;
+
+	guard(mutex)(&nvm->lock);
+
+	while (total_len > 0) {
+		if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {
+			dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len);
+			info->fail_addr = addr;
+			return -ERANGE;
+		}
+
+		idx = idg_nvm_get_region(nvm, addr);
+		if (idx >= nvm->nregions) {
+			dev_err(&mtd->dev, "out of range");
+			info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+			return -ERANGE;
+		}
+
+		from = addr - nvm->regions[idx].offset;
+		region = nvm->regions[idx].id;
+		len = total_len;
+		if (len > nvm->regions[idx].size - from)
+			len = nvm->regions[idx].size - from;
+
+		dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n",
+			region, nvm->regions[idx].name, from, len);
+
+		bytes = idg_erase(nvm, region, from, len, &info->fail_addr);
+		if (bytes < 0) {
+			dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes);
+			info->fail_addr += nvm->regions[idx].offset;
+			return bytes;
+		}
+
+		addr += len;
+		total_len -= len;
+	}
+
+	return 0;
+}
+
+static int intel_dg_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+			     size_t *retlen, u_char *buf)
+{
+	struct intel_dg_nvm *nvm = mtd->priv;
+	ssize_t ret;
+	unsigned int idx;
+	u8 region;
+
+	if (WARN_ON(!nvm))
+		return -EINVAL;
+
+	idx = idg_nvm_get_region(nvm, from);
+
+	dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n",
+		nvm->regions[idx].id, nvm->regions[idx].name, from, len);
+
+	if (idx >= nvm->nregions) {
+		dev_err(&mtd->dev, "out of range");
+		return -ERANGE;
+	}
+
+	from -= nvm->regions[idx].offset;
+	region = nvm->regions[idx].id;
+	if (len > nvm->regions[idx].size - from)
+		len = nvm->regions[idx].size - from;
+
+	guard(mutex)(&nvm->lock);
+
+	ret = idg_read(nvm, region, from, len, buf);
+	if (ret < 0) {
+		dev_dbg(&mtd->dev, "read failed with %zd\n", ret);
+		return ret;
+	}
+
+	*retlen = ret;
+
+	return 0;
+}
+
+static int intel_dg_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+			      size_t *retlen, const u_char *buf)
+{
+	struct intel_dg_nvm *nvm = mtd->priv;
+	ssize_t ret;
+	unsigned int idx;
+	u8 region;
+
+	if (WARN_ON(!nvm))
+		return -EINVAL;
+
+	idx = idg_nvm_get_region(nvm, to);
+
+	dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n",
+		nvm->regions[idx].id, nvm->regions[idx].name, to, len);
+
+	if (idx >= nvm->nregions) {
+		dev_err(&mtd->dev, "out of range");
+		return -ERANGE;
+	}
+
+	to -= nvm->regions[idx].offset;
+	region = nvm->regions[idx].id;
+	if (len > nvm->regions[idx].size - to)
+		len = nvm->regions[idx].size - to;
+
+	guard(mutex)(&nvm->lock);
+
+	ret = idg_write(nvm, region, to, len, buf);
+	if (ret < 0) {
+		dev_dbg(&mtd->dev, "write failed with %zd\n", ret);
+		return ret;
+	}
+
+	*retlen = ret;
+
+	return 0;
+}
+
 static void intel_dg_nvm_release(struct kref *kref)
 {
 	struct intel_dg_nvm *nvm = container_of(kref, struct intel_dg_nvm, refcnt);

@@ -422,9 +564,80 @@ static void intel_dg_nvm_release(struct kref *kref)
 	pr_debug("freeing intel_dg nvm\n");
 	for (i = 0; i < nvm->nregions; i++)
 		kfree(nvm->regions[i].name);
+	mutex_destroy(&nvm->lock);
 	kfree(nvm);
 }
 
+static int intel_dg_mtd_get_device(struct mtd_info *mtd)
+{
+	struct mtd_info *master = mtd_get_master(mtd);
+	struct intel_dg_nvm *nvm = master->priv;
+
+	if (WARN_ON(!nvm))
+		return -EINVAL;
+	pr_debug("get mtd %s %d\n", mtd->name, kref_read(&nvm->refcnt));
+	kref_get(&nvm->refcnt);
+
+	return 0;
+}
+
+static void intel_dg_mtd_put_device(struct mtd_info *mtd)
+{
+	struct mtd_info *master = mtd_get_master(mtd);
+	struct intel_dg_nvm *nvm = master->priv;
+
+	if (WARN_ON(!nvm))
+		return;
+	pr_debug("put mtd %s %d\n", mtd->name, kref_read(&nvm->refcnt));
+	kref_put(&nvm->refcnt, intel_dg_nvm_release);
+}
+
+static int intel_dg_nvm_init_mtd(struct intel_dg_nvm *nvm, struct device *device,
+				 unsigned int nparts, bool writable_override)
+{
+	unsigned int i;
+	unsigned int n;
+	struct mtd_partition *parts = NULL;
+	int ret;
+
+	dev_dbg(device, "registering with mtd\n");
+
+	nvm->mtd.owner = THIS_MODULE;
+	nvm->mtd.dev.parent = device;
+	nvm->mtd.flags = MTD_CAP_NORFLASH | MTD_WRITEABLE;
+	nvm->mtd.type = MTD_DATAFLASH;
+	nvm->mtd.priv = nvm;
+	nvm->mtd._write = intel_dg_mtd_write;
+	nvm->mtd._read = intel_dg_mtd_read;
+	nvm->mtd._erase = intel_dg_mtd_erase;
+	nvm->mtd._get_device = intel_dg_mtd_get_device;
+	nvm->mtd._put_device = intel_dg_mtd_put_device;
+	nvm->mtd.writesize = SZ_1; /* 1 byte granularity */
+	nvm->mtd.erasesize = SZ_4K; /* 4K bytes granularity */
+	nvm->mtd.size = nvm->size;
+
+	parts = kcalloc(nvm->nregions, sizeof(*parts), GFP_KERNEL);
+	if (!parts)
+		return -ENOMEM;
+
+	for (i = 0, n = 0; i < nvm->nregions && n < nparts; i++) {
+		if (!nvm->regions[i].is_readable)
+			continue;
+		parts[n].name = nvm->regions[i].name;
+		parts[n].offset  = nvm->regions[i].offset;
+		parts[n].size = nvm->regions[i].size;
+		if (!nvm->regions[i].is_writable && !writable_override)
+			parts[n].mask_flags = MTD_WRITEABLE;
+		n++;
+	}
+
+	ret = mtd_device_register(&nvm->mtd, parts, n);
+
+	kfree(parts);
+
+	return ret;
+}
+
 static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev,
 			      const struct auxiliary_device_id *aux_dev_id)
 {

@@ -454,6 +667,7 @@ static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev,
 		return -ENOMEM;
 
 	kref_init(&nvm->refcnt);
+	mutex_init(&nvm->lock);
 
 	nvm->nregions = nregions;
 	for (n = 0, i = 0; i < INTEL_DG_NVM_REGIONS; i++) {

@@ -483,6 +697,12 @@ static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev,
 		goto err;
 	}
 
+	ret = intel_dg_nvm_init_mtd(nvm, device, ret, invm->writable_override);
+	if (ret) {
+		dev_err(device, "failed init mtd %d\n", ret);
+		goto err;
+	}
+
 	dev_set_drvdata(&aux_dev->dev, nvm);
 
 	return 0;

@@ -499,6 +719,8 @@ static void intel_dg_mtd_remove(struct auxiliary_device *aux_dev)
 	if (!nvm)
 		return;
 
+	mtd_device_unregister(&nvm->mtd);
+
 	dev_set_drvdata(&aux_dev->dev, NULL);
 
 	kref_put(&nvm->refcnt, intel_dg_nvm_release);

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #14 lore raw

PATCH v7 6/12 mtd: intel-dg: align 64bit read and write

In reply to Alexander Usyskin

GSC NVM controller HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border.

Acked-by Miquel Raynal <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/mtd/devices/mtd_intel_dg.c | 35 ++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

drivers/mtd/devices/mtd_intel_dg.c +35 -0

index 4023f2ebc344..3535f7b64429 100644
@@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
 		len_s -= to_shift;
 	}
 
+	if (!IS_ALIGNED(to, sizeof(u64)) &&
+	    ((to ^ (to + len_s)) & GENMASK(31, 10))) {
+		/*
+		 * Workaround reads/writes across 1k-aligned addresses
+		 * (start u32 before 1k, end u32 after)
+		 * as this fails on hardware.
+		 */
+		u32 data;
+
+		memcpy(&data, &buf[0], sizeof(u32));
+		idg_nvm_write32(nvm, to, data);
+		if (idg_nvm_error(nvm))
+			return -EIO;
+		buf += sizeof(u32);
+		to += sizeof(u32);
+		len_s -= sizeof(u32);
+	}
+
 	len8 = ALIGN_DOWN(len_s, sizeof(u64));
 	for (i = 0; i < len8; i += sizeof(u64)) {
 		u64 data;

@@ -295,6 +313,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,
 		from += from_shift;
 	}
 
+	if (!IS_ALIGNED(from, sizeof(u64)) &&
+	    ((from ^ (from + len_s)) & GENMASK(31, 10))) {
+		/*
+		 * Workaround reads/writes across 1k-aligned addresses
+		 * (start u32 before 1k, end u32 after)
+		 * as this fails on hardware.
+		 */
+		u32 data = idg_nvm_read32(nvm, from);
+
+		if (idg_nvm_error(nvm))
+			return -EIO;
+		memcpy(&buf[0], &data, sizeof(data));
+		len_s -= sizeof(u32);
+		buf += sizeof(u32);
+		from += sizeof(u32);
+	}
+
 	len8 = ALIGN_DOWN(len_s, sizeof(u64));
 	for (i = 0; i < len8; i += sizeof(u64)) {
 		u64 data = idg_nvm_read64(nvm, from + i);

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:37 UTC #15 lore raw

PATCH v7 7/12 mtd: intel-dg: wake card on operations

In reply to Alexander Usyskin

Enable runtime PM in mtd driver to notify graphics driver that whole card should be kept awake while nvm operations are performed through this driver.

CC Lucas De Marchi <[email protected]>

Acked-by Karthik Poosa <[email protected]>

Acked-by Miquel Raynal <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/mtd/devices/mtd_intel_dg.c | 79 +++++++++++++++++++++++++-----
 1 file changed, 67 insertions(+), 12 deletions(-)

drivers/mtd/devices/mtd_intel_dg.c +67 ~~-12~~

index 3535f7b64429..9f4bb15a03b8 100644
@@ -15,11 +15,14 @@
 #include <linux/module.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/pm_runtime.h>
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/sizes.h>
 #include <linux/types.h>
 
+#define INTEL_DG_NVM_RPM_TIMEOUT 500
+
 struct intel_dg_nvm {
 	struct kref refcnt;
 	struct mtd_info mtd;

@@ -460,6 +463,7 @@ static int intel_dg_mtd_erase(struct mtd_info *mtd, struct erase_info *info)
 	loff_t from;
 	size_t len;
 	size_t total_len;
+	int ret = 0;
 
 	if (WARN_ON(!nvm))
 		return -EINVAL;

@@ -474,20 +478,28 @@ static int intel_dg_mtd_erase(struct mtd_info *mtd, struct erase_info *info)
 	total_len = info->len;
 	addr = info->addr;
 
+	ret = pm_runtime_resume_and_get(&mtd->dev);
+	if (ret < 0) {
+		dev_err(&mtd->dev, "rpm: get failed %d\n", ret);
+		return ret;
+	}
+
 	guard(mutex)(&nvm->lock);
 
 	while (total_len > 0) {
 		if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {
 			dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len);
 			info->fail_addr = addr;
-			return -ERANGE;
+			ret = -ERANGE;
+			goto out;
 		}
 
 		idx = idg_nvm_get_region(nvm, addr);
 		if (idx >= nvm->nregions) {
 			dev_err(&mtd->dev, "out of range");
 			info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
-			return -ERANGE;
+			ret = -ERANGE;
+			goto out;
 		}
 
 		from = addr - nvm->regions[idx].offset;

@@ -503,14 +515,18 @@ static int intel_dg_mtd_erase(struct mtd_info *mtd, struct erase_info *info)
 		if (bytes < 0) {
 			dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes);
 			info->fail_addr += nvm->regions[idx].offset;
-			return bytes;
+			ret = bytes;
+			goto out;
 		}
 
 		addr += len;
 		total_len -= len;
 	}
 
-	return 0;
+out:
+	pm_runtime_mark_last_busy(&mtd->dev);
+	pm_runtime_put_autosuspend(&mtd->dev);
+	return ret;
 }
 
 static int intel_dg_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,

@@ -539,17 +555,25 @@ static int intel_dg_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
 	if (len > nvm->regions[idx].size - from)
 		len = nvm->regions[idx].size - from;
 
+	ret = pm_runtime_resume_and_get(&mtd->dev);
+	if (ret < 0) {
+		dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+		return ret;
+	}
+
 	guard(mutex)(&nvm->lock);
 
 	ret = idg_read(nvm, region, from, len, buf);
 	if (ret < 0) {
 		dev_dbg(&mtd->dev, "read failed with %zd\n", ret);
-		return ret;
+	} else {
+		*retlen = ret;
+		ret = 0;
 	}
 
-	*retlen = ret;
-
-	return 0;
+	pm_runtime_mark_last_busy(&mtd->dev);
+	pm_runtime_put_autosuspend(&mtd->dev);
+	return ret;
 }
 
 static int intel_dg_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,

@@ -578,17 +602,25 @@ static int intel_dg_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
 	if (len > nvm->regions[idx].size - to)
 		len = nvm->regions[idx].size - to;
 
+	ret = pm_runtime_resume_and_get(&mtd->dev);
+	if (ret < 0) {
+		dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+		return ret;
+	}
+
 	guard(mutex)(&nvm->lock);
 
 	ret = idg_write(nvm, region, to, len, buf);
 	if (ret < 0) {
 		dev_dbg(&mtd->dev, "write failed with %zd\n", ret);
-		return ret;
+	} else {
+		*retlen = ret;
+		ret = 0;
 	}
 
-	*retlen = ret;
-
-	return 0;
+	pm_runtime_mark_last_busy(&mtd->dev);
+	pm_runtime_put_autosuspend(&mtd->dev);
+	return ret;
 }
 
 static void intel_dg_nvm_release(struct kref *kref)

@@ -670,6 +702,15 @@ static int intel_dg_nvm_init_mtd(struct intel_dg_nvm *nvm, struct device *device
 
 	kfree(parts);
 
+	if (ret)
+		goto out;
+
+	devm_pm_runtime_enable(&nvm->mtd.dev);
+
+	pm_runtime_set_autosuspend_delay(&nvm->mtd.dev, INTEL_DG_NVM_RPM_TIMEOUT);
+	pm_runtime_use_autosuspend(&nvm->mtd.dev);
+
+out:
 	return ret;
 }

@@ -719,6 +760,17 @@ static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev,
 	}
 	nvm->nregions = n; /* in case where kasprintf fail */
 
+	devm_pm_runtime_enable(device);
+
+	pm_runtime_set_autosuspend_delay(device, INTEL_DG_NVM_RPM_TIMEOUT);
+	pm_runtime_use_autosuspend(device);
+
+	ret = pm_runtime_resume_and_get(device);
+	if (ret < 0) {
+		dev_err(device, "rpm: get failed %d\n", ret);
+		goto err_norpm;
+	}
+
 	nvm->base = devm_ioremap_resource(device, &invm->bar);
 	if (IS_ERR(nvm->base)) {
 		dev_err(device, "mmio not mapped\n");

@@ -740,9 +792,12 @@ static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev,
 
 	dev_set_drvdata(&aux_dev->dev, nvm);
 
+	pm_runtime_put(device);
 	return 0;
 
 err:
+	pm_runtime_put(device);
+err_norpm:
 	kref_put(&nvm->refcnt, intel_dg_nvm_release);
 	return ret;
 }

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:38 UTC #16 lore raw

PATCH v7 8/12 drm/i915/nvm: add nvm device for discrete graphics

In reply to Alexander Usyskin

Enable access to internal non-volatile memory on DGFX devices via a child device.
The nvm child device is exposed via auxiliary bus.

CC Lucas De Marchi <[email protected]>

Reviewed-by Rodrigo Vivi <[email protected]>

Co-developed-by Tomas Winkler <[email protected]>

Signed-off-by Tomas Winkler <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/gpu/drm/i915/Makefile      |  4 ++
 drivers/gpu/drm/i915/i915_driver.c |  6 ++
 drivers/gpu/drm/i915/i915_drv.h    |  3 +
 drivers/gpu/drm/i915/i915_reg.h    |  1 +
 drivers/gpu/drm/i915/intel_nvm.c   | 92 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_nvm.h   | 15 +++++
 6 files changed, 121 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.c
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.h

drivers/gpu/drm/i915/Makefile +4 -0

index ed05b131ed3a..58e37d9e4fc6 100644
@@ -213,6 +213,10 @@ i915-y += \
 i915-y += \
 	gt/intel_gsc.o
 
+# graphics nvm device (DGFX) support
+i915-y += \
+	intel_nvm.o
+
 # graphics hardware monitoring (HWMON) support
 i915-$(CONFIG_HWMON) += \
 	i915_hwmon.o

drivers/gpu/drm/i915/i915_driver.c +6 -0

index ce3cc93ea211..1eb42ef3d44a 100644
@@ -83,6 +83,8 @@
 #include "soc/intel_dram.h"
 #include "soc/intel_gmch.h"
 
+#include "intel_nvm.h"
+
 #include "i915_debugfs.h"
 #include "i915_driver.h"
 #include "i915_drm_client.h"

@@ -646,6 +648,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
 	/* Depends on sysfs having been initialized */
 	i915_perf_register(dev_priv);
 
+	intel_nvm_init(dev_priv);
+
 	for_each_gt(gt, dev_priv, i)
 		intel_gt_driver_register(gt);

@@ -686,6 +690,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 
 	i915_hwmon_unregister(dev_priv);
 
+	intel_nvm_fini(dev_priv);
+
 	i915_perf_unregister(dev_priv);
 	i915_pmu_unregister(dev_priv);

drivers/gpu/drm/i915/i915_drv.h +3 -0

index ffc346379cc2..d3e257a9538c 100644
@@ -67,6 +67,7 @@
 struct drm_i915_clock_gating_funcs;
 struct vlv_s0ix_state;
 struct intel_pxp;
+struct intel_dg_nvm_dev;
 
 #define GEM_QUIRK_PIN_SWIZZLED_PAGES	BIT(0)

@@ -314,6 +315,8 @@ struct drm_i915_private {
 
 	struct i915_perf perf;
 
+	struct intel_dg_nvm_dev *nvm;
+
 	struct i915_hwmon *hwmon;
 
 	struct intel_gt *gt[I915_MAX_GT];

drivers/gpu/drm/i915/i915_reg.h +1 -0

index c5064eebe063..809123975e93 100644
@@ -321,6 +321,7 @@
 #define DG2_GSC_HECI2_BASE	0x00374000
 #define MTL_GSC_HECI1_BASE	0x00116000
 #define MTL_GSC_HECI2_BASE	0x00117000
+#define GEN12_GUNIT_NVM_BASE	0x00102040
 
 #define HECI_H_CSR(base)	_MMIO((base) + 0x4)
 #define   HECI_H_CSR_IE		REG_BIT(0)

drivers/gpu/drm/i915/intel_nvm.c new file +92 -0

92 lines not on this page · raw message

drivers/gpu/drm/i915/intel_nvm.h new file +15 -0

new file mode 100644
index 000000000000..7bc3d1114a3f
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_NVM_H__
+#define __INTEL_NVM_H__
+
+struct drm_i915_private;
+
+void intel_nvm_init(struct drm_i915_private *i915);
+
+void intel_nvm_fini(struct drm_i915_private *i915);
+
+#endif /* __INTEL_NVM_H__ */

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:38 UTC #17 lore raw

PATCH v7 9/12 drm/i915/nvm: add support for access mode

In reply to Alexander Usyskin

Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/intel_nvm.c +24 -1

index 75d3ebe669ff..dd3999c934a7 100644
@@ -10,6 +10,7 @@
 #include "intel_nvm.h"
 
 #define GEN12_GUNIT_NVM_SIZE 0x80
+#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3)
 
 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = {
 	[0] = { .name = "DESCRIPTOR", },

@@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev)
 {
 }
 
+static bool i915_nvm_writable_override(struct drm_i915_private *i915)
+{
+	resource_size_t base;
+	bool writable_override;
+
+	if (IS_DG1(i915)) {
+		base = DG1_GSC_HECI2_BASE;
+	} else if (IS_DG2(i915)) {
+		base = DG2_GSC_HECI2_BASE;
+	} else {
+		drm_err(&i915->drm, "Unknown platform\n");
+		return true;
+	}
+
+	writable_override =
+		!(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) &
+		  HECI_FW_STATUS_2_NVM_ACCESS_MODE);
+	if (writable_override)
+		drm_info(&i915->drm, "NVM access overridden by jumper\n");
+	return writable_override;
+}
+
 void intel_nvm_init(struct drm_i915_private *i915)
 {
 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);

@@ -43,7 +66,7 @@ void intel_nvm_init(struct drm_i915_private *i915)
 
 	nvm = i915->nvm;
 
-	nvm->writeable_override = true;
+	nvm->writable_override = i915_nvm_writable_override(i915);
 	nvm->bar.parent = &pdev->resource[0];
 	nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
 	nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:38 UTC #18 lore raw

PATCH v7 10/12 drm/xe/nvm: add on-die non-volatile memory device

In reply to Alexander Usyskin

Enable access to internal non-volatile memory on DGFX with GSC/CSC devices via a child device.
The nvm child device is exposed via auxiliary bus.

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/gpu/drm/xe/Makefile          |   1 +
 drivers/gpu/drm/xe/xe_device.c       |   5 ++
 drivers/gpu/drm/xe/xe_device_types.h |   6 ++
 drivers/gpu/drm/xe/xe_nvm.c          | 101 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_nvm.h          |  15 ++++
 drivers/gpu/drm/xe/xe_pci.c          |   6 ++
 6 files changed, 134 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.c
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.h

drivers/gpu/drm/xe/Makefile +1 -0

index 9699b08585f7..5d5f70b86cf2 100644
@@ -80,6 +80,7 @@ xe-y += xe_bb.o \
 	xe_mmio.o \
 	xe_mocs.o \
 	xe_module.o \
+	xe_nvm.o \
 	xe_oa.o \
 	xe_observation.o \
 	xe_pat.o \

drivers/gpu/drm/xe/xe_device.c +5 -0

index 1ffb7d1f6be6..b6905c114acf 100644
@@ -44,6 +44,7 @@
 #include "xe_memirq.h"
 #include "xe_mmio.h"
 #include "xe_module.h"
+#include "xe_nvm.h"
 #include "xe_oa.h"
 #include "xe_observation.h"
 #include "xe_pat.h"

@@ -885,6 +886,8 @@ int xe_device_probe(struct xe_device *xe)
 			return err;
 	}
 
+	xe_nvm_init(xe);
+
 	err = xe_heci_gsc_init(xe);
 	if (err)
 		return err;

@@ -938,6 +941,8 @@ void xe_device_remove(struct xe_device *xe)
 {
 	xe_display_unregister(xe);
 
+	xe_nvm_fini(xe);
+
 	drm_dev_unplug(&xe->drm);
 }

drivers/gpu/drm/xe/xe_device_types.h +6 -0

index 1334174388af..326aa6a8cdbb 100644
@@ -36,6 +36,7 @@
 #include "intel_display_device.h"
 #endif
 
+struct intel_dg_nvm_dev;
 struct xe_ggtt;
 struct xe_pat_ops;
 struct xe_pxp;

@@ -318,6 +319,8 @@ struct xe_device {
 		u8 has_fan_control:1;
 		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
 		u8 has_flat_ccs:1;
+		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
+		u8 has_gsc_nvm:1;
 		/** @info.has_heci_cscfi: device has heci cscfi */
 		u8 has_heci_cscfi:1;
 		/** @info.has_heci_gscfi: device has heci gscfi */

@@ -526,6 +529,9 @@ struct xe_device {
 	/** @heci_gsc: graphics security controller */
 	struct xe_heci_gsc heci_gsc;
 
+	/** @nvm: discrete graphics non-volatile memory */
+	struct intel_dg_nvm_dev *nvm;
+
 	/** @oa: oa observation subsystem */
 	struct xe_oa oa;

drivers/gpu/drm/xe/xe_nvm.c new file +101 -0

101 lines not on this page · raw message

drivers/gpu/drm/xe/xe_nvm.h new file +15 -0

new file mode 100644
index 000000000000..5487764c180f
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2025 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __XE_NVM_H__
+#define __XE_NVM_H__
+
+struct xe_device;
+
+void xe_nvm_init(struct xe_device *xe);
+
+void xe_nvm_fini(struct xe_device *xe);
+
+#endif

drivers/gpu/drm/xe/xe_pci.c +6 -0

index 88138a3fcf50..65a68ee97bb2 100644
@@ -63,6 +63,7 @@ struct xe_device_desc {
 
 	u8 has_display:1;
 	u8 has_fan_control:1;
+	u8 has_gsc_nvm:1;
 	u8 has_heci_gscfi:1;
 	u8 has_heci_cscfi:1;
 	u8 has_llc:1;

@@ -266,6 +267,7 @@ static const struct xe_device_desc dg1_desc = {
 	PLATFORM(DG1),
 	.dma_mask_size = 39,
 	.has_display = true,
+	.has_gsc_nvm = 1,
 	.has_heci_gscfi = 1,
 	.require_force_probe = true,
 };

@@ -277,6 +279,7 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
 #define DG2_FEATURES \
 	DGFX_FEATURES, \
 	PLATFORM(DG2), \
+	.has_gsc_nvm = 1, \
 	.has_heci_gscfi = 1, \
 	.subplatforms = (const struct xe_subplatform_desc[]) { \
 		{ XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \

@@ -312,6 +315,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
 	PLATFORM(PVC),
 	.dma_mask_size = 52,
 	.has_display = false,
+	.has_gsc_nvm = 1,
 	.has_heci_gscfi = 1,
 	.max_remote_tiles = 1,
 	.require_force_probe = true,

@@ -339,6 +343,7 @@ static const struct xe_device_desc bmg_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_gsc_nvm = 1,
 	.has_heci_cscfi = 1,
 };

@@ -579,6 +584,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.dma_mask_size = desc->dma_mask_size;
 	xe->info.is_dgfx = desc->is_dgfx;
 	xe->info.has_fan_control = desc->has_fan_control;
+	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
 	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
 	xe->info.has_llc = desc->has_llc;

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:38 UTC #19 lore raw

PATCH v7 11/12 drm/xe/nvm: add support for access mode

In reply to Alexander Usyskin

Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/gpu/drm/xe/regs/xe_gsc_regs.h |  4 +++
 drivers/gpu/drm/xe/xe_heci_gsc.c      |  5 +---
 drivers/gpu/drm/xe/xe_nvm.c           | 37 ++++++++++++++++++++++++++-
 3 files changed, 41 insertions(+), 5 deletions(-)

drivers/gpu/drm/xe/regs/xe_gsc_regs.h +4 -0

index 7702364b65f1..9b66cc972a63 100644
@@ -16,6 +16,10 @@
 #define MTL_GSC_HECI1_BASE	0x00116000
 #define MTL_GSC_HECI2_BASE	0x00117000
 
+#define DG1_GSC_HECI2_BASE	0x00259000
+#define PVC_GSC_HECI2_BASE	0x00285000
+#define DG2_GSC_HECI2_BASE	0x00374000
+
 #define HECI_H_CSR(base)	XE_REG((base) + 0x4)
 #define   HECI_H_CSR_IE		REG_BIT(0)
 #define   HECI_H_CSR_IS		REG_BIT(1)

drivers/gpu/drm/xe/xe_heci_gsc.c +1 -4

index 27d11e06a82b..6d7b62724126 100644
@@ -11,15 +11,12 @@
 #include "xe_device_types.h"
 #include "xe_drv.h"
 #include "xe_heci_gsc.h"
+#include "regs/xe_gsc_regs.h"
 #include "xe_platform_types.h"
 #include "xe_survivability_mode.h"
 
 #define GSC_BAR_LENGTH  0x00000FFC
 
-#define DG1_GSC_HECI2_BASE			0x259000
-#define PVC_GSC_HECI2_BASE			0x285000
-#define DG2_GSC_HECI2_BASE			0x374000
-
 static void heci_gsc_irq_mask(struct irq_data *d)
 {
 	/* generic irq handling */

drivers/gpu/drm/xe/xe_nvm.c +36 -1

index 26de7d4472c8..8aec20bc629a 100644
@@ -6,8 +6,11 @@
 #include <linux/intel_dg_nvm_aux.h>
 #include <linux/pci.h>
 
+#include "xe_device.h"
 #include "xe_device_types.h"
+#include "xe_mmio.h"
 #include "xe_nvm.h"
+#include "regs/xe_gsc_regs.h"
 #include "xe_sriov.h"
 
 #define GEN12_GUNIT_NVM_BASE 0x00102040

@@ -25,6 +28,38 @@ static void xe_nvm_release_dev(struct device *dev)
 {
 }
 
+static bool xe_nvm_writable_override(struct xe_device *xe)
+{
+	struct xe_gt *gt = xe_root_mmio_gt(xe);
+	resource_size_t base;
+	bool writable_override;
+
+	switch (xe->info.platform) {
+	case XE_BATTLEMAGE:
+		base = DG2_GSC_HECI2_BASE;
+		break;
+	case XE_PVC:
+		base = PVC_GSC_HECI2_BASE;
+		break;
+	case XE_DG2:
+		base = DG2_GSC_HECI2_BASE;
+		break;
+	case XE_DG1:
+		base = DG1_GSC_HECI2_BASE;
+		break;
+	default:
+		drm_err(&xe->drm, "Unknown platform\n");
+		return true;
+	}
+
+	writable_override =
+		!(xe_mmio_read32(&gt->mmio, HECI_FWSTS2(base)) &
+		  HECI_FW_STATUS_2_NVM_ACCESS_MODE);
+	if (writable_override)
+		drm_info(&xe->drm, "NVM access overridden by jumper\n");
+	return writable_override;
+}
+
 void xe_nvm_init(struct xe_device *xe)
 {
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);

@@ -49,7 +84,7 @@ void xe_nvm_init(struct xe_device *xe)
 
 	nvm = xe->nvm;
 
-	nvm->writeable_override = false;
+	nvm->writable_override = xe_nvm_writable_override(xe);
 	nvm->bar.parent = &pdev->resource[0];
 	nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
 	nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;

Signature · 1 line

2.43.0

Alexander Usyskin

author maintainer

2025-03-26 15:38 UTC #20 lore raw

PATCH v7 12/12 drm/xe/nvm: add support for non-posted erase

In reply to Alexander Usyskin

From: "Abliyev, Reuven" <[email protected]>

Erase command is slow on discrete graphics storage and may overshot PCI completion timeout.
BMG introduces the ability to have non-posted erase. Add driver support for non-posted erase with polling for erase completion.

Signed-off-by Abliyev, Reuven <[email protected]>

Signed-off-by Alexander Usyskin <[email protected]>

---
 drivers/gpu/drm/xe/xe_nvm.c        | 25 +++++++++++++++++
 drivers/mtd/devices/mtd_intel_dg.c | 43 ++++++++++++++++++++++++++++--
 include/linux/intel_dg_nvm_aux.h   |  2 ++
 3 files changed, 68 insertions(+), 2 deletions(-)

drivers/gpu/drm/xe/xe_nvm.c +25 -0

index 8aec20bc629a..dd91f2e37661 100644
@@ -14,7 +14,15 @@
 #include "xe_sriov.h"
 
 #define GEN12_GUNIT_NVM_BASE 0x00102040
+#define GEN12_DEBUG_NVM_BASE 0x00101018
+
+#define GEN12_CNTL_PROTECTED_NVM_REG 0x0010100C
+
 #define GEN12_GUNIT_NVM_SIZE 0x80
+#define GEN12_DEBUG_NVM_SIZE 0x4
+
+#define NVM_NON_POSTED_ERASE_CHICKEN_BIT BIT(13)
+
 #define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3)
 
 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = {

@@ -28,6 +36,16 @@ static void xe_nvm_release_dev(struct device *dev)
 {
 }
 
+static bool xe_nvm_non_posted_erase(struct xe_device *xe)
+{
+	struct xe_gt *gt = xe_root_mmio_gt(xe);
+
+	if (xe->info.platform != XE_BATTLEMAGE)
+		return false;
+	return !(xe_mmio_read32(&gt->mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) &
+		 NVM_NON_POSTED_ERASE_CHICKEN_BIT);
+}
+
 static bool xe_nvm_writable_override(struct xe_device *xe)
 {
 	struct xe_gt *gt = xe_root_mmio_gt(xe);

@@ -85,6 +103,7 @@ void xe_nvm_init(struct xe_device *xe)
 	nvm = xe->nvm;
 
 	nvm->writable_override = xe_nvm_writable_override(xe);
+	nvm->non_posted_erase = xe_nvm_non_posted_erase(xe);
 	nvm->bar.parent = &pdev->resource[0];
 	nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
 	nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;

@@ -92,6 +111,12 @@ void xe_nvm_init(struct xe_device *xe)
 	nvm->bar.desc = IORES_DESC_NONE;
 	nvm->regions = regions;
 
+	nvm->bar2.parent = &pdev->resource[0];
+	nvm->bar2.start = GEN12_DEBUG_NVM_BASE + pdev->resource[0].start;
+	nvm->bar2.end = nvm->bar2.start + GEN12_DEBUG_NVM_SIZE - 1;
+	nvm->bar2.flags = IORESOURCE_MEM;
+	nvm->bar2.desc = IORES_DESC_NONE;
+
 	aux_dev = &nvm->aux_dev;
 
 	aux_dev->name = "nvm";

drivers/mtd/devices/mtd_intel_dg.c +41 -2

91 lines not on this page · raw message

include/linux/intel_dg_nvm_aux.h +2 -0

index 68df634c994c..bee25dfc6982 100644
@@ -17,7 +17,9 @@ struct intel_dg_nvm_region {
 struct intel_dg_nvm_dev {
 	struct auxiliary_device aux_dev;
 	bool writable_override;
+	bool non_posted_erase;
 	struct resource bar;
+	struct resource bar2;
 	const struct intel_dg_nvm_region *regions;
 };

Signature · 1 line

2.43.0

Patchwork

2025-03-26 16:09 UTC #21 lore raw

✗ Fi.CI.CHECKPATCH: warning for mtd: add driver for Intel discrete graphics (rev7)

In reply to Alexander Usyskin

== Series Details ==

Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : warning

== Summary ==

Error: dim checkpatch failed
5a696b562b94 mtd: core: always create master device
a547710a3913 mtd: add driver for intel graphics non-volatile memory device
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #69:
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 202 lines checked
f7c8c021e9e2 mtd: intel-dg: implement region enumeration
9e11cadfdcce mtd: intel-dg: implement access functions
f391936fe856 mtd: intel-dg: register with mtd
21605f9128be mtd: intel-dg: align 64bit read and write
9de54cc563a7 mtd: intel-dg: wake card on operations
23d50cc07f68 drm/i915/nvm: add nvm device for discrete graphics
-:96: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #96:
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 163 lines checked
7133bd3a2ce8 drm/i915/nvm: add support for access mode
26d059f7594e drm/xe/nvm: add on-die non-volatile memory device
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #87:
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 212 lines checked 3f719027642f drm/xe/nvm: add support for access mode b01595c0824d drm/xe/nvm: add support for non-posted erase -:121: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #121: FILE: drivers/mtd/devices/mtd_intel_dg.c:392:
+ while (!(reg & NVM_NON_POSTED_ERASE_DONE) &&
+ ++iter < NVM_NON_POSTED_ERASE_DONE_ITER) {

-:122: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see function description of msleep(). #122: FILE: drivers/mtd/devices/mtd_intel_dg.c:393:
+ msleep(10);

total: 0 errors, 1 warnings, 1 checks, 150 lines checked

Patchwork

2025-03-26 16:09 UTC #22 lore raw

✗ Fi.CI.SPARSE: warning for mtd: add driver for Intel discrete graphics (rev7)

In reply to Alexander Usyskin

== Series Details ==

Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Patchwork

2025-03-26 16:32 UTC #23 lore raw

✓ i915.CI.BAT: success for mtd: add driver for Intel discrete graphics (rev7)

In reply to Alexander Usyskin

== Series Details ==

Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16321 -> Patchwork_140306v7
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/index.html

Participating hosts (40 -> 40)
------------------------------

Additional (2): bat-jsl-4 fi-pnv-d510
Missing (2): bat-twl-1 fi-snb-2520m

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_140306v7:

### IGT changes ###

#### Suppressed ####

The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.

* igt@i915_module_load@load:
- {bat-jsl-4}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-jsl-4/igt@[email protected]

Known issues
------------

Here are the changes found in Patchwork_140306v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@dmabuf@all-tests:
- fi-pnv-d510: NOTRUN -> [INCOMPLETE][2] ([i915#12904]) +1 other test incomplete
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/fi-pnv-d510/igt@[email protected]

* igt@dmabuf@all-tests@dma_fence_chain:
- fi-bsw-nick: [PASS][3] -> [INCOMPLETE][4] ([i915#12904]) +1 other test incomplete
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html

* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/bat-mtlp-9/igt@i915_selftest@[email protected]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-mtlp-9/igt@i915_selftest@[email protected]

* igt@kms_chamelium_edid@vga-edid-read:
- bat-dg2-13: NOTRUN -> [SKIP][7] ([Intel XE#484] / [i915#4550]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-dg2-13/igt@[email protected]

* igt@kms_psr@psr-primary-mmap-gtt:
- fi-pnv-d510: NOTRUN -> [SKIP][8] +33 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/fi-pnv-d510/igt@[email protected]

#### Possible fixes ####

* igt@dmabuf@all-tests:
- bat-apl-1: [INCOMPLETE][9] ([i915#12904]) -> [PASS][10] +1 other test pass
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/bat-apl-1/igt@[email protected]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-apl-1/igt@[email protected]

* igt@i915_selftest@live:
- bat-adlp-11: [ABORT][11] ([i915#13696]) -> [PASS][12] +1 other test pass
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/bat-adlp-11/igt@[email protected]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-adlp-11/igt@[email protected]

* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [DMESG-FAIL][13] ([i915#12061]) -> [PASS][14] +1 other test pass
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/bat-mtlp-6/igt@i915_selftest@[email protected]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-mtlp-6/igt@i915_selftest@[email protected]

* igt@kms_chamelium_edid@dp-edid-read:
- bat-dg2-13: [ABORT][15] ([i915#13940]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/bat-dg2-13/igt@[email protected]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/bat-dg2-13/igt@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[Intel XE#484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/484
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
[i915#13696]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13696
[i915#13940]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13940
[i915#4550]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4550

Build changes
-------------

* Linux: CI_DRM_16321 -> Patchwork_140306v7

CI-20190529: 20190529
CI_DRM_16321: 14c330bc015ded4a1f1dd1f5aeb8617077aaa7e8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8284: 8284
Patchwork_140306v7: 14c330bc015ded4a1f1dd1f5aeb8617077aaa7e8 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/index.html

Patchwork

2025-03-26 18:55 UTC #24 lore raw

✗ i915.CI.Full: failure for mtd: add driver for Intel discrete graphics (rev7)

In reply to Alexander Usyskin

== Series Details ==

Series: mtd: add driver for Intel discrete graphics (rev7)
URL : https://patchwork.freedesktop.org/series/140306/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16321_full -> Patchwork_140306v7_full
====================================================

Summary
-------

**FAILURE**

Serious unknown changes coming with Patchwork_140306v7_full absolutely need to be verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_140306v7_full, please notify your bug team ([email protected]) to allow them to document this new failure mode, which will reduce false positives in CI.

Participating hosts (10 -> 10)
------------------------------

No changes in participating hosts

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_140306v7_full:

### IGT changes ###

#### Possible regressions ####

* igt@kms_pm_dc@dc5-dpms:
- shard-dg2-9: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_vblank@ts-continuation-dpms-suspend:
- shard-rkl: [PASS][2] -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-7/igt@[email protected]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-3/igt@[email protected]

* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [INCOMPLETE][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-3/igt@kms_vblank@[email protected]

Known issues
------------

Here are the changes found in Patchwork_140306v7_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][6] ([i915#8411])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2-9: NOTRUN -> [SKIP][7] ([i915#8411])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@debugfs_test@basic-hwmon:
- shard-tglu-1: NOTRUN -> [SKIP][8] ([i915#9318])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@device_reset@cold-reset-bound:
- shard-dg2-9: NOTRUN -> [SKIP][9] ([i915#11078])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@drm_fdinfo@all-busy-check-all:
- shard-dg2-9: NOTRUN -> [SKIP][10] ([i915#8414]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8414]) +15 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@drm_fdinfo@[email protected]

* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#3281]) +5 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@gem_ccs@block-multicopy-compressed:
- shard-tglu: NOTRUN -> [SKIP][13] ([i915#9323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#9323])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@gem_ccs@large-ctrl-surf-copy:
- shard-tglu-1: NOTRUN -> [SKIP][15] ([i915#13008])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@gem_close_race@multigpu-basic-threads:
- shard-dg2-9: NOTRUN -> [SKIP][16] ([i915#7697])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-tglu: NOTRUN -> [SKIP][17] ([i915#6335])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@gem_create@create-ext-set-pat:
- shard-tglu: NOTRUN -> [SKIP][18] ([i915#8562])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2-9: NOTRUN -> [SKIP][19] ([i915#8555])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][20] ([i915#8555])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][21] ([i915#1099])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-snb2/igt@[email protected]

* igt@gem_ctx_sseu@engines:
- shard-dg2-9: NOTRUN -> [SKIP][22] ([i915#280])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_ctx_sseu@mmap-args:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#280])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@gem_eio@kms:
- shard-tglu-1: NOTRUN -> [DMESG-WARN][24] ([i915#13363])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@gem_eio@wait-immediate:
- shard-mtlp: [PASS][25] -> [ABORT][26] ([i915#13193]) +1 other test abort
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-mtlp-6/igt@[email protected]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-7/igt@[email protected]

* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#4771])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_exec_balancer@bonded-true-hang:
- shard-mtlp: NOTRUN -> [SKIP][28] ([i915#4812])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_exec_balancer@parallel:
- shard-rkl: NOTRUN -> [SKIP][29] ([i915#4525])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@gem_exec_balancer@parallel-balancer:
- shard-tglu: NOTRUN -> [SKIP][30] ([i915#4525])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@gem_exec_big@single:
- shard-tglu: [PASS][31] -> [ABORT][32] ([i915#11713])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-tglu-8/igt@[email protected]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-2/igt@[email protected]

* igt@gem_exec_fence@submit3:
- shard-dg2-9: NOTRUN -> [SKIP][33] ([i915#4812]) +2 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2-9: NOTRUN -> [SKIP][34] ([i915#3539] / [i915#4852])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_exec_flush@basic-uc-rw-default:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3539] / [i915#4852])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_exec_flush@basic-wb-rw-default:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#3539] / [i915#4852])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_exec_reloc@basic-gtt-read:
- shard-dg2-9: NOTRUN -> [SKIP][37] ([i915#3281]) +6 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_exec_reloc@basic-softpin:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#3281])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#3281]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_exec_reloc@basic-write-gtt-noreloc:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#3281]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_exec_schedule@deep@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][41] ([i915#4537])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@gem_exec_schedule@[email protected]

* igt@gem_exec_schedule@reorder-wide:
- shard-dg2-9: NOTRUN -> [SKIP][42] ([i915#4537] / [i915#4812])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_exec_schedule@semaphore-power:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4537] / [i915#4812])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_fence_thrash@bo-write-verify-y:
- shard-dg2-9: NOTRUN -> [SKIP][44] ([i915#4860])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#4860]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#4860])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_huc_copy@huc-copy:
- shard-tglu-1: NOTRUN -> [SKIP][47] ([i915#2190])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@gem_lmem_evict@dontneed-evict-race:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4613])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_lmem_swapping@basic:
- shard-glk: NOTRUN -> [SKIP][49] ([i915#4613])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk2/igt@[email protected]

* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-tglu: NOTRUN -> [SKIP][50] ([i915#4613])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@gem_lmem_swapping@parallel-multi:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#4613]) +3 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@gem_lmem_swapping@verify-random:
- shard-tglu-1: NOTRUN -> [SKIP][52] ([i915#4613]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-dg1: NOTRUN -> [SKIP][53] ([i915#4077]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_mmap_gtt@hang:
- shard-dg2-9: NOTRUN -> [SKIP][54] ([i915#4077]) +11 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_mmap_wc@read-write-distinct:
- shard-dg2-9: NOTRUN -> [SKIP][55] ([i915#4083]) +4 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_mmap_wc@write-prefaulted:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4083]) +4 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_mmap_wc@write-read:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#4083]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_partial_pwrite_pread@reads:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3282]) +4 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2-9: NOTRUN -> [SKIP][59] ([i915#3282])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_pread@exhaustion:
- shard-tglu-1: NOTRUN -> [WARN][60] ([i915#2658])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@gem_pwrite@basic-random:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#3282])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_pxp@create-protected-buffer:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#4270])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2-9: NOTRUN -> [SKIP][63] ([i915#4270]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#4270])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-rkl: [PASS][65] -> [TIMEOUT][66] ([i915#12917] / [i915#12964]) +1 other test timeout
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-8/igt@[email protected]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@gem_readwrite@read-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#3282]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-glk: NOTRUN -> [SKIP][68] +89 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk4/igt@[email protected]

* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#8428])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2-9: NOTRUN -> [SKIP][70] ([i915#5190] / [i915#8428]) +3 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#5190] / [i915#8428]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2-9: NOTRUN -> [SKIP][72] ([i915#4079])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#3282]) +3 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@gem_set_tiling_vs_pwrite.html

* igt@gem_softpin@evict-snoop-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#4885])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_tiled_blits@basic:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#4077]) +8 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@gem_tiled_partial_pwrite_pread@reads:
- shard-mtlp: NOTRUN -> [SKIP][76] ([i915#4077]) +4 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@gem_tiled_pread_basic:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4079])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@gem_tiled_pread_basic.html

* igt@gem_unfence_active_buffers:
- shard-dg2-9: NOTRUN -> [SKIP][78] ([i915#4879])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@gem_unfence_active_buffers.html

* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2-9: NOTRUN -> [SKIP][79] ([i915#3297])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gem_userptr_blits@forbidden-operations:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#3282] / [i915#3297])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#3297] / [i915#4880])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_userptr_blits@map-fixed-invalidate-overlap:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#3297]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_userptr_blits@readonly-unsync:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#3297])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#3297])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglu-1: NOTRUN -> [SKIP][85] ([i915#3297]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3297])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gen9_exec_parse@allowed-single:
- shard-dg2-9: NOTRUN -> [SKIP][87] ([i915#2856]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglu: NOTRUN -> [SKIP][88] ([i915#2527] / [i915#2856])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]
- shard-mtlp: NOTRUN -> [SKIP][89] ([i915#2856])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@gen9_exec_parse@bb-chained:
- shard-tglu-1: NOTRUN -> [SKIP][90] ([i915#2527] / [i915#2856]) +2 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#2856])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gen9_exec_parse@bb-start-far:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#2527]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#2527])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@i915_fb_tiling@basic-x-tiling:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#13786])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@i915_pm_rps@min-max-config-idle:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#11681] / [i915#6621])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@i915_pm_rps@min-max-config-loaded:
- shard-dg2-9: NOTRUN -> [SKIP][96] ([i915#11681] / [i915#6621])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@i915_pm_rps@thresholds-park:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#11681])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@i915_pm_sseu@full-enable:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#4387])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@i915_query@hwconfig_table:
- shard-tglu-1: NOTRUN -> [SKIP][99] ([i915#6245])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@i915_query@hwconfig_table.html

* igt@i915_selftest@live@workarounds:
- shard-mtlp: [PASS][100] -> [DMESG-FAIL][101] ([i915#12061]) +1 other test dmesg-fail
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-mtlp-1/igt@i915_selftest@[email protected]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@i915_selftest@[email protected]

* igt@i915_selftest@mock@memory_region:
- shard-rkl: NOTRUN -> [DMESG-WARN][102] ([i915#9311]) +1 other test dmesg-warn
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@i915_selftest@mock@memory_region.html

* igt@i915_suspend@forcewake:
- shard-glk: NOTRUN -> [INCOMPLETE][103] ([i915#4817])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk2/igt@[email protected]

* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#4212])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#4212])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_async_flips@alternate-sync-async-flip:
- shard-glk: [PASS][106] -> [FAIL][107] ([i915#10991] / [i915#12766])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk9/igt@[email protected]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk6/igt@[email protected]

* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-2:
- shard-glk: [PASS][108] -> [FAIL][109] ([i915#10991])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk9/igt@kms_async_flips@[email protected]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk6/igt@kms_async_flips@[email protected]

* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-4-y-rc-ccs-cc:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#8709]) +7 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-14/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-4-y-rc-ccs-cc.html

* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-1-y-rc-ccs-cc:
- shard-tglu: NOTRUN -> [SKIP][111] ([i915#8709]) +3 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-1-y-rc-ccs-cc.html

* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-d-edp-1-4-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][112] ([i915#8709]) +7 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-d-edp-1-4-mc-ccs.html

* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#8709]) +7 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@kms_async_flips@[email protected]

* igt@kms_async_flips@invalid-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][114] ([i915#12967] / [i915#6228])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-dg2-9: NOTRUN -> [SKIP][115] ([i915#12967])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-tglu: NOTRUN -> [SKIP][116] ([i915#9531])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#1769] / [i915#3555])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
- shard-tglu-1: NOTRUN -> [SKIP][118] ([i915#1769] / [i915#3555])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#5286]) +3 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#4538] / [i915#5286])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-dg2-9: NOTRUN -> [SKIP][121] +5 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_big_fb@4-tiled-addfb:
- shard-tglu-1: NOTRUN -> [SKIP][122] ([i915#5286]) +4 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][123] ([i915#5286]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [PASS][124] -> [FAIL][125] ([i915#5138])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-mtlp-2/igt@[email protected]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-8/igt@[email protected]

* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#3638]) +1 other test skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_big_fb@y-tiled-32bpp-rotate-90:
- shard-dg2-9: NOTRUN -> [SKIP][127] ([i915#4538] / [i915#5190]) +8 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#6187])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][129] +10 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][130] ([i915#4538])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#4538] / [i915#5190]) +8 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][132] +41 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_busy@extended-pageflip-hang-oldfb:
- shard-dg1: [PASS][133] -> [DMESG-WARN][134] ([i915#4423])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-15/igt@[email protected]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-18/igt@[email protected]

* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#6095]) +152 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@kms_ccs@[email protected]

* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][136] ([i915#6095]) +24 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@kms_ccs@[email protected]

* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-2:
- shard-dg2-9: NOTRUN -> [SKIP][137] ([i915#10307] / [i915#6095]) +39 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_ccs@[email protected]

* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#6095]) +19 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_ccs@[email protected]

* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][139] ([i915#12313]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][140] ([i915#6095]) +60 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-4/igt@kms_ccs@[email protected]

* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][141] ([i915#12313])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#12805])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][143] ([i915#6095]) +4 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][144] ([i915#6095]) +44 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_ccs@[email protected]

* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-c-dp-3:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#6095]) +17 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@kms_ccs@[email protected]

* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#10307] / [i915#6095]) +166 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-5/igt@kms_ccs@[email protected]

* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-4/igt@kms_ccs@[email protected]

* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#12313]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_cdclk@mode-transition:
- shard-tglu: NOTRUN -> [SKIP][149] ([i915#3742])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2-9: NOTRUN -> [SKIP][150] ([i915#11151] / [i915#7828]) +7 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#11151] / [i915#7828]) +3 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@kms_chamelium_color@ctm-0-25:
- shard-dg2: NOTRUN -> [SKIP][152] +5 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@kms_chamelium_color@ctm-max:
- shard-mtlp: NOTRUN -> [SKIP][153] +6 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#11151] / [i915#7828]) +4 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#11151] / [i915#7828])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#11151] / [i915#7828]) +3 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-tglu-1: NOTRUN -> [SKIP][157] ([i915#11151] / [i915#7828]) +6 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#11151] / [i915#7828]) +2 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_color@deep-color:
- shard-dg2: [PASS][159] -> [SKIP][160] ([i915#3555])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-11/igt@[email protected]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-5/igt@[email protected]

* igt@kms_content_protection@atomic:
- shard-rkl: NOTRUN -> [SKIP][161] ([i915#7118] / [i915#9424])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][162] ([i915#7173])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-10/igt@kms_content_protection@[email protected]

* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#3299])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglu-1: NOTRUN -> [SKIP][164] ([i915#3116] / [i915#3299])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2-9: NOTRUN -> [SKIP][165] ([i915#3299])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_content_protection@legacy:
- shard-dg2-9: NOTRUN -> [SKIP][166] ([i915#7118] / [i915#9424])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_content_protection@lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#9424])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]
- shard-tglu-1: NOTRUN -> [SKIP][168] ([i915#6944] / [i915#9424])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_content_protection@srm:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#6944])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_cursor_crc@cursor-onscreen-128x42:
- shard-mtlp: NOTRUN -> [SKIP][170] ([i915#8814])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]

* igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [FAIL][171] ([i915#13566]) +1 other test fail
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@kms_cursor_crc@[email protected]

* igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][172] ([i915#13566])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-3/igt@kms_cursor_crc@[email protected]

* igt@kms_cursor_crc@cursor-random-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][173] ([i915#3555]) +3 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2-9: NOTRUN -> [SKIP][174] ([i915#13049]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#3555] / [i915#8814])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-dg2-9: NOTRUN -> [SKIP][176] ([i915#3555]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#13049])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_cursor_crc@cursor-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][178] ([i915#12358] / [i915#7882])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk4/igt@[email protected]

* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [INCOMPLETE][179] ([i915#12358])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk4/igt@kms_cursor_crc@[email protected]

* igt@kms_cursor_edge_walk@64x64-right-edge@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [DMESG-WARN][180] ([i915#12964]) +2 other tests dmesg-warn
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_cursor_edge_walk@[email protected]

* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#13046] / [i915#5354]) +2 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-tglu-1: NOTRUN -> [SKIP][182] ([i915#4103])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-dg2-9: NOTRUN -> [SKIP][183] ([i915#13046] / [i915#5354])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-rkl: NOTRUN -> [FAIL][184] ([i915#2346])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#9067])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#4103] / [i915#4213]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-tglu-1: NOTRUN -> [SKIP][187] ([i915#9723])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#9833])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][189] ([i915#3804])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-5/igt@kms_dither@[email protected]

* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg1: NOTRUN -> [SKIP][190] ([i915#3555]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_dp_aux_dev:
- shard-dg2: [PASS][191] -> [SKIP][192] ([i915#1257])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-11/igt@kms_dp_aux_dev.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-5/igt@kms_dp_aux_dev.html

* igt@kms_dp_link_training@non-uhbr-sst:
- shard-tglu-1: NOTRUN -> [SKIP][193] ([i915#13749])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_dp_link_training@uhbr-mst:
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#13748])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg2-9: NOTRUN -> [SKIP][195] ([i915#8812])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_dsc@dsc-basic:
- shard-tglu-1: NOTRUN -> [SKIP][196] ([i915#3555] / [i915#3840])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2-9: NOTRUN -> [SKIP][197] ([i915#3840])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_dsc@dsc-with-formats:
- shard-tglu: NOTRUN -> [SKIP][198] ([i915#3555] / [i915#3840])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#3840]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2-9: NOTRUN -> [SKIP][200] ([i915#3840] / [i915#9053])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#13798])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-tglu: NOTRUN -> [SKIP][202] ([i915#2575])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_fbcon_fbt@psr:
- shard-dg2-9: NOTRUN -> [SKIP][203] ([i915#3469])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#3955])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#4854])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_feature_discovery@display-2x:
- shard-tglu: NOTRUN -> [SKIP][206] ([i915#1839])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][207] ([i915#9337])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_feature_discovery@psr1:
- shard-tglu-1: NOTRUN -> [SKIP][208] ([i915#658])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_feature_discovery@psr2:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#658])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_flip@2x-flip-vs-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][210] ([i915#3637]) +6 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#8381])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_flip@2x-flip-vs-modeset:
- shard-tglu: NOTRUN -> [SKIP][212] ([i915#3637]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#9934]) +5 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#9934]) +3 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_flip@2x-flip-vs-wf_vblank.html
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#9934]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_flip@2x-flip-vs-wf_vblank.html

* igt@kms_flip@2x-plain-flip-interruptible:
- shard-dg2-9: NOTRUN -> [SKIP][216] ([i915#9934]) +6 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_flip@dpms-vs-vblank-race-interruptible@b-hdmi-a2:
- shard-rkl: [PASS][217] -> [DMESG-WARN][218] ([i915#12964]) +14 other tests dmesg-warn
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-8/igt@kms_flip@[email protected]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-5/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-dg2: NOTRUN -> [FAIL][219] ([i915#13734]) +3 other tests fail
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

* igt@kms_flip@flip-vs-expired-vblank:
- shard-dg2: [PASS][220] -> [FAIL][221] ([i915#13027])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-10/igt@[email protected]
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-2/igt@[email protected]

* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a3:
- shard-dg2: NOTRUN -> [FAIL][222] ([i915#13027])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-2/igt@kms_flip@[email protected]

* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][223] ([i915#2587] / [i915#2672]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][224] ([i915#2672] / [i915#3555])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html

* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#2672] / [i915#3555])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#2672])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglu: NOTRUN -> [SKIP][227] ([i915#2587] / [i915#2672] / [i915#3555])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][228] ([i915#2587] / [i915#2672])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-dg2-9: NOTRUN -> [SKIP][229] ([i915#2672] / [i915#3555] / [i915#5190]) +2 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html

* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode:
- shard-dg2-9: NOTRUN -> [SKIP][230] ([i915#2672]) +3 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][231] ([i915#2672]) +1 other test skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][232] ([i915#2672] / [i915#3555]) +1 other test skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
- shard-dg1: NOTRUN -> [SKIP][233] ([i915#2672] / [i915#3555])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][234] ([i915#2587] / [i915#2672])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][235] ([i915#2672] / [i915#3555]) +1 other test skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html

* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][236] ([i915#3555] / [i915#8810] / [i915#8813]) +1 other test skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html

* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][237] ([i915#3555] / [i915#8810]) +1 other test skip
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][238] ([i915#1825]) +7 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#5354]) +19 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-dg1: NOTRUN -> [SKIP][240] ([i915#3458]) +2 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#3458]) +13 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][242] ([i915#8708]) +3 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html

* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite:
- shard-tglu-1: NOTRUN -> [SKIP][243] +54 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html

* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][244] ([i915#5439])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][245] ([i915#5439])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][246] ([i915#10055])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][247] ([i915#8708]) +4 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][248] ([i915#3023]) +12 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-dg2-9: NOTRUN -> [SKIP][249] ([i915#3458]) +7 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2-9: NOTRUN -> [SKIP][250] ([i915#8708]) +15 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html

* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt:
- shard-dg2-9: NOTRUN -> [SKIP][251] ([i915#5354]) +25 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#8708]) +9 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][253] +6 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render.html

* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][254] ([i915#1825]) +17 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2-9: NOTRUN -> [SKIP][255] ([i915#6118])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_hdr@bpc-switch:
- shard-tglu-1: NOTRUN -> [SKIP][256] ([i915#3555] / [i915#8228])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_hdr@static-toggle:
- shard-dg2-9: NOTRUN -> [SKIP][257] ([i915#3555] / [i915#8228]) +1 other test skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_joiner@basic-big-joiner:
- shard-dg2-9: NOTRUN -> [SKIP][258] ([i915#10656])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_joiner@basic-force-big-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][259] ([i915#12388])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_joiner@basic-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][260] ([i915#12394])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_joiner@basic-max-non-joiner:
- shard-dg2-9: NOTRUN -> [SKIP][261] ([i915#13688])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_joiner@basic-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][262] ([i915#12339])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-rkl: NOTRUN -> [SKIP][263] ([i915#12394])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][264] ([i915#13522])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_plane_multiple@tiling-y:
- shard-dg2-9: NOTRUN -> [SKIP][265] ([i915#8806])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers:
- shard-dg2-9: NOTRUN -> [SKIP][266] ([i915#12247] / [i915#9423])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers.html

* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#12247] / [i915#9423]) +1 other test skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b:
- shard-tglu: NOTRUN -> [SKIP][268] ([i915#12247]) +4 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
- shard-tglu-1: NOTRUN -> [SKIP][269] ([i915#12247]) +12 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][270] ([i915#12247] / [i915#6953])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][271] ([i915#12247]) +11 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-dg2-9: NOTRUN -> [SKIP][272] ([i915#12247] / [i915#6953] / [i915#9423]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b:
- shard-rkl: NOTRUN -> [SKIP][273] ([i915#12247]) +4 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
- shard-mtlp: NOTRUN -> [SKIP][274] ([i915#6953])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html

* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-b:
- shard-mtlp: NOTRUN -> [SKIP][275] ([i915#12247]) +3 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b:
- shard-snb: NOTRUN -> [SKIP][276] +71 other tests skip
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-snb1/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][277] ([i915#12247] / [i915#6953] / [i915#9423])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
- shard-tglu-1: NOTRUN -> [SKIP][278] ([i915#12247] / [i915#6953])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html

* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][279] ([i915#12247] / [i915#3555])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
- shard-rkl: NOTRUN -> [SKIP][280] ([i915#12247] / [i915#3555])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
- shard-dg1: NOTRUN -> [SKIP][281] ([i915#12247]) +3 other tests skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@kms_plane_scaling@[email protected]

* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d:
- shard-dg2-9: NOTRUN -> [SKIP][282] ([i915#12247]) +11 other tests skip
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@kms_plane_scaling@[email protected]

* igt@kms_pm_backlight@fade-with-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][283] ([i915#9812]) +1 other test skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2-9: NOTRUN -> [SKIP][284] ([i915#9685])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: NOTRUN -> [SKIP][285] ([i915#4281])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [PASS][286] -> [SKIP][287] ([i915#9340])
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-8/igt@[email protected]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-6/igt@[email protected]

* igt@kms_pm_lpsp@screens-disabled:
- shard-dg2-9: NOTRUN -> [SKIP][288] ([i915#8430])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][289] ([i915#9519])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][290] ([i915#9519])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [PASS][291] -> [SKIP][292] ([i915#9519]) +2 other tests skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-7/igt@[email protected]
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-3/igt@[email protected]

* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [PASS][293] -> [SKIP][294] ([i915#9519])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-2/igt@[email protected]
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-8/igt@[email protected]

* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][295] ([i915#6524] / [i915#6805])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]
- shard-tglu-1: NOTRUN -> [SKIP][296] ([i915#6524])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2-9: NOTRUN -> [SKIP][297] ([i915#11520]) +4 other tests skip
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
- shard-dg2: NOTRUN -> [SKIP][298] ([i915#11520]) +6 other tests skip
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]
- shard-tglu-1: NOTRUN -> [SKIP][299] ([i915#11520]) +4 other tests skip
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][300] ([i915#9808])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_psr2_sf@[email protected]

* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][301] ([i915#12316]) +3 other tests skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_psr2_sf@[email protected]

* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
- shard-glk: NOTRUN -> [SKIP][302] ([i915#11520]) +2 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk4/igt@[email protected]

* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][303] ([i915#11520]) +4 other tests skip
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][304] ([i915#11520]) +1 other test skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
- shard-snb: NOTRUN -> [SKIP][305] ([i915#11520]) +1 other test skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-snb1/igt@[email protected]

* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-tglu: NOTRUN -> [SKIP][306] ([i915#11520]) +3 other tests skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2-9: NOTRUN -> [SKIP][307] ([i915#9683])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_psr2_su@page_flip-nv12:
- shard-tglu: NOTRUN -> [SKIP][308] ([i915#9683])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@kms_psr2_su@page_flip-nv12.html

* igt@kms_psr2_su@page_flip-p010:
- shard-tglu-1: NOTRUN -> [SKIP][309] ([i915#9683])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_psr2_su@page_flip-p010.html

* igt@kms_psr@fbc-pr-basic:
- shard-mtlp: NOTRUN -> [SKIP][310] ([i915#9688]) +3 other tests skip
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_psr@fbc-pr-no-drrs:
- shard-dg1: NOTRUN -> [SKIP][311] ([i915#1072] / [i915#9732]) +3 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][312] ([i915#1072] / [i915#9732]) +14 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_psr@psr-sprite-mmap-gtt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][313] ([i915#4077] / [i915#9688]) +3 other tests skip
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@kms_psr@[email protected]

* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][314] ([i915#1072] / [i915#9732]) +11 other tests skip
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@kms_psr@psr2-cursor-blt:
- shard-dg2-9: NOTRUN -> [SKIP][315] ([i915#1072] / [i915#9732]) +14 other tests skip
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_psr@psr2-primary-render:
- shard-tglu: NOTRUN -> [SKIP][316] ([i915#9732]) +9 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][317] ([i915#9732]) +13 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglu-1: NOTRUN -> [SKIP][318] ([i915#9685])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_rotation_crc@exhaust-fences:
- shard-dg1: NOTRUN -> [SKIP][319] ([i915#4884])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][320] ([i915#5289])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][321] ([i915#5289])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2-9: NOTRUN -> [SKIP][322] ([i915#5190])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-mtlp: NOTRUN -> [SKIP][323] ([i915#12755])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][324] ([i915#12755])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2-9: NOTRUN -> [SKIP][325] ([i915#12755]) +1 other test skip
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_scaling_modes@scaling-mode-full:
- shard-tglu: NOTRUN -> [SKIP][326] ([i915#3555]) +5 other tests skip
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@kms_selftest@drm_framebuffer:
- shard-tglu-1: NOTRUN -> [ABORT][327] ([i915#13179]) +1 other test abort
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@kms_selftest@drm_framebuffer.html

* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][328] ([i915#3555] / [i915#8809] / [i915#8823])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@kms_setmode@invalid-clone-single-crtc:
- shard-rkl: NOTRUN -> [SKIP][329] ([i915#3555]) +1 other test skip
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu-1: NOTRUN -> [SKIP][330] ([i915#8623])
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]
- shard-dg2: NOTRUN -> [SKIP][331] ([i915#8623])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@kms_vrr@lobf:
- shard-tglu: NOTRUN -> [SKIP][332] ([i915#11920])
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-3/igt@[email protected]

* igt@kms_vrr@max-min:
- shard-tglu-1: NOTRUN -> [SKIP][333] ([i915#9906])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: NOTRUN -> [SKIP][334] ([i915#9906])
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@kms_writeback@writeback-check-output:
- shard-dg2-9: NOTRUN -> [SKIP][335] ([i915#2437])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][336] ([i915#2437] / [i915#9412])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-7/igt@[email protected]

* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2-9: NOTRUN -> [SKIP][337] ([i915#2437] / [i915#9412])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@kms_writeback@writeback-pixel-formats:
- shard-tglu: NOTRUN -> [SKIP][338] ([i915#2437] / [i915#9412])
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-8/igt@[email protected]

* igt@perf@non-zero-reason:
- shard-dg2: NOTRUN -> [FAIL][339] ([i915#9100]) +1 other test fail
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][340] -> [FAIL][341] ([i915#4349]) +4 other tests fail
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-11/igt@perf_pmu@[email protected]
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-5/igt@perf_pmu@[email protected]

* igt@perf_pmu@rc6-all-gts:
- shard-tglu-1: NOTRUN -> [SKIP][342] ([i915#8516])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-tglu-1/igt@[email protected]

* igt@prime_vgem@basic-read:
- shard-rkl: NOTRUN -> [SKIP][343] ([i915#3291] / [i915#3708])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]
- shard-dg1: NOTRUN -> [SKIP][344] ([i915#3708])
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

* igt@prime_vgem@coherency-gtt:
- shard-rkl: NOTRUN -> [SKIP][345] ([i915#3708])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@prime_vgem@fence-write-hang:
- shard-dg2-9: NOTRUN -> [SKIP][346] ([i915#3708]) +1 other test skip
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-9/igt@[email protected]

* igt@syncobj_timeline@etime-single-wait-all-for-submit-unsubmitted:
- shard-glk: [PASS][347] -> [DMESG-WARN][348] ([i915#118])
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk9/igt@syncobj_timeline@etime-single-wait-all-for-submit-unsubmitted.html
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk3/igt@syncobj_timeline@etime-single-wait-all-for-submit-unsubmitted.html

#### Possible fixes ####

* igt@gem_eio@in-flight-internal-10ms:
- shard-mtlp: [ABORT][349] ([i915#13193]) -> [PASS][350] +1 other test pass
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-mtlp-7/igt@[email protected]
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-5/igt@[email protected]

* igt@gem_eio@kms:
- shard-rkl: [DMESG-WARN][351] ([i915#13363]) -> [PASS][352]
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-8/igt@[email protected]
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-5/igt@[email protected]

* igt@gem_exec_flush@basic-wb-set-default:
- shard-glk: [DMESG-WARN][353] ([i915#118]) -> [PASS][354] +2 other tests pass
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk9/igt@[email protected]
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk6/igt@[email protected]

* igt@gem_exec_suspend@basic-s3:
- shard-rkl: [INCOMPLETE][355] ([i915#13304]) -> [PASS][356] +1 other test pass
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-5/igt@[email protected]
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@gem_exec_suspend@basic-s4-devices:
- shard-dg2: [ABORT][357] ([i915#7975] / [i915#8213]) -> [PASS][358] +1 other test pass
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-4/igt@[email protected]
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-11/igt@[email protected]

* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [TIMEOUT][359] ([i915#5493]) -> [PASS][360] +1 other test pass
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-8/igt@gem_lmem_swapping@[email protected]
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-4/igt@gem_lmem_swapping@[email protected]

* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: [TIMEOUT][361] ([i915#12964]) -> [PASS][362]
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-5/igt@[email protected]
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@gem_pxp@reject-modify-context-protection-on:
- shard-rkl: [TIMEOUT][363] ([i915#12917] / [i915#12964]) -> [PASS][364] +1 other test pass
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-5/igt@[email protected]
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@[email protected]

* igt@gen9_exec_parse@allowed-all:
- shard-glk: [ABORT][365] ([i915#5566]) -> [PASS][366]
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk7/igt@[email protected]
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk2/igt@[email protected]

* igt@i915_hangman@gt-error-state-capture@rcs0:
- shard-rkl: [DMESG-WARN][367] ([i915#12964]) -> [PASS][368] +4 other tests pass
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-5/igt@i915_hangman@[email protected]
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-8/igt@i915_hangman@[email protected]

* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][369] ([i915#3591]) -> [PASS][370]
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-17/igt@i915_pm_rc6_residency@[email protected]
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-19/igt@i915_pm_rc6_residency@[email protected]

* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][371] ([i915#13821]) -> [PASS][372]
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-snb5/igt@[email protected]
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-snb1/igt@[email protected]

* igt@i915_selftest@live:
- shard-dg1: [DMESG-FAIL][373] ([i915#12435]) -> [PASS][374]
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@[email protected]
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@[email protected]

* igt@i915_selftest@live@gem_contexts:
- shard-dg1: [DMESG-FAIL][375] -> [PASS][376]
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@i915_selftest@live@gem_contexts.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@i915_selftest@live@gem_contexts.html

* igt@kms_addfb_basic@no-handle:
- shard-dg1: [DMESG-WARN][377] ([i915#4391] / [i915#4423]) -> [PASS][378] +1 other test pass
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-15/igt@[email protected]
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-18/igt@[email protected]

* igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions:
- shard-glk: [FAIL][379] ([i915#2346]) -> [PASS][380] +1 other test pass
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk8/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk6/igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html

* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: [SKIP][381] ([i915#3555]) -> [PASS][382]
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-7/igt@[email protected]
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-10/igt@[email protected]

* igt@kms_flip@2x-modeset-vs-vblank-race@ab-vga1-hdmi-a1:
- shard-snb: [INCOMPLETE][383] ([i915#12314]) -> [PASS][384] +1 other test pass
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-snb2/igt@kms_flip@[email protected]
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-snb2/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-dg1: [FAIL][385] ([i915#13734]) -> [PASS][386]
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-12/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: [FAIL][387] ([i915#6880]) -> [PASS][388] +1 other test pass
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-dg1: [DMESG-WARN][389] ([i915#4423]) -> [PASS][390] +4 other tests pass
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html

* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: [SKIP][391] ([i915#3555] / [i915#8228]) -> [PASS][392]
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-7/igt@[email protected]
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-10/igt@[email protected]

* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][393] ([i915#3361]) -> [PASS][394]
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-rkl-8/igt@[email protected]
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-rkl-1/igt@[email protected]

* igt@perf_pmu@module-unload:
- shard-dg1: [INCOMPLETE][395] ([i915#13520]) -> [PASS][396]
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-15/igt@[email protected]
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-12/igt@[email protected]

#### Warnings ####

* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: [SKIP][397] ([i915#4423] / [i915#4538]) -> [SKIP][398] ([i915#4538])
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: [SKIP][399] ([i915#4423] / [i915#6095]) -> [SKIP][400] ([i915#6095]) +1 other test skip
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-16/igt@kms_ccs@[email protected]
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-19/igt@kms_ccs@[email protected]

* igt@kms_content_protection@atomic-dpms:
- shard-dg2: [SKIP][401] ([i915#7118] / [i915#9424]) -> [FAIL][402] ([i915#7173])
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-7/igt@[email protected]
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-10/igt@[email protected]

* igt@kms_content_protection@lic-type-0:
- shard-dg2: [FAIL][403] ([i915#7173]) -> [SKIP][404] ([i915#9424])
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-11/igt@[email protected]
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-5/igt@[email protected]

* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][405] ([i915#9433]) -> [SKIP][406] ([i915#9424])
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-13/igt@[email protected]
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-14/igt@[email protected]

* igt@kms_flip@2x-flip-vs-suspend:
- shard-glk: [INCOMPLETE][407] ([i915#12314] / [i915#12745] / [i915#4839]) -> [INCOMPLETE][408] ([i915#12745] / [i915#4839])
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk8/igt@[email protected]
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk6/igt@[email protected]

* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk: [INCOMPLETE][409] ([i915#12314] / [i915#4839]) -> [INCOMPLETE][410] ([i915#4839])
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-glk8/igt@kms_flip@[email protected]
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-glk6/igt@kms_flip@[email protected]

* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg1: [SKIP][411] ([i915#4423] / [i915#9934]) -> [SKIP][412] ([i915#9934])
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-12/igt@[email protected]
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-14/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-dg2: [SKIP][413] ([i915#10433] / [i915#3458]) -> [SKIP][414] ([i915#3458]) +1 other test skip
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-4/igt@[email protected]
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-2/igt@[email protected]

* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-dg2: [SKIP][415] ([i915#3458]) -> [SKIP][416] ([i915#10433] / [i915#3458]) +2 other tests skip
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html

* igt@kms_hdr@brightness-with-hdr:
- shard-mtlp: [SKIP][417] ([i915#1187] / [i915#12713]) -> [SKIP][418] ([i915#12713])
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-mtlp-1/igt@[email protected]
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-mtlp-2/igt@[email protected]
- shard-dg2: [SKIP][419] ([i915#13331]) -> [SKIP][420] ([i915#12713])
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg2-10/igt@[email protected]
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg2-3/igt@[email protected]

* igt@kms_pm_rpm@i2c:
- shard-dg1: [SKIP][421] ([i915#12916] / [i915#4423]) -> [DMESG-WARN][422] ([i915#4423])
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@[email protected]
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@[email protected]

* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg1: [SKIP][423] ([i915#11520] / [i915#4423]) -> [SKIP][424] ([i915#11520])
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

* igt@kms_psr@fbc-psr2-sprite-plane-onoff:
- shard-dg1: [SKIP][425] ([i915#1072] / [i915#9732]) -> [SKIP][426] ([i915#1072] / [i915#4423] / [i915#9732]) +1 other test skip
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-15/igt@[email protected]
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-18/igt@[email protected]

* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg1: [SKIP][427] ([i915#4423] / [i915#5289]) -> [SKIP][428] ([i915#5289])
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-19/igt@[email protected]
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-17/igt@[email protected]

* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg1: [SKIP][429] ([i915#4423] / [i915#9906]) -> [SKIP][430] ([i915#9906])
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16321/shard-dg1-16/igt@[email protected]
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/shard-dg1-19/igt@[email protected]

Build changes
-------------

* Linux: CI_DRM_16321 -> Patchwork_140306v7

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140306v7/index.html

Rodrigo Vivi

maintainer

2025-03-26 19:23 UTC #25 lore raw

In reply to Alexander Usyskin

Quoted 33 lines · Alexander Usyskin

Add driver for access to Intel discrete graphics card internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and provide mtd driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics" and "spi: add driver for Intel discrete graphics"
series with connection to the Xe driver and splitting
the spi driver part to separate module in mtd subsystem.
This series intended to be pushed through drm-xe-next.
V2: Replace dev_* prints with drm_* prints in drm (xe and i915) patches.
Enable NVM device on Battlemage HW (xe driver patch)
Fix overwrite register address (xe driver patch)
Add Rodrigo's r-b
V3: Use devm_pm_runtime_enable to simplify flow.
Drop print in i915 unload that was accidentally set as error. Drop HAS_GSC_NVM macro in line with latest Xe changes. Add more Rodrigo's r-b and Miquel's ack.
V4: Add patch that always creates mtd master device
and adjust mtd-intel-dg power management to use this device.
V5: Fix master device creation to accomodate for devices without
partitions (create partitoned master in this case) Rebase over latest drm-xe-next
Add ack's
V6: Fix master device release (use rigth idr in release)
Rebase over latest drm-xe-next
Grammar and style fixes

Quoted 2 lines

V7: Add patch with non-posted erase support (fix hang on BMG)
Rebase over latest drm-xe-next

There are 2 things that I should had noticed earlier and mentioned to you. I'm sorry for forgetting that.

1. Rebase on drm-tip branch of this repo: https://gitlab.freedesktop.org/drm/tip
We merge to drm-xe-next, but development and CI happens on drm-tip.

2. Please also send to [email protected] Xe CI only runs on that mailing list. intel-gfx is for i915.

No need to rebase or resend right now. Let's wait for a few reviews, then we rebase and resend.

Thanks,
Rodrigo.

Quoted 50 lines

Abliyev, Reuven (1):
drm/xe/nvm: add support for non-posted erase

 MAINTAINERS                           |   7 +
 drivers/gpu/drm/i915/Makefile         |   4 +
 drivers/gpu/drm/i915/i915_driver.c    |   6 +
 drivers/gpu/drm/i915/i915_drv.h       |   3 +
 drivers/gpu/drm/i915/i915_reg.h       |   1 +
 drivers/gpu/drm/i915/intel_nvm.c      | 115 ++++
 drivers/gpu/drm/i915/intel_nvm.h      |  15 +
 drivers/gpu/drm/xe/Makefile           |   1 +
 drivers/gpu/drm/xe/regs/xe_gsc_regs.h |   4 +
 drivers/gpu/drm/xe/xe_device.c        |   5 +
 drivers/gpu/drm/xe/xe_device_types.h  |   6 +
 drivers/gpu/drm/xe/xe_heci_gsc.c      |   5 +-
 drivers/gpu/drm/xe/xe_nvm.c           | 161 +++++
 drivers/gpu/drm/xe/xe_nvm.h           |  15 +
 drivers/gpu/drm/xe/xe_pci.c           |   6 +
 drivers/mtd/devices/Kconfig           |  11 +
 drivers/mtd/devices/Makefile          |   1 +
 drivers/mtd/devices/mtd_intel_dg.c    | 884 ++++++++++++++++++++++++++
 drivers/mtd/mtdcore.c                 | 141 ++--
 drivers/mtd/mtdcore.h                 |   2 +-
 drivers/mtd/mtdpart.c                 |  17 +-
 include/linux/intel_dg_nvm_aux.h      |  29 +
 22 files changed, 1385 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.c
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.h
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.c
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.h
 create mode 100644 drivers/mtd/devices/mtd_intel_dg.c
 create mode 100644 include/linux/intel_dg_nvm_aux.h

Signature · 1 line

2.43.0

Usyskin, Alexander

author maintainer

2025-04-09 09:33 UTC #26 lore raw

Quoted 44 lines · Alexander Usyskin

Quoted 33 lines
Add driver for access to Intel discrete graphics card internal NVM device.
Expose device on auxiliary bus by i915 and Xe drivers and provide mtd driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics" and "spi: add driver for Intel discrete graphics"
series with connection to the Xe driver and splitting
the spi driver part to separate module in mtd subsystem.
This series intended to be pushed through drm-xe-next.
V2: Replace dev_* prints with drm_* prints in drm (xe and i915) patches.
Enable NVM device on Battlemage HW (xe driver patch)
Fix overwrite register address (xe driver patch)
Add Rodrigo's r-b
V3: Use devm_pm_runtime_enable to simplify flow.
Drop print in i915 unload that was accidentally set as error. Drop HAS_GSC_NVM macro in line with latest Xe changes. Add more Rodrigo's r-b and Miquel's ack.
V4: Add patch that always creates mtd master device
and adjust mtd-intel-dg power management to use this device.
V5: Fix master device creation to accomodate for devices without
partitions (create partitoned master in this case) Rebase over latest drm-xe-next
Add ack's
V6: Fix master device release (use rigth idr in release)
Rebase over latest drm-xe-next
Grammar and style fixes
Quoted 2 lines
V7: Add patch with non-posted erase support (fix hang on BMG)
Rebase over latest drm-xe-next
There are 2 things that I should had noticed earlier and mentioned to you. I'm sorry for forgetting that.
1. Rebase on drm-tip branch of this repo:
https://gitlab.freedesktop.org/drm/tip
We merge to drm-xe-next, but development and CI happens on drm-tip.

Quoted 6 lines

2. Please also send to [email protected] Xe CI only runs on that mailing list. intel-gfx is for i915.
No need to rebase or resend right now. Let's wait for a few reviews, then we rebase and resend.

Do not see flock of reviewers for this one...
Can you, please, review the last patch? This one is a new one. All other are already acked.
Then I'll re-spin the series with right base and cc.

- -
Thanks,
Sasha

Quoted 54 lines

Thanks,
Rodrigo.
Quoted 27 lines
Abliyev, Reuven (1):
drm/xe/nvm: add support for non-posted erase
Alexander Usyskin (11):
mtd: core: always create master device
mtd: add driver for intel graphics non-volatile memory device
mtd: intel-dg: implement region enumeration
mtd: intel-dg: implement access functions
mtd: intel-dg: register with mtd
mtd: intel-dg: align 64bit read and write
mtd: intel-dg: wake card on operations drm/i915/nvm: add nvm device for discrete graphics drm/i915/nvm: add support for access mode drm/xe/nvm: add on-die non-volatile memory device drm/xe/nvm: add support for access mode
 MAINTAINERS                           |   7 +
 drivers/gpu/drm/i915/Makefile         |   4 +
 drivers/gpu/drm/i915/i915_driver.c    |   6 +
 drivers/gpu/drm/i915/i915_drv.h       |   3 +
 drivers/gpu/drm/i915/i915_reg.h       |   1 +
 drivers/gpu/drm/i915/intel_nvm.c      | 115 ++++
 drivers/gpu/drm/i915/intel_nvm.h      |  15 +
 drivers/gpu/drm/xe/Makefile           |   1 +
 drivers/gpu/drm/xe/regs/xe_gsc_regs.h |   4 +
 drivers/gpu/drm/xe/xe_device.c        |   5 +
Quoted 8 lines
 drivers/gpu/drm/xe/xe_device_types.h  |   6 +
 drivers/gpu/drm/xe/xe_heci_gsc.c      |   5 +-
 drivers/gpu/drm/xe/xe_nvm.c           | 161 +++++
 drivers/gpu/drm/xe/xe_nvm.h           |  15 +
 drivers/gpu/drm/xe/xe_pci.c           |   6 +
 drivers/mtd/devices/Kconfig           |  11 +
 drivers/mtd/devices/Makefile          |   1 +
 drivers/mtd/devices/mtd_intel_dg.c    | 884
++++++++++++++++++++++++++
Quoted 15 lines
 drivers/mtd/mtdcore.c                 | 141 ++--
 drivers/mtd/mtdcore.h                 |   2 +-
 drivers/mtd/mtdpart.c                 |  17 +-
 include/linux/intel_dg_nvm_aux.h      |  29 +
 22 files changed, 1385 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.c
 create mode 100644 drivers/gpu/drm/i915/intel_nvm.h
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.c
 create mode 100644 drivers/gpu/drm/xe/xe_nvm.h
 create mode 100644 drivers/mtd/devices/mtd_intel_dg.c
 create mode 100644 include/linux/intel_dg_nvm_aux.h
--
2.43.0

Patchwork

2025-04-10 14:30 UTC #27 lore raw

✗ Fi.CI.BUILD: failure for mtd: add driver for Intel discrete graphics (rev8)

In reply to Alexander Usyskin

== Series Details ==

Series: mtd: add driver for Intel discrete graphics (rev8)
URL : https://patchwork.freedesktop.org/series/140306/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/140306/revisions/8/mbox/ not applied
Applying: mtd: core: always create master device
error: sha1 information is lacking or useless (drivers/mtd/mtdcore.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 mtd: core: always create master device
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced