x86: Introduce Intel Tangier SoC and Edison board
v2 cover x86: Introduce Intel Tangier SoC and Edison board
This brings support for Intel Tangier SoC and Intel Edison board which is using U-Boot as a main bootloader.
The series has implicit dependency to watchdog driver (V3 of which had been sent earlier today).
Since v1:
- split patch 1 to 2 (Bin)
- move enum to sfi.h (Bin)
- remove unnecessary headers (Bin)
- add comment to SFI system table search (Bin)
- append and update copyright notices: sdram.c and tangier.c are almost done by Intel (Simon)
- disable SD card slot (Simon)
- add Simon's tag to patch 1 and 2 (changes basically technical)
- add Edison support
Andy Shevchenko (2):
x86: Add dma-mapping.h to architectural code
x86: Add Intel Edison board files
Felipe Balbi (1):
x86: Add Intel Tangier support
arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/tangier/Kconfig | 24 +++++ arch/x86/cpu/tangier/Makefile | 7 ++ arch/x86/cpu/tangier/car.S | 13 +++ arch/x86/cpu/tangier/sdram.c | 206 +++++++++++++++++++++++++++++++++++++ arch/x86/cpu/tangier/tangier.c | 34 ++++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/edison.dts | 89 ++++++++++++++++ arch/x86/include/asm/dma-mapping.h | 41 ++++++++ arch/x86/include/asm/sfi.h | 19 ++++ board/intel/Kconfig | 8 ++ board/intel/edison/Kconfig | 26 +++++ board/intel/edison/Makefile | 1 + board/intel/edison/config.mk | 18 ++++ board/intel/edison/edison.c | 104 +++++++++++++++++++ board/intel/edison/edison_start.S | 13 +++ configs/edison_defconfig | 53 ++++++++++ doc/README.x86 | 39 +++++++ include/configs/edison.h | 78 ++++++++++++++ 20 files changed, 776 insertions(+) create mode 100644 arch/x86/cpu/tangier/Kconfig create mode 100644 arch/x86/cpu/tangier/Makefile create mode 100644 arch/x86/cpu/tangier/car.S create mode 100644 arch/x86/cpu/tangier/sdram.c create mode 100644 arch/x86/cpu/tangier/tangier.c create mode 100644 arch/x86/dts/edison.dts create mode 100644 arch/x86/include/asm/dma-mapping.h create mode 100644 board/intel/edison/Kconfig create mode 100644 board/intel/edison/Makefile create mode 100644 board/intel/edison/config.mk create mode 100644 board/intel/edison/edison.c create mode 100644 board/intel/edison/edison_start.S create mode 100644 configs/edison_defconfig create mode 100644 include/configs/edison.h
Signature · 1 line
2.11.0
PATCH v2 1/3 x86: Add dma-mapping.h to architectural code
Some cross-platform drivers rely on this header present. Make it so for x86.
It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.
--- arch/x86/include/asm/dma-mapping.h | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 arch/x86/include/asm/dma-mapping.h
arch/x86/include/asm/dma-mapping.h new file +41 -0
@@ -0,0 +1,41 @@ +/* +* (C) Copyright 2007 +* Stelian Pop <[email protected]> +* Lead Tech Design <www.leadtechdesign.com> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __ASM_X86_DMA_MAPPING_H +#define __ASM_X86_DMA_MAPPING_H + +#define dma_mapping_error (x, y) 0 + +enum dma_data_direction { +DMA_BIDIRECTIONAL =0 , +DMA_TO_DEVICE =1 , +DMA_FROM_DEVICE =2 , +}; + +static inline void *dma_alloc_coherent (size_t len,unsigned long *handle) +{ + *handle = (unsigned long )memalign (ARCH_DMA_MINALIGN , len); +return (void *)*handle; +} + +static inline void dma_free_coherent (void *addr) +{ +free (addr); +} + +static inline unsigned long dma_map_single (volatile void *vaddr,size_t len, +enum dma_data_direction dir) +{ +return (unsigned long )vaddr; +} + +static inline void dma_unmap_single (volatile void *vaddr,size_t len, +unsigned long paddr) +{ +} + +#endif /* __ASM_X86_DMA_MAPPING_H */
Signature · 1 line
2.11.0
PATCH v2 1/3 x86: Add dma-mapping.h to architectural code
Quoted 5 lines · Andy Shevchenko
Some cross-platform drivers rely on this header present. Make it so for x86.
It's just a copy'n'paste of
arch/arm/include/asm/dma-mapping.h.
Quoted 8 lines
Suggested-by Bin Meng <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>--- arch/x86/include/asm/dma-mapping.h | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 arch/x86/include/asm/dma-mapping.h
PATCH v2 1/3 x86: Add dma-mapping.h to architectural code
In reply to Andy ShevchenkoQuoted 5 lines · Andy Shevchenko
Some cross-platform drivers rely on this header present. Make it so for x86.
It's just a copy'n'paste of
arch/arm/include/asm/dma-mapping.h.
Quoted 7 lines
Suggested-by Bin Meng <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>--- arch/x86/include/asm/dma-mapping.h | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 arch/x86/include/asm/dma-mapping.h
PATCH v2 1/3 x86: Add dma-mapping.h to architectural code
Quoted 15 lines · Simon Glass
Quoted 5 lines · Andy Shevchenko
Some cross-platform drivers rely on this header present. Make it so for x86.
It's just a copy'n'paste of
arch/arm/include/asm/dma-mapping.h.Quoted 7 lines
Suggested-by Bin Meng <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>--- arch/x86/include/asm/dma-mapping.h | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 arch/x86/include/asm/dma-mapping.h
Quoted 1 line
Reviewed-by Simon Glass <[email protected]>
applied to u-boot-x86, thanks!
PATCH v2 2/3 x86: Add Intel Tangier support
In reply to Andy ShevchenkoFrom: Felipe Balbi <[email protected]>
Add Intel Tangier SoC support.
Intel Tangier SoC is a core part of Intel Merrifield platform. For example, Intel Edison board is based on such platform.
The patch is based on work done by the following people (in alphabetical order):
Aiden Park <[email protected]>
Dukjoon Jeon <[email protected]>
eric.park <[email protected]>
Fabien Chereau <[email protected]>
Scott D Phillips <[email protected]> Sebastien Colleur <[email protected]> Steve Sakoman <[email protected]>
Vincent Tinelli <[email protected]>
--- arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/tangier/Kconfig | 20 ++++ arch/x86/cpu/tangier/Makefile | 7 ++ arch/x86/cpu/tangier/car.S | 13 +++ arch/x86/cpu/tangier/sdram.c | 206 +++++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/tangier/tangier.c | 34 +++++++ arch/x86/include/asm/sfi.h | 19 ++++ 8 files changed, 301 insertions(+) create mode 100644 arch/x86/cpu/tangier/Kconfig create mode 100644 arch/x86/cpu/tangier/Makefile create mode 100644 arch/x86/cpu/tangier/car.S create mode 100644 arch/x86/cpu/tangier/sdram.c create mode 100644 arch/x86/cpu/tangier/tangier.c
arch/x86/Kconfig +1 -0
@@ -114,6 +114,7 @@ source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" +source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below
arch/x86/cpu/Makefile +1 -0
@@ -34,6 +34,7 @@ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ +obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-y += lapic.o ioapic.o obj-y += irq.o ifndef CONFIG_$(SPL_)X86_64
arch/x86/cpu/tangier/Kconfig new file +20 -0
@@ -0,0 +1,20 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_TANGIER + bool + depends on INTEL_MID + +config SYS_CAR_ADDR + hex + default 0x19200000 + +config SYS_CAR_SIZE + hex + default 0x4000 + help + Space in bytes in eSRAM used as Cache-As-RAM (CAR). + Note this size must not exceed eSRAM's total size.
arch/x86/cpu/tangier/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += car.o tangier.o sdram.o
arch/x86/cpu/tangier/car.S new file +13 -0
@@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010-2011 + * Graeme Russ, <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.section .text + +.globl car_init +car_init: + jmp car_init_ret
arch/x86/cpu/tangier/sdram.c new file +206 -0
206 lines not on this page · raw message
arch/x86/cpu/tangier/tangier.c new file +34 -0
@@ -0,0 +1,34 @@ +/* +* Copyright (c) 2017 Intel Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR ; + +/* +* Miscellaneous platform dependent initializations +*/ +int arch_cpu_init (void ) +{ +return x86_cpu_init_f (); +} + +int checkcpu (void ) +{ +return 0 ; +} + +int print_cpuinfo (void ) +{ +return default_print_cpuinfo (); +} + +void reset_cpu (ulong addr) +{ +scu_ipc_simple_command (IPCMSG_COLD_RESET ,0 ); +}
arch/x86/include/asm/sfi.h +19 -0
@@ -60,6 +60,25 @@ struct __packed sfi_mem_entry {u64 attrib; }; +/* Memory type definitions */ +enum sfi_mem_type { +SFI_MEM_RESERVED , +SFI_LOADER_CODE , +SFI_LOADER_DATA , +SFI_BOOT_SERVICE_CODE , +SFI_BOOT_SERVICE_DATA , +SFI_RUNTIME_SERVICE_CODE , +SFI_RUNTIME_SERVICE_DATA , +SFI_MEM_CONV , +SFI_MEM_UNUSABLE , +SFI_ACPI_RECLAIM , +SFI_ACPI_NVS , +SFI_MEM_MMIO , +SFI_MEM_IOPORT , +SFI_PAL_CODE , +SFI_MEM_TYPEMAX , +}; +struct __packed sfi_cpu_table_entry {u32 apic_id; };
Signature · 1 line
2.11.0
PATCH v2 2/3 x86: Add Intel Tangier support
Quoted 22 lines · Andy Shevchenko
From: Felipe Balbi <[email protected]>
Add Intel Tangier SoC support.
Intel Tangier SoC is a core part of Intel Merrifield platform. For example, Intel Edison board is based on such platform.
The patch is based on work done by the following people (in alphabetical order):
Aiden Park <[email protected]>
Dukjoon Jeon <[email protected]>
eric.park <[email protected]>
Fabien Chereau <[email protected]>
Scott D Phillips <[email protected]> Sebastien Colleur <[email protected]> Steve Sakoman <[email protected]>
Vincent Tinelli <[email protected]>Reviewed-by Simon Glass <[email protected]>Signed-off-by Vincent Tinelli <[email protected]>Signed-off-by Felipe Balbi <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>
Quoted 16 lines
--- arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/tangier/Kconfig | 20 ++++ arch/x86/cpu/tangier/Makefile | 7 ++ arch/x86/cpu/tangier/car.S | 13 +++ arch/x86/cpu/tangier/sdram.c | 206 +++++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/tangier/tangier.c | 34 +++++++ arch/x86/include/asm/sfi.h | 19 ++++ 8 files changed, 301 insertions(+) create mode 100644 arch/x86/cpu/tangier/Kconfig create mode 100644 arch/x86/cpu/tangier/Makefile create mode 100644 arch/x86/cpu/tangier/car.S create mode 100644 arch/x86/cpu/tangier/sdram.c create mode 100644 arch/x86/cpu/tangier/tangier.c
PATCH v2 3/3 x86: Add Intel Edison board files
In reply to Andy ShevchenkoAdd Intel Edison board which is using U-Boot.
The patch is based on work done by the following people (in alphabetical order):
Aiden Park <[email protected]>
Dukjoon Jeon <[email protected]>
eric.park <[email protected]>
Fabien Chereau <[email protected]>
Felipe Balbi <[email protected]>
Scott D Phillips <[email protected]> Sebastien Colleur <[email protected]> Steve Sakoman <[email protected]>
Vincent Tinelli <[email protected]>
In case we're building for Intel Edison, we must have 4096 bytes of zeroes in the beginning on u-boot.bin. This is done in board/intel/edison/config.mk.
First run sets hardware_id environment variable which is read from System Controller Unit (SCU).
Serial number (serial# environment variable) is generated based on eMMC CID.
MAC address on USB network interface is unique to the board but kept the same all over the time.
Set mac address from U-Boot using following scheme:
OUI = 02:00:86 next 3 bytes of MAC address set from eMMC serial number
This allows to have a unique mac address across reboot and flashing.
--- arch/x86/cpu/tangier/Kconfig | 4 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/edison.dts | 89 ++++++++++++++++++++++++++++++++ board/intel/Kconfig | 8 +++ board/intel/edison/Kconfig | 26 ++++++++++ board/intel/edison/Makefile | 1 + board/intel/edison/config.mk | 18 +++++++ board/intel/edison/edison.c | 104 ++++++++++++++++++++++++++++++++++++++ board/intel/edison/edison_start.S | 13 +++++ configs/edison_defconfig | 53 +++++++++++++++++++ doc/README.x86 | 39 ++++++++++++++ include/configs/edison.h | 78 ++++++++++++++++++++++++++++ 12 files changed, 434 insertions(+) create mode 100644 arch/x86/dts/edison.dts create mode 100644 board/intel/edison/Kconfig create mode 100644 board/intel/edison/Makefile create mode 100644 board/intel/edison/config.mk create mode 100644 board/intel/edison/edison.c create mode 100644 board/intel/edison/edison_start.S create mode 100644 configs/edison_defconfig create mode 100644 include/configs/edison.h
arch/x86/cpu/tangier/Kconfig +4 -0
@@ -18,3 +18,7 @@ config SYS_CAR_SIZE help Space in bytes in eSRAM used as Cache-As-RAM (CAR). Note this size must not exceed eSRAM's total size. + +config SYS_USB_OTG_BASE + hex + default 0xf9100000
arch/x86/dts/Makefile +1 -0
@@ -10,6 +10,7 @@ dtb-y += bayleybay.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ + edison.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \
arch/x86/dts/edison.dts new file +89 -0
89 lines not on this page · raw message
board/intel/Kconfig +8 -0
@@ -35,6 +35,13 @@ config TARGET_CROWNBAY Intel Platform Controller Hub EG20T, other system components and peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. +config TARGET_EDISON + bool "Edison" + help + This is the Intel Edison Compute Module. It contains a dual core Intel + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. + config TARGET_GALILEO bool "Galileo" help
@@ -64,6 +71,7 @@ endchoice source "board/intel/bayleybay/Kconfig" source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" +source "board/intel/edison/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig"
board/intel/edison/Kconfig new file +26 -0
@@ -0,0 +1,26 @@ +if TARGET_EDISON + +config SYS_BOARD + default "edison" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "tangier" + +config SYS_CONFIG_NAME + default "edison" + +config SYS_TEXT_BASE + default 0x01101000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_LOAD_FROM_32_BIT + select INTEL_MID + select INTEL_TANGIER + select BOARD_LATE_INIT + select MD5 + +endif
board/intel/edison/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-y += edison_start.o edison.o
board/intel/edison/config.mk new file +18 -0
@@ -0,0 +1,18 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause +# + +# Add 4096 bytes of zeroes to u-boot.bin +quiet_cmd_mkalign_eds = EDSALGN $@ +cmd_mkalign_eds = \ + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $^ + +ALL-y += u-boot-align.bin +u-boot-align.bin: u-boot.bin + $(call if_changed,mkalign_eds) + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
board/intel/edison/edison.c new file +104 -0
104 lines not on this page · raw message
board/intel/edison/edison_start.S new file +13 -0
@@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, [email protected]. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp early_board_init_ret
configs/edison_defconfig new file +53 -0
53 lines not on this page · raw message
doc/README.x86 +39 -0
@@ -18,6 +18,8 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link work with minimal adjustments on other x86 boards since coreboot deals with most of the low-level details. +U-boot is a main bootloader on Intel Edison board. + U-Boot also supports booting directly from x86 reset vector, without coreboot. In this case, known as bare mode, from the fact that it runs on the 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
@@ -61,6 +63,16 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board. +Build Instructions for U-Boot as main bootloader +------------------------------------------------ + +Intel Edison instructions: + +Simple you can build U-Boot and obtain u-boot.bin + +$ make edison_defconfig +$ make all + Build Instructions for U-Boot as BIOS replacement (bare mode) ------------------------------------------------------------- Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
@@ -455,6 +467,33 @@ Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, => zboot 01000000 - 04000000 1b1ab50 +Updating U-Boot on Edison +------------------------- +By default Intel Edison boards are shipped with preinstalled heavily +patched U-Boot v2014.04. Though it supports DFU which we may be able to +use. + +1. Prepare u-boot.bin as described in chapter above. You still need one +more step (if and only if you have original U-Boot), i.e. run the +following command: + +$ truncate -s %4096 u-boot.bin + +2. Run your board and interrupt booting to U-Boot console. In the console +call: + + => run do_force_flash_os + +3. Wait for few seconds, it will prepare environment variable and runs +DFU. Run DFU command from the host system: + +$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin + +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and +reset the board: + + => reset + CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [8] to be
include/configs/edison.h new file +78 -0
78 lines not on this page · raw message
Signature · 1 line
2.11.0
PATCH v2 3/3 x86: Add Intel Edison board files
Hi Andy,
Quoted 50 lines · Andy Shevchenko
Add Intel Edison board which is using U-Boot.
The patch is based on work done by the following people (in alphabetical order):
Aiden Park <[email protected]>
Dukjoon Jeon <[email protected]>
eric.park <[email protected]>
Fabien Chereau <[email protected]>
Felipe Balbi <[email protected]>
Scott D Phillips <[email protected]> Sebastien Colleur <[email protected]> Steve Sakoman <[email protected]>
Vincent Tinelli <[email protected]>In case we're building for Intel Edison, we must have 4096 bytes of zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.First run sets
hardware_idenvironment variable which is read from System Controller Unit (SCU).Serial number (serial# environment variable) is generated based on eMMC CID.
MAC address on USB network interface is unique to the board but kept the same all over the time.
Set mac address from U-Boot using following scheme:
OUI = 02:00:86
next 3 bytes of MAC address set from eMMC serial numberThis allows to have a unique mac address across reboot and flashing.
Signed-off-by Vincent Tinelli <[email protected]>Signed-off-by Felipe Balbi <[email protected]>Signed-off-by Andy Shevchenko <[email protected]>--- arch/x86/cpu/tangier/Kconfig | 4 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/edison.dts | 89 ++++++++++++++++++++++++++++++++ board/intel/Kconfig | 8 +++ board/intel/edison/Kconfig | 26 ++++++++++ board/intel/edison/Makefile | 1 + board/intel/edison/config.mk | 18 +++++++ board/intel/edison/edison.c | 104 ++++++++++++++++++++++++++++++++++++++ board/intel/edison/edison_start.S | 13 +++++ configs/edison_defconfig | 53 +++++++++++++++++++ doc/README.x86 | 39 ++++++++++++++ include/configs/edison.h | 78 ++++++++++++++++++++++++++++ 12 files changed, 434 insertions(+)
Quoted 9 lines
create mode 100644 arch/x86/dts/edison.dts create mode 100644 board/intel/edison/Kconfig create mode 100644 board/intel/edison/Makefile create mode 100644 board/intel/edison/config.mk create mode 100644 board/intel/edison/edison.c create mode 100644 board/intel/edison/edison_start.S create mode 100644 configs/edison_defconfig create mode 100644 include/configs/edison.h
Thank you for your efforts to bring edition support upstream! Looks quite clean. A few comments below.
arch/x86/cpu/tangier/Kconfig config SYS_CAR_SIZE · line 24
Quoted 12 lines
arch/x86/cpu/tangier/Kconfig +4
-0@@ -18,3 +18,7 @@ config SYS_CAR_SIZE help Space in bytes in eSRAM used as Cache-As-RAM (CAR). Note this size must not exceed eSRAM's total size. + +config SYS_USB_OTG_BASE + hex + default 0xf9100000
Can this otg controller be put into device tree, like other peripherals?
board/intel/edison/edison_start.S
Quoted 307 lines
arch/x86/dts/Makefile +1
-0@@ -10,6 +10,7 @@ dtb-y += bayleybay.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ + edison.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \arch/x86/dts/edison.dts new file +89
-0@@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Edison"; + compatible = "intel,edison"; + + aliases { + serial0 = &serial0; + }; + + chosen { + stdout-path = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <2>; + }; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + serial0: serial at ff010180 { + compatible = "intel,mid-uart"; + reg = <0xff010180 0x100>; + reg-shift = <0>; + clock-frequency = <29491200>; + current-speed = <115200>; + }; + + emmc: mmc at ff3fc000 { + compatible = "intel,sdhci-tangier"; + reg = <0xff3fc000 0x1000>; + }; + +/* + * FIXME: For now U-Boot DM model doesn't allow to power up this controller. + * Enabling it will make U-Boot hang. + * + sdcard: mmc at ff3fa000 { + compatible = "intel,sdhci-tangier"; + reg = <0xff3fa000 0x1000>; + }; + */ + + pmu: power at ff00b000 { + compatible = "intel,pmu-mid"; + reg = <0xff00b000 0x1000>; + }; + + scu: ipc at ff009000 { + compatible = "intel,scu-ipc"; + reg = <0xff009000 0x1000>; + }; +};board/intel/Kconfig +8
-0@@ -35,6 +35,13 @@ config TARGET_CROWNBAY Intel Platform Controller Hub EG20T, other system components and peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. +config TARGET_EDISON + bool "Edison" + help + This is the Intel Edison Compute Module. It contains a dual core Intel + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. + config TARGET_GALILEO bool "Galileo" help@@ -64,6 +71,7 @@ endchoice source "board/intel/bayleybay/Kconfig" source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" +source "board/intel/edison/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig"board/intel/edison/Kconfig new file +26
-0@@ -0,0 +1,26 @@ +if TARGET_EDISON + +config SYS_BOARD + default "edison" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "tangier" + +config SYS_CONFIG_NAME + default "edison" + +config SYS_TEXT_BASE + default 0x01101000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_LOAD_FROM_32_BIT + select INTEL_MID + select INTEL_TANGIER + select BOARD_LATE_INIT + select MD5 + +endifboard/intel/edison/Makefile new file +1
-0@@ -0,0 +1 @@ +obj-y += edison_start.o edison.oboard/intel/edison/config.mk new file +18
-0@@ -0,0 +1,18 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause +# + +# Add 4096 bytes of zeroes to u-boot.bin +quiet_cmd_mkalign_eds = EDSALGN $@ +cmd_mkalign_eds = \ + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $^ + +ALL-y += u-boot-align.bin +u-boot-align.bin: u-boot.bin + $(call if_changed,mkalign_eds) + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macrosboard/intel/edison/edison.c new file +104
-0@@ -0,0 +1,104 @@ +/* +* Copyright (c) 2017 Intel Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#include <common.h> +#include <dwc3-uboot.h> +#include <mmc.h> +#include <u-boot/md5.h> +#include <usb.h> +#include <watchdog.h> + +#include <linux/usb/gadget.h> + +#include <asm/cache.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR ; + +static struct dwc3_device dwc3_device_data = { + .maximum_speed =USB_SPEED_HIGH , + .base =CONFIG_SYS_USB_OTG_BASE , + .dr_mode =USB_DR_MODE_PERIPHERAL , + .index =0 , +}; + +int usb_gadget_handle_interrupts (int controller_index) +{ +dwc3_uboot_handle_interrupt (controller_index); +WATCHDOG_RESET (); +return 0 ; +} + +int board_usb_init (int index,enum usb_init_type init) +{ +if (index ==0 && init ==USB_INIT_DEVICE ) +return dwc3_uboot_init (&dwc3_device_data); +return -EINVAL ; +} + +int board_usb_cleanup (int index,enum usb_init_type init) +{ +if (index ==0 && init ==USB_INIT_DEVICE ) { +dwc3_uboot_exit (index); +return 0 ; + } +return -EINVAL ; +} + +static void assign_serial (void ) +{ +struct mmc *mmc =find_mmc_device (0 ); +unsigned char ssn[16 ]; +char usb0addr[18 ]; +char serial[33 ]; +int i; + +if (!mmc) +return ; + +md5 ((unsigned char *)mmc->cid,sizeof (mmc->cid), ssn); + +snprintf (usb0addr,sizeof (usb0addr),"02:00:86:%02x:%02x:%02x" , + ssn[13 ], ssn[14 ], ssn[15 ]); +setenv ("usb0addr" , usb0addr); + +for (i =0 ; i <16 ; i++) +snprintf (&serial[2 * i],3 ,"%02x" , ssn[i]); +setenv ("serial#" , serial); + +#if defined(CONFIG_CMD_SAVEENV ) && !defined(CONFIG_ENV_IS_NOWHERE ) +saveenv (); +#endif +} + +static void assign_hardware_id (void ) +{ +struct ipc_ifwi_version v; +char hardware_id[4 ]; +int ret; + + ret =scu_ipc_command (IPCMSG_GET_FW_REVISION ,1 ,NULL ,0 , (u32 *)&v,4 ); +if (ret <0 ) +printf ("Can't retrieve hardware revision\n" ); + +snprintf (hardware_id,sizeof (hardware_id),"%02X" , v.hardware_id); +setenv ("hardware_id" , hardware_id); + +#if defined(CONFIG_CMD_SAVEENV ) && !defined(CONFIG_ENV_IS_NOWHERE ) +saveenv (); +#endif +} + +int board_late_init (void ) +{ +if (!getenv ("serial#" )) +assign_serial (); + +if (!getenv ("hardware_id" )) +assign_hardware_id (); + +return 0 ; +}board/intel/edison/edison_start.S +0
-0
This file should be renamed to just start.S
Quoted 82 lines
new file mode 100644
index 0000000000..932fe6c24bboard/intel/edison/edison_start.S new file +13
-0@@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ at gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp early_board_init_retconfigs/edison_defconfig new file +53
-0@@ -0,0 +1,53 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="edison" +CONFIG_TARGET_EDISON=y +CONFIG_SMP=y +# CONFIG_ARCH_EARLY_INIT_R is not set +# CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ENV_CALLBACK=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_TIMER=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_CPU=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_TANGIER=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_DM_RTC=y +CONFIG_INTEL_MID_SERIAL=y +CONFIG_TIMER=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Intel" +CONFIG_G_DNL_VENDOR_NUM=0x8087 +CONFIG_G_DNL_PRODUCT_NUM=0x0a99 +CONFIG_TANGIER_WATCHDOG=y +CONFIG_FAT_WRITE=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SHA1=ydoc/README.x86 +0
-0
doc/README.x86 U-Boot supports running as a coreboot [1] payload on x86. So far only Link · line 21
Quoted 4 lines
doc/README.x86 +1
-0@@ -18,6 +18,8 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link work with minimal adjustments on other x86 boards since coreboot deals with most of the low-level details. +U-boot is a main bootloader on Intel Edison board.
U-Boot
Quoted 42 lines
doc/README.x86 +28
-0+ U-Boot also supports booting directly from x86 reset vector, without coreboot. In this case, known as bare mode, from the fact that it runs on the 'bare metal', U-Boot acts like a BIOS replacement. The following platforms@@ -61,6 +63,16 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board. +Build Instructions for U-Boot as main bootloader +------------------------------------------------ + +Intel Edison instructions: + +Simple you can build U-Boot and obtain u-boot.bin + +$ make edison_defconfig +$ make all + Build Instructions for U-Boot as BIOS replacement (bare mode) ------------------------------------------------------------- Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a@@ -455,6 +467,33 @@ Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, => zboot 01000000 - 04000000 1b1ab50 +Updating U-Boot on Edison +------------------------- +By default Intel Edison boards are shipped with preinstalled heavily +patched U-Boot v2014.04. Though it supports DFU which we may be able to +use. + +1. Prepare u-boot.bin as described in chapter above. You still need one +more step (if and only if you have original U-Boot), i.e. run the +following command: + +$ truncate -s %4096 u-boot.bin + +2. Run your board and interrupt booting to U-Boot console. In the console +call: + + => run do_force_flash_os +
doc/README.x86 Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, · line 496
Quoted 10 lines
doc/README.x86 +10
-0+3. Wait for few seconds, it will prepare environment variable and runs +DFU. Run DFU command from the host system: + +$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin + +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and +reset the board: + + => reset +
Are there instructions on how to program U-Boot on a board that does not have pre-flashed U-Boot? or in a situation that users flashed a bad image that makes the board brick.
Quoted 11 lines
doc/README.x86 +0
-0CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [8] to beinclude/configs/edison.h new file +2
-0@@ -0,0 +1,78 @@ +/* +* Copyright (c) 2017 Intel Corp.
include/configs/edison.h line 12
Quoted 10 lines
include/configs/edison.h new file +10
-0+* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/ibmpc.h> + +/*-----------------------------------------------------------------------
nits: /* Boot */
include/configs/edison.h line 22
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include/configs/edison.h new file +10
-0+* Boot +*/ + +#define CONFIG_CMD_ZBOOT +#define CONFIG_BOOTCOMMAND "run bootcmd" + +/*----------------------------------------------------------------------- +* DISK Partition support +*/ +
ditto
Quoted 47 lines
include/configs/edison.h new file +47
-0+#define CONFIG_RANDOM_UUID + +/* +* Miscellaneous configurable options +*/ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_AUTO_COMPLETE + +/*----------------------------------------------------------------------- +* Memory +*/ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_PHYSMEM + +#define CONFIG_NR_DRAM_BANKS 3 + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) + +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 + +/*----------------------------------------------------------------------- +* Environment +*/ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_SIZE (64 * 1024) +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) +#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) +#define CONFIG_SUPPORT_EMMC_BOOT + +/*----------------------------------------------------------------------- +* PCI +*/ + +#define CONFIG_CMD_PCI
include/configs/edison.h
Quoted 10 lines
include/configs/edison.h new file +9
-1+ +/*----------------------------------------------------------------------- +* RTC +*/ + +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_RTC_MC146818 + +#endif --
Regards,
Bin
PATCH v2 3/3 x86: Add Intel Edison board files
Quoted 6 lines · Bin Meng
Hi Andy,
Quoted 1 line · Andy Shevchenko
Add Intel Edison board which is using U-Boot.
Thanks for review, my answers below.
Quoted 2 lines
Thank you for your efforts to bring edition support upstream! Looks quite clean. A few comments below.
I hope to see it soon there!
Quoted 6 lines
Quoted 3 lines
+config
SYS_USB_OTG_BASE
+ hex
+ default0xf9100000Can this otg controller be put into device tree, like other peripherals?
I will check the possibility.
Quoted 4 lines
board/intel/edison/edison_start.S
Quoted 2 lines
board/intel/edison/edison_start.S +0
-0This file should be renamed to just
start.S
Done.
Quoted 3 lines
Quoted 1 line
+U-boot is a main bootloader on Intel Edison board.
U-Boot
Fixed.
Quoted 3 lines
Are there instructions on how to program U-Boot on a board that does not have pre-flashed U-Boot? or in a situation that users flashed a bad image that makes the board brick.
We assume that board is supplied with official image. There is official documentation how to "unbrick" board to the stock state. So, I consider it out of scope of U-Boot documentation.
Quoted 4 lines
Quoted 2 lines
+/*-----------------------------------------------------------------
------nits: /* Boot */
Fixed (all cases).
Signature · 2 lines
Andy Shevchenko <[email protected]> Intel Finland Oy
PATCH v2 3/3 x86: Add Intel Edison board files
Quoted 7 lines · Andy Shevchenko
Quoted 5 lines · Bin Meng
Hi Andy,
Quoted 1 line · Andy Shevchenko
Add Intel Edison board which is using U-Boot.
Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
+config
SYS_USB_OTG_BASE
+ hex
+ default0xf9100000Can this otg controller be put into device tree, like other peripherals?
I will check the possibility.
Is it show stopper? To keep things simpler it would be better to keep board initialization in place and move forward later.
Felipe, what is your opinion on the topic?
Signature · 2 lines
Andy Shevchenko <[email protected]> Intel Finland Oy
PATCH v2 3/3 x86: Add Intel Edison board files
Hi,
Quoted 15 lines · Andy Shevchenko
Quoted 14 lines · Andy Shevchenko
Quoted 12 lines · Bin Meng
Hi Andy,
Quoted 5 lines · Andy Shevchenko
Add Intel Edison board which is using U-Boot.
+config
SYS_USB_OTG_BASE
+ hex
+ default0xf9100000Can this otg controller be put into device tree, like other peripherals?
Quoted 6 lines
Quoted 1 line
I will check the possibility.
Is it show stopper? To keep things simpler it would be better to keep board initialization in place and move forward later.
Felipe, what is your opinion on the topic?
IIRC, there are some folks working on moving DWC3 to DM. Frankly, I would rather not wait for the conversion before merging Edison's board-file. After the driver is switched to DM, adding another node on DT isn't really a lot of work by any stretch of the imagination.
Signature · 8 lines
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PATCH v2 3/3 x86: Add Intel Edison board files
Hi Felipe,
Quoted 24 lines · Felipe Balbi
Hi,
Quoted 20 lines · Andy Shevchenko
Quoted 7 lines · Andy Shevchenko
Quoted 5 lines · Bin Meng
Hi Andy,
Quoted 1 line · Andy Shevchenko
Add Intel Edison board which is using U-Boot.
Quoted 8 lines
Quoted 6 lines
arch/x86/cpu/tangier/Kconfig config SYS_CAR_SIZE · line 24
Quoted 3 lines
arch/x86/cpu/tangier/Kconfig +3
-0+config SYS_USB_OTG_BASE + hex + default 0xf9100000Can this otg controller be put into device tree, like other peripherals?
I will check the possibility.
Is it show stopper? To keep things simpler it would be better to keep board initialization in place and move forward later.
Quoted 6 lines
Quoted 1 line
Felipe, what is your opinion on the topic?
IIRC, there are some folks working on moving DWC3 to DM. Frankly, I would rather not wait for the conversion before merging Edison's board-file. After the driver is switched to DM, adding another node on DT isn't really a lot of work by any stretch of the imagination.
Thanks for the clarification.
Regards,
Bin
PATCH v2 3/3 x86: Add Intel Edison board files
In reply to Andy ShevchenkoHi Andy,
Quoted 12 lines · Andy Shevchenko
Quoted 11 lines · Andy Shevchenko
Quoted 10 lines · Bin Meng
Hi Andy,
Quoted 5 lines · Andy Shevchenko
Add Intel Edison board which is using U-Boot.
arch/x86/cpu/tangier/Kconfig +3
-0+config SYS_USB_OTG_BASE + hex + default 0xf9100000
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines
Can this otg controller be put into device tree, like other peripherals?
I will check the possibility.
Is it show stopper? To keep things simpler it would be better to keep board initialization in place and move forward later.
It is not show stopper. But this needs to be addressed in future commits.
Quoted 3 lines
Felipe, what is your opinion on the topic?
--
Regards,
Bin