arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node

PATCH New Antoine Tenart 2 participants 4 messages Aug 24, 2017 – Aug 30, 2017

Subsystems (3)

Device tree bindings Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support Marvell macchiatobin support

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Antoine Tenart

author

2017-08-24 08:46 UTC #0 lore raw

PATCH v3 1/2 arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node

The network driver on Marvell SoC (7k/8k) needs to access some registers in the system controller to configure its ports at runtime. This patch adds a phandle reference to the syscon system controller node in the ppv2 node.

Signed-off-by Antoine Tenart <[email protected]>

Tested-by Marcin Wojtas <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 +
 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi  | 1 +
 2 files changed, 2 insertions(+)

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +1 -0

index 4c68605675a8..18299e164cb7 100644
@@ -65,6 +65,7 @@
 				reg = <0x0 0x100000>, <0x129000 0xb000>;
 				clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
 				clock-names = "pp_clk", "gop_clk", "mg_clk";
+				marvell,system-controller = <&cpm_syscon0>;
 				status = "disabled";
 				dma-coherent;

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +1 -0

index 923f354b02f0..5ae8fa575859 100644
@@ -72,6 +72,7 @@
 				reg = <0x0 0x100000>, <0x129000 0xb000>;
 				clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
 				clock-names = "pp_clk", "gop_clk", "mg_clk";
+				marvell,system-controller = <&cps_syscon0>;
 				status = "disabled";
 				dma-coherent;

Signature · 1 line

2.13.5

Antoine Tenart

author

2017-08-24 08:46 UTC #1 lore raw

PATCH v3 2/2 arm64: dts: marvell: mcbin: enable more networking ports

This patch enables the two GE/SFP ports. They are configured in 10GKR mode by default. To do this the cpm_xdmio is enabled as well, and two phy descriptions are added.

Signed-off-by Antoine Tenart <[email protected]>

Tested-by Marcin Wojtas <[email protected]>

---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +30 -0

index abd39d1c1739..9f0a00802452 100644
@@ -127,6 +127,30 @@
 	};
 };
 
+&cpm_xmdio {
+	status = "okay";
+
+	phy0: ethernet-phy at 0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+
+	phy8: ethernet-phy at 8 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth0 {
+	status = "okay";
+	phy = <&phy0>;
+	phy-mode = "10gbase-kr";
+};
+
 &cpm_sata0 {
 	/* CPM Lane 0 - U29 */
 	status = "okay";

@@ -154,6 +178,12 @@
 	status = "okay";
 };
 
+&cps_eth0 {
+	status = "okay";
+	phy = <&phy8>;
+	phy-mode = "10gbase-kr";
+};
+
 &cps_eth1 {
 	/* CPS Lane 0 - J5 (Gigabit RJ45) */
 	status = "okay";

Signature · 1 line

2.13.5

Antoine Tenart

author

2017-08-30 09:36 UTC #2 lore raw

PATCH v3 2/2 arm64: dts: marvell: mcbin: enable more networking ports

Hi Gregory,

Quoted 6 lines · Antoine Tenart

This patch enables the two GE/SFP ports. They are configured in 10GKR mode by default. To do this the cpm_xdmio is enabled as well, and two phy descriptions are added.
Signed-off-by Antoine Tenart <[email protected]>
Tested-by Marcin Wojtas <[email protected]>

These DT changes (patches 1/2 and 2/2) came along a series with patches on the PPv2 driver. All the net part was merged in linux-next, but these two dt patches were not taken because we all were in holidays.

I know it's very late, but it would be very nice to have these two patches merged for 4.14.

Thanks!
Antoine

Quoted 55 lines

---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +30 -0

index abd39d1c1739..9f0a00802452 100644
@@ -127,6 +127,30 @@
 	};
 };
 
+&cpm_xmdio {
+	status = "okay";
+
+	phy0: ethernet-phy at 0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+
+	phy8: ethernet-phy at 8 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth0 {
+	status = "okay";
+	phy = <&phy0>;
+	phy-mode = "10gbase-kr";
+};
+
 &cpm_sata0 {
 	/* CPM Lane 0 - U29 */
 	status = "okay";

@@ -154,6 +178,12 @@
 	status = "okay";
 };
 
+&cps_eth0 {
+	status = "okay";
+	phy = <&phy8>;
+	phy-mode = "10gbase-kr";
+};
+
 &cps_eth1 {
 	/* CPS Lane 0 - J5 (Gigabit RJ45) */
 	status = "okay";

Signature · 1 line

2.13.5

Signature · 10 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Gregory CLEMENT

2017-08-30 12:28 UTC #3 lore raw

PATCH v3 2/2 arm64: dts: marvell: mcbin: enable more networking ports

Hi Antoine,

Quoted 10 lines · Antoine Tenart

Hi Gregory,
Quoted 6 lines · Antoine Tenart
This patch enables the two GE/SFP ports. They are configured in 10GKR mode by default. To do this the cpm_xdmio is enabled as well, and two phy descriptions are added.
Signed-off-by Antoine Tenart <[email protected]>
Tested-by Marcin Wojtas <[email protected]>

Quoted 6 lines

These DT changes (patches 1/2 and 2/2) came along a series with patches on the PPv2 driver. All the net part was merged in linux-next, but these two dt patches were not taken because we all were in holidays.
I know it's very late, but it would be very nice to have these two patches merged for 4.14.

I added them to mvebu/dt64 and made a pull request with the patch from Thomas.

Thanks,

Gregory

Quoted 65 lines

Thanks!
Antoine

Quoted 55 lines

---
 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +30 -0

index abd39d1c1739..9f0a00802452 100644
@@ -127,6 +127,30 @@
 	};
 };
 
+&cpm_xmdio {
+	status = "okay";
+
+	phy0: ethernet-phy at 0 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+	};
+
+	phy8: ethernet-phy at 8 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+	};
+};
+
+&cpm_ethernet {
+	status = "okay";
+};
+
+&cpm_eth0 {
+	status = "okay";
+	phy = <&phy0>;
+	phy-mode = "10gbase-kr";
+};
+
 &cpm_sata0 {
 	/* CPM Lane 0 - U29 */
 	status = "okay";

@@ -154,6 +178,12 @@
 	status = "okay";
 };
 
+&cps_eth0 {
+	status = "okay";
+	phy = <&phy8>;
+	phy-mode = "10gbase-kr";
+};
+
 &cps_eth1 {
 	/* CPS Lane 0 - J5 (Gigabit RJ45) */
 	status = "okay";

Signature · 1 line

2.13.5

Signature · 3 lines

Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com