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PCI: aardvark: Fix masking and unmasking legacy INTx interrupts

PATCH Applied Pali Rohár 3 participants 3 messages Aug 20, 2021 – Aug 26, 2021

Subsystems (3)
PCI PCI native host bridge and endpoint drivers PCI driver for aardvark (Marvell Armada 3700)
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Pali Rohár

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#0 lore raw

PATCH 1/1 PCI: aardvark: Fix masking and unmasking legacy INTx interrupts

irq_mask and irq_unmask callbacks need to be properly guarded by raw spin locks as masking/unmasking procedure needs atomic read-modify-write operation on hardware register.

Signed-off-by Pali Rohár <[email protected]>
Reported-by Marc Zyngier <[email protected]>
Cc [email protected]
---
 drivers/pci/controller/pci-aardvark.c | 9 +++++++++
 1 file changed, 9 insertions(+)
drivers/pci/controller/pci-aardvark.c +9 -0
index fb8060160251..a49e8bad9f4f 100644
@@ -234,6 +234,7 @@ struct advk_pcie {
 	u8 wins_count;
 	struct irq_domain *irq_domain;
 	struct irq_chip irq_chip;
+	raw_spinlock_t irq_lock;
 	struct irq_domain *msi_domain;
 	struct irq_domain *msi_inner_domain;
 	struct irq_chip msi_bottom_irq_chip;

@@ -1087,22 +1088,28 @@ static void advk_pcie_irq_mask(struct irq_data *d)
 {
 	struct advk_pcie *pcie = d->domain->host_data;
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
+	unsigned long flags;
 	u32 mask;
 
+	raw_spin_lock_irqsave(&pcie->irq_lock, flags);
 	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
 	mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
 	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
+	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
 }
 
 static void advk_pcie_irq_unmask(struct irq_data *d)
 {
 	struct advk_pcie *pcie = d->domain->host_data;
 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
+	unsigned long flags;
 	u32 mask;
 
+	raw_spin_lock_irqsave(&pcie->irq_lock, flags);
 	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
 	mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
 	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
+	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
 }
 
 static int advk_pcie_irq_map(struct irq_domain *h,

@@ -1186,6 +1193,8 @@ static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
 	struct irq_chip *irq_chip;
 	int ret = 0;
 
+	raw_spin_lock_init(&pcie->irq_lock);
+
 	pcie_intc_node =  of_get_next_child(node, NULL);
 	if (!pcie_intc_node) {
 		dev_err(dev, "No PCIe Intc node found\n");
Signature · 1 line
2.20.1
Acked-by on v1 1/1
#1 lore raw
Quoted 8 lines · Pali Rohár

irq_mask and irq_unmask callbacks need to be properly guarded by raw spin locks as masking/unmasking procedure needs atomic read-modify-write operation on hardware register.

Signed-off-by Pali Rohár <[email protected]>
Reported-by Marc Zyngier <[email protected]>
Cc [email protected]
Acked-by Marc Zyngier <[email protected]>
	M.
Signature · 1 line
Without deviation from the norm, progress is not possible.