ARM: mvebu: Armada-38x DDR training update

index 160d30cd795a..1f7650cb3610 100644
@@ -212,7 +212,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,			/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_NORMAL,		/* temperature */
 	    MV_DDR_TIM_2T} },		/* timing */

@@ -234,7 +234,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_8GBIT,			/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_NORMAL,		/* temperature */
 	    MV_DDR_TIM_2T} },		/* timing */

index 92d7ae77f07e..bc18fe6ddf4a 100644
@@ -67,7 +67,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    SPEED_BIN_DDR_1866L,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_2GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */

index a8cfe8af0a88..9368bce26cee 100644
@@ -88,7 +88,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    SPEED_BIN_DDR_1866L,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_8BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */

index 824a08f12af8..9cbb33ff668d 100644
@@ -51,7 +51,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
-	    DDR_FREQ_533,		/* frequency */
+	    MV_DDR_FREQ_533,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */

index 341678319a46..15e78dee944b 100644
@@ -78,7 +78,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_8GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */

index 4e1386c8a223..1742aa8921c9 100644
@@ -65,7 +65,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    SPEED_BIN_DDR_1600K,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* mem_size */
-	    DDR_FREQ_800,		/* frequency */
+	    MV_DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_wl cas_l */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_DEFAULT} },	/* timing */

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index e29b1713f9a0..d388a172918f 100644
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
 
 static u32 bist_offset = 32;
 enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0;

index 03e5c9fdcea3..648b37ef6f79 100644
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
 
 #define VALIDATE_WIN_LENGTH(e1, e2, maxsize)		\
 	(((e2) + 1 > (e1) + (u8)MIN_WINDOW_SIZE) &&	\

@@ -698,6 +699,8 @@ int ddr3_tip_print_centralization_result(u32 dev_num)
 	u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
+	dev_num = dev_num;
+
 	printf("Centralization Results\n");
 	printf("I/F0 Result[0 - success 1-fail 2 - state_2 3 - state_3] ...\n");
 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {

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index 6b8aae83d759..db0f8ad7fb55 100644
@@ -4,6 +4,7 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
 
 #define VREF_INITIAL_STEP		3
 #define VREF_SECOND_STEP		1

index 531103c1abd5..056c21497c85 100644
@@ -6,12 +6,8 @@
 #ifndef _DDR3_TRAINING_IP_H_
 #define _DDR3_TRAINING_IP_H_
 
-#include "ddr3_training_ip_def.h"
 #include "ddr_topology_def.h"
-#include "ddr_training_ip_db.h"
 
-#define MAX_CS_NUM		4
-#define MAX_TOTAL_BUS_NUM	(MAX_INTERFACE_NUM * MAX_BUS_NUM)
 #define TIP_ENG_LOCK	0x02000000
 #define TIP_TX_DLL_RANGE_MAX	64
 

@@ -112,40 +108,11 @@ struct pattern_info {
 	u8 pattern_len;
 };
 
-/* CL value for each frequency */
-struct cl_val_per_freq {
-	u8 cl_val[DDR_FREQ_LAST];
-};
-
 struct cs_element {
 	u8 cs_num;
 	u8 num_of_cs;
 };
 
-struct mode_info {
-	/* 32 bits representing MRS bits */
-	u32 reg_mr0[MAX_INTERFACE_NUM];
-	u32 reg_mr1[MAX_INTERFACE_NUM];
-	u32 reg_mr2[MAX_INTERFACE_NUM];
-	u32 reg_m_r3[MAX_INTERFACE_NUM];
-	/*
-	 * Each element in array represent read_data_sample register delay for
-	 * a specific interface.
-	 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
-	 * cycles from read command until data is ready to be fetched from
-	 * the PHY, when accessing CS.
-	 */
-	u32 read_data_sample[MAX_INTERFACE_NUM];
-	/*
-	 * Each element in array represent read_data_sample register delay for
-	 * a specific interface.
-	 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
-	 * from read command until opening the read mask, when accessing CS.
-	 * This field defines the delay in DDR cycles granularity.
-	 */
-	u32 read_data_ready[MAX_INTERFACE_NUM];
-};
-
 struct hws_tip_freq_config_info {
 	u8 is_supported;
 	u8 bw_per_freq;

@@ -173,12 +140,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num,
 int hws_ddr3_tip_load_topology_map(u32 dev_num,
 				   struct mv_ddr_topology_map *topology);
 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
-int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
-int hws_ddr3_tip_read_training_result(u32 dev_num,
-		enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
 u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
 u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
-uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void);
-uint64_t mv_ddr_get_total_memory_size_in_bits(void);
 #endif /* _DDR3_TRAINING_IP_H_ */

index 2318ceba2920..2a68669f36c0 100644
@@ -75,32 +75,6 @@
 #define GET_RESULT_STATE(res)		(res)
 #define SET_RESULT_STATE(res, state)	(res = state)
 
-#define _1K				0x00000400
-#define _4K				0x00001000
-#define _8K				0x00002000
-#define _16K				0x00004000
-#define _32K				0x00008000
-#define _64K				0x00010000
-#define _128K				0x00020000
-#define _256K				0x00040000
-#define _512K				0x00080000
-
-#define _1M				0x00100000
-#define _2M				0x00200000
-#define _4M				0x00400000
-#define _8M				0x00800000
-#define _16M				0x01000000
-#define _32M				0x02000000
-#define _64M				0x04000000
-#define _128M				0x08000000
-#define _256M				0x10000000
-#define _512M				0x20000000
-
-#define _1G				0x40000000
-#define _2G				0x80000000
-#define _4G				0x100000000
-#define _8G				0x200000000
-
 #define ADDR_SIZE_512MB			0x04000000
 #define ADDR_SIZE_1GB			0x08000000
 #define ADDR_SIZE_2GB			0x10000000

@@ -126,11 +100,6 @@ enum hws_search_dir {
 	HWS_SEARCH_DIR_LIMIT
 };
 
-enum hws_page_size {
-	PAGE_SIZE_1K,
-	PAGE_SIZE_2K
-};
-
 enum hws_operation {
 	OPERATION_READ = 0,
 	OPERATION_WRITE = 1

index 334c2906fdbf..74417d61b4c5 100644
@@ -4,6 +4,8 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_regs.h"
+#include "ddr_training_ip_db.h"
 
 #define PATTERN_1	0x55555555
 #define PATTERN_2	0xaaaaaaaa

index 8fbcff50bb26..2d40e68db861 100644
@@ -8,6 +8,7 @@
 
 #include "ddr3_training_ip_def.h"
 #include "ddr3_training_ip_flow.h"
+#include "ddr3_training_ip_pbs.h"
 
 #define EDGE_1				0
 #define EDGE_2				1

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index f614d688c915..2df592e1b02d 100644
@@ -28,15 +28,15 @@ typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)(
 	u8 dev_num, enum hws_access_type interface_access, u32 if_id,
 	u32 offset, u32 data, u32 mask);
 typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)(
-	u8 dev_num, enum hws_ddr_freq freq,
+	u8 dev_num, enum mv_ddr_freq freq,
 	struct hws_tip_freq_config_info *freq_config_info);
 typedef int (*HWS_TIP_GET_DEVICE_INFO)(
 	u8 dev_num, struct ddr3_device_info *info_ptr);
 typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)(
 	u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
 typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)(
-	u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
-typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
+	u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
+typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq);
 typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)(
 	u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
 	u32 reg_addr, u32 data, u32 mask);

@@ -54,7 +54,7 @@ typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)(
 	u32 dev_num, enum hws_algo_type algo_type);
 typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)(
 	u32 dev_num, enum hws_access_type access_type, u32 if_id,
-	enum hws_ddr_freq frequency);
+	enum mv_ddr_freq frequency);
 typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)(
 	u32 dev_num, struct init_cntr_param *init_cntr_prm);
 typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num);

@@ -64,7 +64,7 @@ typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)(
 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
 	u32 dev_num, struct mv_ddr_topology_map *tm);
 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
-	u32 dev_num, enum hws_ddr_freq frequency,
+	u32 dev_num, enum mv_ddr_freq frequency,
 	enum hws_static_config_type static_config_type, u32 if_id);
 typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)(
 	u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);

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index 96d945a33d6e..6719fb83f518 100644
@@ -11,6 +11,5 @@
 int ddr3_tip_print_wl_supp_result(u32 dev_num);
 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
 			  u32 *cs_mask);
-u32 ddr3_tip_max_cs_get(u32 dev_num);
 
 #endif /* _DDR3_TRAINING_LEVELING_H_ */

index 0511026afbe2..b7dfebd93cc4 100644
@@ -4,6 +4,9 @@
  */
 
 #include "ddr3_init.h"
+#include "mv_ddr_training_db.h"
+#include "mv_ddr_common.h"
+#include "mv_ddr_regs.h"
 
 #define TYPICAL_PBS_VALUE	12
 

@@ -33,7 +36,7 @@ static u8 pup_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode)
 {
 	u32 res0[MAX_INTERFACE_NUM];
-	int adll_tap = MEGA / freq_val[medium_freq] / 64;
+	int adll_tap = MEGA / mv_ddr_freq_get(medium_freq) / 64;
 	int pad_num = 0;
 	enum hws_search_dir search_dir =
 		(pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH;

@@ -921,7 +924,7 @@ int ddr3_tip_pbs_tx(u32 uidev_num)
 int ddr3_tip_print_all_pbs_result(u32 dev_num)
 {
 	u32 curr_cs;
-	u32 max_cs = ddr3_tip_max_cs_get(dev_num);
+	unsigned int max_cs = mv_ddr_cs_num_get();
 
 	for (curr_cs = 0; curr_cs < max_cs; curr_cs++) {
 		ddr3_tip_print_pbs_result(dev_num, curr_cs, PBS_RX_MODE);

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index e7de5aef0ca7..f1b4d8efc0e1 100644
@@ -6,10 +6,8 @@
 #ifndef _DDR_TRAINING_IP_DB_H_
 #define _DDR_TRAINING_IP_DB_H_
 
-#include "ddr_topology_def.h"
 #include "ddr3_training_ip_db.h"
 
-u32 speed_bin_table(u8 index, enum speed_bin_table_elements element);
 u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
 
 #endif /* _DDR3_TRAINING_IP_DB_H_ */

new file mode 100644
index 000000000000..4d0846489b90
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ */
+
+#ifndef _DRAM_IF_H_
+#define _DRAM_IF_H_
+
+/* TODO: update atf to this new prototype */
+int dram_init(void);
+void dram_mmap_config(void);
+unsigned long long dram_iface_mem_sz_get(void);
+#endif /* _DRAM_IF_H_ */

index 2b49b77f7306..cc6234fd406c 100644
@@ -1,3 +1,3 @@
 // SPDX-License-Identifier: GPL-2.0
 const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-17.10.4";
+const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";

index c71ff442edd3..321a390c0d30 100644
@@ -9,10 +9,44 @@
 extern const char mv_ddr_build_message[];
 extern const char mv_ddr_version_string[];
 
-#define MV_DDR_NUM_BITS_IN_BYTE	8
-#define MV_DDR_MEGA_BITS	(1024 * 1024)
+#define _1K	0x00000400
+#define _4K	0x00001000
+#define _8K	0x00002000
+#define _16K	0x00004000
+#define _32K	0x00008000
+#define _64K	0x00010000
+#define _128K	0x00020000
+#define _256K	0x00040000
+#define _512K	0x00080000
+
+#define _1M	0x00100000
+#define _2M	0x00200000
+#define _4M	0x00400000
+#define _8M	0x00800000
+#define _16M	0x01000000
+#define _32M	0x02000000
+#define _64M	0x04000000
+#define _128M	0x08000000
+#define _256M	0x10000000
+#define _512M	0x20000000
+
+#define _1G	0x40000000
+#define _2G	0x80000000
+#define _4G	0x100000000
+#define _8G	0x200000000
+#define _16G	0x400000000
+#define _32G	0x800000000
+#define _64G	0x1000000000
+#define _128G	0x2000000000
+
+#define MEGA			1000000
+#define MV_DDR_MEGABYTE		(1024 * 1024)
 #define MV_DDR_32_BITS_MASK	0xffffffff
 
+#define GET_MAX_VALUE(x, y) \
+	(((x) > (y)) ? (x) : (y))
+
+void mv_ddr_ver_print(void);
 unsigned int ceil_div(unsigned int x, unsigned int y);
 unsigned int time_to_nclk(unsigned int t, unsigned int tclk);
 int round_div(unsigned int dividend, unsigned int divisor, unsigned int *quotient);

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