arm64: dts: marvell: mcbin: Enable PCIe interface
Subsystems (3)
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
--- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +6 -0
@@ -136,6 +136,12 @@ vqmmc-supply = <&v_3_3>; }; +&cpm_pcie0 { + /* CON 12 */ + num-lanes = <4>; + status = "okay"; +}; + &cpm_usb3_0 { /* J38? - USB2.0 only */ status = "okay";
Signature · 1 line
2.13.2
Russell King - ARM Linux
maintainerPATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>
Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";
+};
+
+ cpm_pcie_pins: pcie-pins {
+ marvell,pins = "mpp52";
+ marvell,function = "gpio";
+ };
Since you have merged GPIO and pinmux support for the v4.13 window, there's absolutely no reason not to include the GPIO bits. In fact, there's no reason not to consider using my bloody patches.
Except your stupid idiotic NiH problem that you seem to have.
I know that your behaviour in regard of this has been discussed within Marvell, and people are getting unhappy with free electron's attitude over this. You need to change, and start working _with_ people instead of constantly screwing people over.
So, NAK on your patch.
Once v4.13-rc1 is out, I'll update my patch series for the screw-over free-electrons has already done, and post some patches. I can't do it sooner, your work is scattered all over the place which makes it impossible to build upon, and afaics you've not published a consolidated tree.
Maybe the whole plan here is to "screw rmk" - that's exactly the message that I'm getting from you guys. You've no interest in working with others, you seem to want to out-right own everything Marvell and sod everyone else.
Signature · 3 lines
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 19 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
Review
Quoted 5 lines
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC PCIe driver will happily reconfigure the I/O window at runtime to perform config space accesses, without any locking whatsoever.
Russell King - ARM Linux
maintainerPATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 26 lines · Ard Biesheuvel
Quoted 19 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
Review
Quoted 5 lines
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";
Quoted 3 lines
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC PCIe driver will happily reconfigure the I/O window at runtime to perform config space accesses, without any locking whatsoever.
Thanks for the feedback, I'll integrate that change into my patch, so it's ready for when I rebase after -rc1.
Signature · 3 lines
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 20 lines · On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
Quoted 19 lines · Ard Biesheuvel
Quoted 18 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
Quoted 8 lines
Quoted 8 lines
Review
Quoted 6 lines
+&cpm_pcie0 {
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
IMHO, maybe putting this property into dtsi is better.
Thanks,
Jisheng
Quoted 6 lines
Quoted 2 lines
PCIe driver will happily reconfigure the I/O window at runtime to perform config space accesses, without any locking whatsoever.
Thanks for the feedback, I'll integrate that change into my patch, so it's ready for when I rebase after -rc1.
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 29 lines · Jisheng Zhang
Quoted 27 lines · On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
Quoted 26 lines · Ard Biesheuvel
Quoted 24 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";
Quoted 4 lines
Quoted 1 line
Quoted 1 line
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
IMHO, maybe putting this property into dtsi is better.
Good point. Do all instances of this IP that live on the SoC have 8 viewports?
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Hi Ard,
Quoted 30 lines · Ard Biesheuvel
Quoted 29 lines · Jisheng Zhang
Quoted 27 lines · On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
Quoted 26 lines · Ard Biesheuvel
Quoted 24 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";
Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
IMHO, maybe putting this property into dtsi is better.
Good point. Do all instances of this IP that live on the SoC have 8 viewports?
In the Armada 80x0 datasheet there is no mention of viewport. However 2 days ago you said that "What I do know is that boards like the Marvell 8040 based MacchiatoBin uses this IP in RC mode, and exposes config, MMIO and IO space windows using only 2 viewports. Note that this is essentially a bug in the DT description, given that its version of the IP supports 8 viewports."[1]
So you seem to know that the version of the IP used support the 8 viewports!
What I can also say is that the in the datasheet there is no mention of difference between the instance. The only thing that can differ is the number of lane for each PCIe Port.
Gregory
[1]: https://www.spinics.net/lists/arm-kernel/msg592091.html
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 49 lines · Gregory CLEMENT
Hi Ard,
Quoted 30 lines · Ard Biesheuvel
Quoted 29 lines · Jisheng Zhang
Quoted 27 lines · On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
Quoted 26 lines · Ard Biesheuvel
Quoted 24 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
IMHO, maybe putting this property into dtsi is better.
Good point. Do all instances of this IP that live on the SoC have 8 viewports?
In the Armada 80x0 datasheet there is no mention of viewport. However 2 days ago you said that "What I do know is that boards like the Marvell 8040 based MacchiatoBin uses this IP in RC mode, and exposes config, MMIO and IO space windows using only 2 viewports. Note that this is essentially a bug in the DT description, given that its version of the IP supports 8 viewports."[1]
Quoted 7 lines
So you seem to know that the version of the IP used support the 8 viewports!
What I can also say is that the in the datasheet there is no mention of difference between the instance. The only thing that can differ is the number of lane for each PCIe Port.
I am sure I found it in the datasheet somewhere. It is the number of ATU windows.
In any case, I implemented ACPI firmware for the MacchiatoBin, which also involves programming the PCIe RC in a mode that is compatible with ECAM. This turns out to be impossible (which means you cannot implement a SBSA compatible platform with this SoC), but in attempting to do so, I used five different windows, for type 0 config cycles, type 1 config cycles, IO space, MMIO32 space and MMIO64 space (which the Synopsys DW PCIe controller does not even implement, unfortunately)
Note that this also involved reprogramming all the memory translation windows from the secure firmware, to free up the region 0xc000_0000 - 0xefff_ffff for use by PCIe (config and MMIO32 space), and assigning a window 0x8_0000_0000 - 0x8_ffff_ffff for 64-bit MMIO BARs.
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Hi Ard,
Quoted 54 lines · Ard Biesheuvel
Quoted 52 lines · Gregory CLEMENT
Hi Ard,
Quoted 30 lines · Ard Biesheuvel
Quoted 29 lines · Jisheng Zhang
Quoted 27 lines · On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
Quoted 26 lines · Ard Biesheuvel
Quoted 24 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
IMHO, maybe putting this property into dtsi is better.
Good point. Do all instances of this IP that live on the SoC have 8 viewports?
In the Armada 80x0 datasheet there is no mention of viewport. However 2 days ago you said that "What I do know is that boards like the Marvell 8040 based MacchiatoBin uses this IP in RC mode, and exposes config, MMIO and IO space windows using only 2 viewports. Note that this is essentially a bug in the DT description, given that its version of the IP supports 8 viewports."[1]
So you seem to know that the version of the IP used support the 8 viewports!
Quoted 7 lines
Quoted 4 lines
What I can also say is that the in the datasheet there is no mention of difference between the instance. The only thing that can differ is the number of lane for each PCIe Port.
I am sure I found it in the datasheet somewhere. It is the number of ATU windows.
Under the "Outbound iATU Features" and "Inbound iATU Features" I have the following point:
"Up to 8 address regions programmable for location and size."
Is that what you think about ?
Quoted 10 lines
In any case, I implemented ACPI firmware for the MacchiatoBin, which also involves programming the PCIe RC in a mode that is compatible with ECAM. This turns out to be impossible (which means you cannot implement a SBSA compatible platform with this SoC), but in attempting to do so, I used five different windows, for type 0 config cycles, type 1 config cycles, IO space, MMIO32 space and MMIO64 space (which the Synopsys DW PCIe controller does not even implement, unfortunately)
Quoted 4 lines
Note that this also involved reprogramming all the memory translation windows from the secure firmware, to free up the region 0xc000_0000 - 0xefff_ffff for use by PCIe (config and MMIO32 space), and assigning a window 0x8_0000_0000 - 0x8_ffff_ffff for 64-bit MMIO BARs.
Currently for the driver the only important information is having a num-viewport greater than 2. So given all this we are OK if we add the 'num-viewport = <8>' in all the PCIe port node in the dtsi file.
Gregory
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 63 lines · Gregory CLEMENT
Hi Ard,
Quoted 59 lines · Ard Biesheuvel
Quoted 56 lines · Gregory CLEMENT
Hi Ard,
Quoted 30 lines · Ard Biesheuvel
Quoted 29 lines · Jisheng Zhang
Quoted 27 lines · On Wed, 5 Jul 2017 18:44:03 +0100 Russell King - ARM Linux wrote:
Quoted 26 lines · Ard Biesheuvel
Quoted 24 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Here's what I have:
+&cpm_pcie0 {
(quoted diff) +5
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay";Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line
This needs 'num-viewport = <8>' as well, or the crazy Synopsys DWC
IMHO, maybe putting this property into dtsi is better.
Good point. Do all instances of this IP that live on the SoC have 8 viewports?
In the Armada 80x0 datasheet there is no mention of viewport. However 2 days ago you said that "What I do know is that boards like the Marvell 8040 based MacchiatoBin uses this IP in RC mode, and exposes config, MMIO and IO space windows using only 2 viewports. Note that this is essentially a bug in the DT description, given that its version of the IP supports 8 viewports."[1]
So you seem to know that the version of the IP used support the 8 viewports!
What I can also say is that the in the datasheet there is no mention of difference between the instance. The only thing that can differ is the number of lane for each PCIe Port.
Quoted 9 lines
Quoted 2 lines
I am sure I found it in the datasheet somewhere. It is the number of ATU windows.
Under the "Outbound iATU Features" and "Inbound iATU Features" I have the following point:
"Up to 8 address regions programmable for location and size."Is that what you think about ?
Yes.
Quoted 10 lines
Quoted 10 lines
In any case, I implemented ACPI firmware for the MacchiatoBin, which also involves programming the PCIe RC in a mode that is compatible with ECAM. This turns out to be impossible (which means you cannot implement a SBSA compatible platform with this SoC), but in attempting to do so, I used five different windows, for type 0 config cycles, type 1 config cycles, IO space, MMIO32 space and MMIO64 space (which the Synopsys DW PCIe controller does not even implement, unfortunately)
Quoted 9 lines
Quoted 4 lines
Note that this also involved reprogramming all the memory translation windows from the secure firmware, to free up the region 0xc000_0000 - 0xefff_ffff for use by PCIe (config and MMIO32 space), and assigning a window 0x8_0000_0000 - 0x8_ffff_ffff for 64-bit MMIO BARs.
Currently for the driver the only important information is having a num-viewport greater than 2. So given all this we are OK if we add the 'num-viewport = <8>' in all the PCIe port node in the dtsi file.
OK. If the x4 and the x1 versions of the description in the manual both contain the sentence about 8 the address regions, then I think it is safe to include it for all 6 instances of this IP.
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
In reply to Russell King - ARM LinuxHi Russell King,
Quoted 9 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Enable the PCIe interface on the MACCHIATOBin board. It is located on CON12 and is 4 lanes capable.
Signed-off-by Gregory CLEMENT <[email protected]>Why do you folk at free-electrons like doing half a job all the friggin time?
Quoted 6 lines
You know I have complete patches for mcbin, but you pointedly won't look at them at all - except when you have a problem and want to test my tree. And even then, you ignore my work (despite testing that it works), and you still recreate my patches.
This is really frustrating and insane behaviour on your part.
Sorry for this, I wrongly assumed that if you had the PCIe part you would have already submitted it. Also I didn't expect there was a gpio dependency with PCIe because until now I never saw the reset-gpio for PCIe with the controller I use.
Quoted 28 lines
Here's what I have:
+&cpm_pcie0 {
(quoted diff) +11
-0+ pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_pins>; + num-lanes = <4>; + reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + + cpm_pcie_pins: pcie-pins { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + };Since you have merged GPIO and pinmux support for the v4.13 window, there's absolutely no reason not to include the GPIO bits. In fact, there's no reason not to consider using my bloody patches.
Except your stupid idiotic NiH problem that you seem to have.
I know that your behaviour in regard of this has been discussed within Marvell, and people are getting unhappy with free electron's attitude over this. You need to change, and start working _with_ people instead of constantly screwing people over.
Quoted 5 lines
So, NAK on your patch.
Once v4.13-rc1 is out, I'll update my patch series for the screw-over free-electrons has already done, and post some patches. I can't do it sooner, your work is scattered all over the place which makes it
Actually everything is available in the linux-next branch since one or two weeks. So you can rebase and send your series right now.
Gregory
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Russell King - ARM Linux
maintainerPATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Quoted 4 lines · Gregory CLEMENT
Hi Russell King,
Actually everything is available in the linux-next branch since one or two weeks. So you can rebase and send your series right now.
As there are multiple trees, just specifying a branch is not helpful. The Xenon SDHCI and ethernet changes were being published through the MISL tree, but that tree has no for-next branch.
There is no git tree specified in MAINTAINERS either.
So, sorry, I've no idea which tree you're referring to.
And no, I do _not_ want to grab a copy of linux-next to rebase my changes on and publish back to SolidRun for their use, that would be insane.
Signature · 3 lines
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.
PATCH 1/1 arm64: dts: marvell: mcbin: Enable PCIe interface
Hi Russell King,
Quoted 10 lines · Russell King - ARM Linux
Quoted 4 lines · Gregory CLEMENT
Hi Russell King,
Actually everything is available in the linux-next branch since one or two weeks. So you can rebase and send your series right now.
As there are multiple trees, just specifying a branch is not helpful. The Xenon SDHCI and ethernet changes were being published through the MISL tree, but that tree has no for-next branch.
Quoted 5 lines
There is no git tree specified in
MAINTAINERSeither.So, sorry, I've no idea which tree you're referring to.
And no, I do _not_ want to grab a copy of linux-next to rebase my
Well for upstreaming I don't see the problem to base on a linux-net tags such as next-20170704. We do it often when we submit patches to various subsystem (and if it is not a next tag we merge various branch by ourselves).
Quoted 2 lines
changes on and publish back to SolidRun for their use, that would be insane.
We also deliver stable branch for various customers and in this case we just have a different branch or tree.
However, I think we have exactly what meets your requirements:
https://github.com/MISL-EBU-System-SW/mainline-public/tree/4.12-rc6/backports
It is a stable branch which gathers most of the patch submitted for Armada 37xx, 7K and 8K.
Gregory
Quoted 5 lines
Signature · 4 lines
-- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com