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drm/i915/hsw: Fix workaround for server AUX channel clock divisor

PATCH In review [email protected] 2 participants 3 messages May 27, 2015 – May 28, 2015

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PATCH v2 1/1 drm/i915/hsw: Fix workaround for server AUX channel clock divisor

From: Jim Bride <[email protected]>

According to the HSW b-spec we need to try clock divisors of 63 and 72, each 3 or more times, when attempting DP AUX channel communication on a server chipset. This actually wasn't happening due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit in status rather than checking that the operation was done and that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

[v2] Implemented alternate solution suggested by Jani Nikula.

Signed-off-by Jim Bride <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +2 -3
index 0edc305..7d1e024 100644
@@ -893,10 +893,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 				continue;
 			}
 			if (status & DP_AUX_CH_CTL_DONE)
-				break;
+				goto done;
 		}
-		if (status & DP_AUX_CH_CTL_DONE)
-			break;
 	}
 
 	if ((status & DP_AUX_CH_CTL_DONE) == 0) {

@@ -905,6 +903,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		goto out;
 	}
 
+done:
 	/* Check for timeout or receive error.
 	 * Timeouts occur when the sink is not connected
 	 */
Signature · 6 lines
1.9.1

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maintainer Reviewed-by on v2 1/1
#1 lore raw
Quoted 9 lines · On Wed, 27 May 2015, [email protected] wrote:

From: Jim Bride <[email protected]>

According to the HSW b-spec we need to try clock divisors of 63 and 72, each 3 or more times, when attempting DP AUX channel communication on a server chipset. This actually wasn't happening due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit in status rather than checking that the operation was done and that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

Quoted 3 lines

[v2] Implemented alternate solution suggested by Jani Nikula.

Signed-off-by Jim Bride <[email protected]>
Cc [email protected]
Reviewed-by Jani Nikula <[email protected]>
Quoted 31 lines
---
 drivers/gpu/drm/i915/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +2 -3
index 0edc305..7d1e024 100644
@@ -893,10 +893,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 				continue;
 			}
 			if (status & DP_AUX_CH_CTL_DONE)
-				break;
+				goto done;
 		}
-		if (status & DP_AUX_CH_CTL_DONE)
-			break;
 	}
 
 	if ((status & DP_AUX_CH_CTL_DONE) == 0) {

@@ -905,6 +903,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		goto out;
 	}
 
+done:
 	/* Check for timeout or receive error.
 	 * Timeouts occur when the sink is not connected
 	 */
Signature · 1 line
1.9.1
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
maintainer
#2 lore raw
Quoted 10 lines · Jani Nikula
Quoted 9 lines · On Wed, 27 May 2015, [email protected] wrote:

From: Jim Bride <[email protected]>

According to the HSW b-spec we need to try clock divisors of 63 and 72, each 3 or more times, when attempting DP AUX channel communication on a server chipset. This actually wasn't happening due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit in status rather than checking that the operation was done and that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

Quoted 6 lines
Quoted 3 lines

[v2] Implemented alternate solution suggested by Jani Nikula.

Signed-off-by Jim Bride <[email protected]>
Cc [email protected]
Reviewed-by Jani Nikula <[email protected]>

...and pushed to drm-intel-fixes, thanks for the patch.

BR,
Jani.

Quoted 35 lines
Quoted 32 lines
---
 drivers/gpu/drm/i915/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +2 -3
index 0edc305..7d1e024 100644
@@ -893,10 +893,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 				continue;
 			}
 			if (status & DP_AUX_CH_CTL_DONE)
-				break;
+				goto done;
 		}
-		if (status & DP_AUX_CH_CTL_DONE)
-			break;
 	}
 
 	if ((status & DP_AUX_CH_CTL_DONE) == 0) {

@@ -905,6 +903,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		goto out;
 	}
 
+done:
 	/* Check for timeout or receive error.
 	 * Timeouts occur when the sink is not connected
 	 */
Signature · 1 line
1.9.1
Signature · 1 line
Jani Nikula, Intel Open Source Technology Center
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx