arm64: dts: marvell: mark CP110 ahci as dma-coherent
Subsystems (2)
PATCH 1/1 arm64: dts: marvell: mark CP110 ahci as dma-coherent
The hardware is clearly DMA coherent and not marking it as such leads to cache coherency problems, at least with the OpenBSD kernel.
Signed-off-by Mark Kettenis <[email protected]>
--- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/marvell/armada-cp110.dtsi +1 -0
@@ -231,6 +231,7 @@ compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; + dma-coherent; interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CP110_LABEL(clk) 1 15>; status = "disabled";
Signature · 1 line
2.16.2
Gregory CLEMENT
maintainerPATCH 1/1 arm64: dts: marvell: mark CP110 ahci as dma-coherent
Hi Mark,
Quoted 2 lines · Mark Kettenis
The hardware is clearly DMA coherent and not marking it as such leads to cache coherency problems, at least with the OpenBSD kernel.
The reason to not having this flag from the beginning was that there was some issue around it in the very first revision (A0) of the SoC. But now all the SoC publicly released belongs to a newer revision that don't have anymore this issue, so your patch make sense.
Applied on mvebu/dt64-for-4.18
Thanks,
Gregory
Quoted 21 lines
Signed-off-by Mark Kettenis <[email protected]>--- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 1 + 1 file changed, 1 insertion(+)arch/arm64/boot/dts/marvell/armada-cp110.dtsi +1
-0@@ -231,6 +231,7 @@ compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; + dma-coherent; interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CP110_LABEL(clk) 1 15>; status = "disabled";Signature · 1 line
2.16.2
Signature · 3 lines
Gregory Clement, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering http://bootlin.com