drm/i915: Baytrail MIPI DSI support
Subsystems (3)
v3 cover drm/i915: Baytrail MIPI DSI support
Hi all, v3 of [1] addressing (most of) Ville's review comments.
I am not reposting patch 1/15 to dri-devel, as it's unchanged since [2].
BR,
Jani.
[1] http://mid.gmane.org/[email protected]
[2] http://mid.gmane.org/[email protected]
Jani Nikula (10):
drm/i915: add more VLV IOSF sideband ports accessors drm/i915: add VLV pipeconf bit definition for DSI PLL lock drm/i915: add MIPI DSI register definitions drm/i915: add MIPI DSI output type and subtypes drm/i915: add structs for MIPI DSI output drm/i915: add MIPI DSI command sending routines drm/i915: add basic MIPI DSI output support drm/i915: fix PLL assertions for DSI PLL drm/i915: don't enable DPLL for DSI
drm/i915: initialize DSI output on VLV
Shobhit Kumar (4):
drm: add MIPI DSI encoder and connector types
drm/i915: Band Gap WA
drm/i915: Parse the MIPI related VBT Block and store relevant info drm/i915: add AUO MIPI DSI display sub-encoder
ymohanma (1):
drm/i915: add VLV DSI PLL Calculations
drivers/gpu/drm/drm_crtc.c | 2 + drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/auo_dsi_display.c | 182 ++++++++++ drivers/gpu/drm/i915/i915_drv.h | 13 + drivers/gpu/drm/i915/i915_reg.h | 447 +++++++++++++++++++++++ drivers/gpu/drm/i915/intel_bios.c | 16 + drivers/gpu/drm/i915/intel_bios.h | 41 +++ drivers/gpu/drm/i915/intel_display.c | 96 +++-- drivers/gpu/drm/i915/intel_drv.h | 7 +- drivers/gpu/drm/i915/intel_dsi.c | 626 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi.h | 105 ++++++ drivers/gpu/drm/i915/intel_dsi_cmd.c | 427 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 ++++++ drivers/gpu/drm/i915/intel_dsi_pll.c | 317 ++++++++++++++++ drivers/gpu/drm/i915/intel_sideband.c | 56 +++ include/uapi/drm/drm_mode.h | 2 + 16 files changed, 2421 insertions(+), 29 deletions(-) create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c create mode 100644 drivers/gpu/drm/i915/intel_dsi.c create mode 100644 drivers/gpu/drm/i915/intel_dsi.h create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c
Signature · 1 line
1.7.9.5
PATCH v3 1/15 drm: add MIPI DSI encoder and connector types
From: Shobhit Kumar <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/drm_crtc.c | 2 ++ include/uapi/drm/drm_mode.h | 2 ++ 2 files changed, 4 insertions(+)
drivers/gpu/drm/drm_crtc.c +2 -0
@@ -202,6 +202,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = { DRM_MODE_CONNECTOR_TV, "TV" }, { DRM_MODE_CONNECTOR_eDP, "eDP" }, { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" }, + { DRM_MODE_CONNECTOR_DSI, "DSI" }, }; static const struct drm_prop_enum_list drm_encoder_enum_list[] =
@@ -211,6 +212,7 @@ static const struct drm_prop_enum_list drm_encoder_enum_list[] = { DRM_MODE_ENCODER_LVDS, "LVDS" }, { DRM_MODE_ENCODER_TVDAC, "TV" }, { DRM_MODE_ENCODER_VIRTUAL, "Virtual" }, + { DRM_MODE_ENCODER_DSI, "DSI" }, };void drm_connector_ida_init (void )
include/uapi/drm/drm_mode.h +2 -0
@@ -165,6 +165,7 @@ struct drm_mode_get_plane_res {#define DRM_MODE_ENCODER_LVDS 3#define DRM_MODE_ENCODER_TVDAC 4#define DRM_MODE_ENCODER_VIRTUAL 5 +#define DRM_MODE_ENCODER_DSI 6struct drm_mode_get_encoder {__u32 encoder_id;
@@ -203,6 +204,7 @@ struct drm_mode_get_encoder {#define DRM_MODE_CONNECTOR_TV 13#define DRM_MODE_CONNECTOR_eDP 14#define DRM_MODE_CONNECTOR_VIRTUAL 15 +#define DRM_MODE_CONNECTOR_DSI 16struct drm_mode_get_connector {
Signature · 1 line
1.7.9.5
PATCH v3 2/15 drm/i915: add more VLV IOSF sideband ports accessors
In reply to Jani NikulaFor GPIO NC, CCK, CCU, and GPS CORE.
Signed-off-by Jani Nikula <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
--- drivers/gpu/drm/i915/i915_drv.h | 8 +++++ drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_sideband.c | 56 +++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+)
drivers/gpu/drm/i915/i915_drv.h +8 -0
@@ -2240,6 +2240,14 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)u32 vlv_punit_read (struct drm_i915_private *dev_priv,u8 addr);void vlv_punit_write (struct drm_i915_private *dev_priv,u8 addr,u32 val);u32 vlv_nc_read (struct drm_i915_private *dev_priv,u8 addr); +u32 vlv_gpio_nc_read (struct drm_i915_private *dev_priv,u32 reg); +void vlv_gpio_nc_write (struct drm_i915_private *dev_priv,u32 reg,u32 val); +u32 vlv_cck_read (struct drm_i915_private *dev_priv,u32 reg); +void vlv_cck_write (struct drm_i915_private *dev_priv,u32 reg,u32 val); +u32 vlv_ccu_read (struct drm_i915_private *dev_priv,u32 reg); +void vlv_ccu_write (struct drm_i915_private *dev_priv,u32 reg,u32 val); +u32 vlv_gps_core_read (struct drm_i915_private *dev_priv,u32 reg); +void vlv_gps_core_write (struct drm_i915_private *dev_priv,u32 reg,u32 val);u32 vlv_dpio_read (struct drm_i915_private *dev_priv,int reg);void vlv_dpio_write (struct drm_i915_private *dev_priv,int reg,u32 val); u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
drivers/gpu/drm/i915/i915_reg.h +4 -0
@@ -360,6 +360,10 @@#define IOSF_PORT_PUNIT 0x4#define IOSF_PORT_NC 0x11#define IOSF_PORT_DPIO 0x12 +#define IOSF_PORT_GPIO_NC 0x13 +#define IOSF_PORT_CCK 0x14 +#define IOSF_PORT_CCU 0xA9 +#define IOSF_PORT_GPS_CORE 0x48#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
drivers/gpu/drm/i915/intel_sideband.c +56 -0
62 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v3 3/15 drm/i915: add VLV pipeconf bit definition for DSI PLL lock
In reply to Jani Nikulav2: Add comment this is pipe A only (Ville)
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/i915_reg.h | 1 + 1 file changed, 1 insertion(+)
drivers/gpu/drm/i915/i915_reg.h +1 -0
@@ -2983,6 +2983,7 @@#define PIPECONF_DISABLE 0#define PIPECONF_DOUBLE_WIDE (1<<30)#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPECONF_DSI_PLL_LOCKED (1<<29)/* vlv & pipe A only */ #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)#define PIPECONF_SINGLE_WIDE 0#define PIPECONF_PIPE_UNLOCKED 0
Signature · 1 line
1.7.9.5
PATCH v3 4/15 drm/i915: add MIPI DSI register definitions
In reply to Jani NikulaAdd definitions for VLV MIPI DSI registers.
v2: Small fixes per Ville's review comments.
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/i915_reg.h | 410 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 410 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +410 -0
@@ -5115,4 +5115,414 @@#define PIPE_CSC_POSTOFF_ME (pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)#define PIPE_CSC_POSTOFF_LO (pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) +/* VLV MIPI registers */ + +#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) +#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) +#define MIPI_PORT_CTRL (pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL) +#define DPI_ENABLE (1 << 31)/* A + B */ +#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 +#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) +#define DUAL_LINK_MODE_MASK (1 << 26) +#define DUAL_LINK_MODE_FRONT_BACK (0 << 26) +#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) +#define DITHERING_ENABLE (1 << 25)/* A + B */ +#define FLOPPED_HSTX (1 << 23) +#define DE_INVERT (1 << 19)/* XXX */ +#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 +#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) +#define AFE_LATCHOUT (1 << 17) +#define LP_OUTPUT_HOLD (1 << 16) +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 +#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) +#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 +#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) +#define CSB_SHIFT 9 +#define CSB_MASK (3 << 9) +#define CSB_20MHZ (0 << 9) +#define CSB_10MHZ (1 << 9) +#define CSB_40MHZ (2 << 9) +#define BANDGAP_MASK (1 << 8) +#define BANDGAP_PNW_CIRCUIT (0 << 8) +#define BANDGAP_LNC_CIRCUIT (1 << 8) +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 +#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) +#define TEARING_EFFECT_DELAY (1 << 4)/* A + B */ +#define TEARING_EFFECT_SHIFT 2/* A + B */ +#define TEARING_EFFECT_MASK (3 << 2) +#define TEARING_EFFECT_OFF (0 << 2) +#define TEARING_EFFECT_DSI (1 << 2) +#define TEARING_EFFECT_GPIO (2 << 2) +#define LANE_CONFIGURATION_SHIFT 0 +#define LANE_CONFIGURATION_MASK (3 << 0) +#define LANE_CONFIGURATION_4LANE (0 << 0) +#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) +#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) + +#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) +#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) +#define MIPI_TEARING_CTRL (pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) +#define TEARING_EFFECT_DELAY_SHIFT 0 +#define TEARING_EFFECT_DELAY_MASK (0xffff << 0) + +/* XXX: all bits reserved */ +#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) + +/* MIPI DSI Controller and D-PHY registers */ + +#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000) +#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800) +#define MIPI_DEVICE_READY (pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY) +#define BUS_POSSESSION (1 << 3)/* set to give bus to receiver */ +#define ULPS_STATE_MASK (3 << 1) +#define ULPS_STATE_ENTER (2 << 1) +#define ULPS_STATE_EXIT (1 << 1) +#define ULPS_STATE_NORMAL_OPERATION (0 << 1) +#define DEVICE_READY (1 << 0) + +#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004) +#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804) +#define MIPI_INTR_STAT (pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT) +#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008) +#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808) +#define MIPI_INTR_EN (pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN) +#define TEARING_EFFECT (1 << 31) +#define SPL_PKT_SENT_INTERRUPT (1 << 30) +#define GEN_READ_DATA_AVAIL (1 << 29) +#define LP_GENERIC_WR_FIFO_FULL (1 << 28) +#define HS_GENERIC_WR_FIFO_FULL (1 << 27) +#define RX_PROT_VIOLATION (1 << 26) +#define RX_INVALID_TX_LENGTH (1 << 25) +#define ACK_WITH_NO_ERROR (1 << 24) +#define TURN_AROUND_ACK_TIMEOUT (1 << 23) +#define LP_RX_TIMEOUT (1 << 22) +#define HS_TX_TIMEOUT (1 << 21) +#define DPI_FIFO_UNDERRUN (1 << 20) +#define LOW_CONTENTION (1 << 19) +#define HIGH_CONTENTION (1 << 18) +#define TXDSI_VC_ID_INVALID (1 << 17) +#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) +#define TXCHECKSUM_ERROR (1 << 15) +#define TXECC_MULTIBIT_ERROR (1 << 14) +#define TXECC_SINGLE_BIT_ERROR (1 << 13) +#define TXFALSE_CONTROL_ERROR (1 << 12) +#define RXDSI_VC_ID_INVALID (1 << 11) +#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) +#define RXCHECKSUM_ERROR (1 << 9) +#define RXECC_MULTIBIT_ERROR (1 << 8) +#define RXECC_SINGLE_BIT_ERROR (1 << 7) +#define RXFALSE_CONTROL_ERROR (1 << 6) +#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) +#define RX_LP_TX_SYNC_ERROR (1 << 4) +#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) +#define RXEOT_SYNC_ERROR (1 << 2) +#define RXSOT_SYNC_ERROR (1 << 1) +#define RXSOT_ERROR (1 << 0) + +#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c) +#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c) +#define MIPI_DSI_FUNC_PRG (pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG) +#define CMD_MODE_DATA_WIDTH_MASK (7 << 13) +#define CMD_MODE_NOT_SUPPORTED (0 << 13) +#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) +#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) +#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) +#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) +#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) +#define VID_MODE_FORMAT_MASK (0xf << 7) +#define VID_MODE_NOT_SUPPORTED (0 << 7) +#define VID_MODE_FORMAT_RGB565 (1 << 7) +#define VID_MODE_FORMAT_RGB666 (2 << 7) +#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) +#define VID_MODE_FORMAT_RGB888 (4 << 7) +#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 +#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) +#define VID_MODE_CHANNEL_NUMBER_SHIFT 3 +#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) +#define DATA_LANES_PRG_REG_SHIFT 0 +#define DATA_LANES_PRG_REG_MASK (7 << 0) + +#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010) +#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810) +#define MIPI_HS_TX_TIMEOUT (pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT) +#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff + +#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014) +#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814) +#define MIPI_LP_RX_TIMEOUT (pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT) +#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff + +#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018) +#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818) +#define MIPI_TURN_AROUND_TIMEOUT (pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) +#define TURN_AROUND_TIMEOUT_MASK 0x3f + +#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c) +#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c) +#define MIPI_DEVICE_RESET_TIMER (pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) +#define DEVICE_RESET_TIMER_MASK 0xffff + +#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020) +#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820) +#define MIPI_DPI_RESOLUTION (pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION) +#define VERTICAL_ADDRESS_SHIFT 16 +#define VERTICAL_ADDRESS_MASK (0xffff << 16) +#define HORIZONTAL_ADDRESS_SHIFT 0 +#define HORIZONTAL_ADDRESS_MASK 0xffff + +#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024) +#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824) +#define MIPI_DBI_FIFO_THROTTLE (pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) +#define DBI_FIFO_EMPTY_HALF (0 << 0) +#define DBI_FIFO_EMPTY_QUARTER (1 << 0) +#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) + +/* regs below are bits 15:0 */ +#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028) +#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828) +#define MIPI_HSYNC_PADDING_COUNT (pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) + +#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c) +#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c) +#define MIPI_HBP_COUNT (pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT) + +#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030) +#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830) +#define MIPI_HFP_COUNT (pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT) + +#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034) +#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834) +#define MIPI_HACTIVE_AREA_COUNT (pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) + +#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038) +#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838) +#define MIPI_VSYNC_PADDING_COUNT (pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) + +#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c) +#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c) +#define MIPI_VBP_COUNT (pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT) + +#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040) +#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840) +#define MIPI_VFP_COUNT (pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT) + +#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044) +#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844) +#define MIPI_HIGH_LOW_SWITCH_COUNT (pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) +/* regs above are bits 15:0 */ + +#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048) +#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848) +#define MIPI_DPI_CONTROL (pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL) +#define DPI_LP_MODE (1 << 6) +#define BACKLIGHT_OFF (1 << 5) +#define BACKLIGHT_ON (1 << 4) +#define COLOR_MODE_OFF (1 << 3) +#define COLOR_MODE_ON (1 << 2) +#define TURN_ON (1 << 1) +#define SHUTDOWN (1 << 0) + +#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c) +#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c) +#define MIPI_DPI_DATA (pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA) +#define COMMAND_BYTE_SHIFT 0 +#define COMMAND_BYTE_MASK (0x3f << 0) + +#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050) +#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850) +#define MIPI_INIT_COUNT (pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT) +#define MASTER_INIT_TIMER_SHIFT 0 +#define MASTER_INIT_TIMER_MASK (0xffff << 0) + +#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054) +#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854) +#define MIPI_MAX_RETURN_PKT_SIZE (pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) +#define MAX_RETURN_PKT_SIZE_SHIFT 0 +#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) + +#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058) +#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858) +#define MIPI_VIDEO_MODE_FORMAT (pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) +#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) +#define DISABLE_VIDEO_BTA (1 << 3) +#define IP_TG_CONFIG (1 << 2) +#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) +#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) +#define VIDEO_MODE_BURST (3 << 0) + +#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c) +#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c) +#define MIPI_EOT_DISABLE (pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE) +#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) +#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) +#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) +#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) +#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) +#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) +#define CLOCKSTOP (1 << 1) +#define EOT_DISABLE (1 << 0) + +#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060) +#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860) +#define MIPI_LP_BYTECLK (pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK) +#define LP_BYTECLK_SHIFT 0 +#define LP_BYTECLK_MASK (0xffff << 0) + +/* bits 31:0 */ +#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064) +#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864) +#define MIPI_LP_GEN_DATA (pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA) + +/* bits 31:0 */ +#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068) +#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868) +#define MIPI_HS_GEN_DATA (pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA) + +#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c) +#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c) +#define MIPI_LP_GEN_CTRL (pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL) +#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070) +#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870) +#define MIPI_HS_GEN_CTRL (pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL) +#define LONG_PACKET_WORD_COUNT_SHIFT 8 +#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) +#define SHORT_PACKET_PARAM_SHIFT 8 +#define SHORT_PACKET_PARAM_MASK (0xffff << 8) +#define VIRTUAL_CHANNEL_SHIFT 6 +#define VIRTUAL_CHANNEL_MASK (3 << 6) +#define DATA_TYPE_SHIFT 0 +#define DATA_TYPE_MASK (3f << 0) +/* data type values, see include/video/mipi_display.h */ + +#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074) +#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874) +#define MIPI_GEN_FIFO_STAT (pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT) +#define DPI_FIFO_EMPTY (1 << 28) +#define DBI_FIFO_EMPTY (1 << 27) +#define LP_CTRL_FIFO_EMPTY (1 << 26) +#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) +#define LP_CTRL_FIFO_FULL (1 << 24) +#define HS_CTRL_FIFO_EMPTY (1 << 18) +#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) +#define HS_CTRL_FIFO_FULL (1 << 16) +#define LP_DATA_FIFO_EMPTY (1 << 10) +#define LP_DATA_FIFO_HALF_EMPTY (1 << 9) +#define LP_DATA_FIFO_FULL (1 << 8) +#define HS_DATA_FIFO_EMPTY (1 << 2) +#define HS_DATA_FIFO_HALF_EMPTY (1 << 1) +#define HS_DATA_FIFO_FULL (1 << 0) + +#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078) +#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878) +#define MIPI_HS_LP_DBI_ENABLE (pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) +#define DBI_HS_LP_MODE_MASK (1 << 0) +#define DBI_LP_MODE (1 << 0) +#define DBI_HS_MODE (0 << 0) + +#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080) +#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880) +#define MIPI_DPHY_PARAM (pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM) +#define EXIT_ZERO_COUNT_SHIFT 24 +#define EXIT_ZERO_COUNT_MASK (0x3f << 24) +#define TRAIL_COUNT_SHIFT 16 +#define TRAIL_COUNT_MASK (0x1f << 16) +#define CLK_ZERO_COUNT_SHIFT 8 +#define CLK_ZERO_COUNT_MASK (0xff << 8) +#define PREPARE_COUNT_SHIFT 0 +#define PREPARE_COUNT_MASK (0x3f << 0) + +/* bits 31:0 */ +#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084) +#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884) +#define MIPI_DBI_BW_CTRL (pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL) + +#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088) +#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888) +#define MIPI_CLK_LANE_SWITCH_TIME_CNT (pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) +#define LP_HS_SSW_CNT_SHIFT 16 +#define LP_HS_SSW_CNT_MASK (0xffff << 16) +#define HS_LP_PWR_SW_CNT_SHIFT 0 +#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) + +#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c) +#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c) +#define MIPI_STOP_STATE_STALL (pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) +#define STOP_STATE_STALL_COUNTER_SHIFT 0 +#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) + +#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090) +#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890) +#define MIPI_INTR_STAT_REG_1 (pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) +#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094) +#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894) +#define MIPI_INTR_EN_REG_1 (pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1) +#define RX_CONTENTION_DETECTED (1 << 0) + +/* XXX: only pipe A ?!? */ +#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100) +#define DBI_TYPEC_ENABLE (1 << 31) +#define DBI_TYPEC_WIP (1 << 30) +#define DBI_TYPEC_OPTION_SHIFT 28 +#define DBI_TYPEC_OPTION_MASK (3 << 28) +#define DBI_TYPEC_FREQ_SHIFT 24 +#define DBI_TYPEC_FREQ_MASK (0xf << 24) +#define DBI_TYPEC_OVERRIDE (1 << 8) +#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 +#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) + + +/* MIPI adapter registers */ + +#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104) +#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904) +#define MIPI_CTRL (pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL) +#define ESCAPE_CLOCK_DIVIDER_SHIFT 5/* A only */ +#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) +#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) +#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) +#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) +#define READ_REQUEST_PRIORITY_SHIFT 3 +#define READ_REQUEST_PRIORITY_MASK (3 << 3) +#define READ_REQUEST_PRIORITY_LOW (0 << 3) +#define READ_REQUEST_PRIORITY_HIGH (3 << 3) +#define RGB_FLIP_TO_BGR (1 << 2) + +#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108) +#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908) +#define MIPI_DATA_ADDRESS (pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS) +#define DATA_MEM_ADDRESS_SHIFT 5 +#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) +#define DATA_VALID (1 << 0) + +#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c) +#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c) +#define MIPI_DATA_LENGTH (pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH) +#define DATA_LENGTH_SHIFT 0 +#define DATA_LENGTH_MASK (0xfffff << 0) + +#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110) +#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910) +#define MIPI_COMMAND_ADDRESS (pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) +#define COMMAND_MEM_ADDRESS_SHIFT 5 +#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) +#define AUTO_PWG_ENABLE (1 << 2) +#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) +#define COMMAND_VALID (1 << 0) + +#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114) +#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914) +#define MIPI_COMMAND_LENGTH (pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH) +#define COMMAND_LENGTH_SHIFT (n) (8 * (n))/* n: 0...3 */ +#define COMMAND_LENGTH_MASK (n) (0xff << (8 * (n))) + +#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118) +#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918) +#define MIPI_READ_DATA_RETURN (pipe, n) \ + (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n))/* n: 0...7 */ + +#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138) +#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938) +#define MIPI_READ_DATA_VALID (pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) +#define READ_DATA_VALID (n) (1 << (n)) +#endif /* _I915_REG_H_ */
Signature · 1 line
1.7.9.5
PATCH v3 5/15 drm/i915: add MIPI DSI output type and subtypes
In reply to Jani NikulaSigned-off-by Jani Nikula <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
--- drivers/gpu/drm/i915/intel_drv.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_drv.h +5 -1
@@ -93,13 +93,17 @@#define INTEL_OUTPUT_HDMI 6#define INTEL_OUTPUT_DISPLAYPORT 7#define INTEL_OUTPUT_EDP 8 -#define INTEL_OUTPUT_UNKNOWN 9 +#define INTEL_OUTPUT_DSI 9 +#define INTEL_OUTPUT_UNKNOWN 10#define INTEL_DVO_CHIP_NONE 0#define INTEL_DVO_CHIP_LVDS 1#define INTEL_DVO_CHIP_TMDS 2#define INTEL_DVO_CHIP_TVOUT 4 +#define INTEL_DSI_COMMAND_MODE 0 +#define INTEL_DSI_VIDEO_MODE 1 +struct intel_framebuffer {struct drm_framebuffer base;struct drm_i915_gem_object *obj;
Signature · 1 line
1.7.9.5
PATCH v3 6/15 drm/i915: add structs for MIPI DSI output
In reply to Jani NikulaThe sub-encoder model is copied from DVO.
v2: Add attached_connector to struct intel_dsi.
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/intel_dsi.h | 99 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi.h
drivers/gpu/drm/i915/intel_dsi.h new file +99 -0
@@ -0,0 +1,99 @@ +/* +* Copyright © 2013 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice (including the next +* paragraph) shall be included in all copies or substantial portions of the +* Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +*/ + +#ifndef _INTEL_DSI_H +#define _INTEL_DSI_H + +#include <drm/drmP.h> +#include <drm/drm_crtc.h> +#include "intel_drv.h" + +struct intel_dsi_device { +unsigned int panel_id; +const char *name; +int type; +const struct intel_dsi_dev_ops *dev_ops; +void *dev_priv; +}; + +struct intel_dsi_dev_ops { +bool (*init)(struct intel_dsi_device *dsi); + +/* This callback must be able to assume DSI commands can be sent */ +void (*enable)(struct intel_dsi_device *dsi); + +/* This callback must be able to assume DSI commands can be sent */ +void (*disable)(struct intel_dsi_device *dsi); + +int (*mode_valid)(struct intel_dsi_device *dsi, +struct drm_display_mode *mode); + +bool (*mode_fixup)(struct intel_dsi_device *dsi, +const struct drm_display_mode *mode, +struct drm_display_mode *adjusted_mode); + +void (*mode_set)(struct intel_dsi_device *dsi, +struct drm_display_mode *mode, +struct drm_display_mode *adjusted_mode); + +enum drm_connector_status (*detect)(struct intel_dsi_device *dsi); + +bool (*get_hw_state)(struct intel_dsi_device *dev); + +struct drm_display_mode *(*get_modes)(struct intel_dsi_device *dsi); + +void (*destroy) (struct intel_dsi_device *dsi); +}; + +struct intel_dsi { +struct intel_encoder base; + +struct intel_dsi_device dev; + +struct intel_connector *attached_connector; + +/* if true, use HS mode, otherwise LP */ +bool hs; + +/* virtual channel */ +int channel; + +/* number of DSI lanes */ +unsigned int lane_count; + +/* video mode pixel format for MIPI_DSI_FUNC_PRG register */ +u32 pixel_format; + +/* video mode format for MIPI_VIDEO_MODE_FORMAT register */ +u32 video_mode_format; + +/* eot for MIPI_EOT_DISABLE register */ +u32 eot_disable; +}; + +static inline struct intel_dsi *enc_to_intel_dsi (struct drm_encoder *encoder) +{ + return container_of(encoder, struct intel_dsi, base.base); +} + +#endif /* _INTEL_DSI_H */
Signature · 6 lines
1.7.9.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 7/15 drm/i915: add MIPI DSI command sending routines
In reply to Jani Nikulav2: Rebase due to register bit definition change.
v3: Mostly based on Ville's review comments.
- Use size_t for length all around.
- Reuse dsi_vc_send_short in dsi_vc_send_long.
- Remove stale/incorrect comments.
- Reverse special packet sent interrupt check.
- Use DSI controller regs for reading, not adapter.
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/intel_dsi_cmd.c | 427 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 +++++++++ 3 files changed, 537 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h
drivers/gpu/drm/i915/Makefile +1 -0
@@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_display.o \ intel_crt.o \ intel_lvds.o \ + intel_dsi_cmd.o \ intel_bios.o \ intel_ddi.o \ intel_dp.o \
drivers/gpu/drm/i915/intel_dsi_cmd.c new file +427 -0
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drivers/gpu/drm/i915/intel_dsi_cmd.h new file +109 -0
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Signature · 6 lines
1.7.9.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 8/15 drm/i915: add basic MIPI DSI output support
In reply to Jani NikulaThis does not include any panel specific sub-encoders yet.
v2: Fix fixed mode handling (Daniel)
v3: Mostly based on Ville's review comments.
- Fix MIPI_HS_TX_TIMEOUT.
- DPI_ENABLE only for video mode.
- Drop ULPS usage for now, use DEVICE_READY only.
- Set MIPI_INIT_COUNT based on txclkesc.
Signed-off-by Jani Nikula <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_dsi.c | 566 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 568 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi.c
drivers/gpu/drm/i915/Makefile +1 -0
@@ -21,6 +21,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_display.o \ intel_crt.o \ intel_lvds.o \ + intel_dsi.o \ intel_dsi_cmd.o \ intel_bios.o \ intel_ddi.o \
drivers/gpu/drm/i915/intel_drv.h +1 -0
@@ -525,6 +525,7 @@ extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj, struct intel_ring_buffer *ring);extern void intel_mark_idle (struct drm_device *dev);extern void intel_lvds_init (struct drm_device *dev); +extern bool intel_dsi_init (struct drm_device *dev);extern bool intel_is_dual_link_lvds (struct drm_device *dev);extern void intel_dp_init (struct drm_device *dev,int output_reg,enum port port);
drivers/gpu/drm/i915/intel_dsi.c new file +566 -0
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1.7.9.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v3 9/15 drm/i915: add VLV DSI PLL Calculations
In reply to Jani NikulaFrom: ymohanma <[email protected]>
v2:
- Grab dpio_lock mutex in vlv_enable_dsi_pll().
- Add and call vlv_disable_dsi_pll().
v3: Mostly based on Ville's review comments.
- Only pipe A has DSI PLL lock bit.
- Add more of CCK REG bit definitions for DSI PLL.
- Make tables static.
- Move clock gating out of the clock calculation functions.
- DSI PLL LDO power gating.
- Put alternative MNP from table calc behind #ifdef.
Signed-off-by ymohanma <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_reg.h | 32 ++++ drivers/gpu/drm/i915/intel_dsi.c | 7 + drivers/gpu/drm/i915/intel_dsi.h | 3 + drivers/gpu/drm/i915/intel_dsi_pll.c | 317 ++++++++++++++++++++++++++++++++++ 5 files changed, 360 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c
drivers/gpu/drm/i915/Makefile +1 -0
@@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_lvds.o \ intel_dsi.o \ intel_dsi_cmd.o \ + intel_dsi_pll.o \ intel_bios.o \ intel_ddi.o \ intel_dp.o \
drivers/gpu/drm/i915/i915_reg.h +32 -0
@@ -390,6 +390,38 @@#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +/* vlv2 north clock has */ +#define CCK_REG_DSI_PLL_FUSE 0x44 +#define CCK_REG_DSI_PLL_CONTROL 0x48 +#define DSI_PLL_VCO_EN (1 << 31) +#define DSI_PLL_LDO_GATE (1 << 30) +#define DSI_PLL_P1_POST_DIV_SHIFT 17 +#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) +#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) +#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) +#define DSI_PLL_MUX_MASK (3 << 9) +#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) +#define DSI_PLL_MUX_DSI0_CCK (1 << 10) +#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) +#define DSI_PLL_MUX_DSI1_CCK (1 << 9) +#define DSI_PLL_CLK_GATE_MASK (0xf << 5) +#define DSI_PLL_CKK_GATE_DSI0_DSIPLL (1 << 8) +#define DSI_PLL_CKK_GATE_DSI1_DSIPLL (1 << 7) +#define DSI_PLL_CKK_GATE_DSI0_CCK (1 << 6) +#define DSI_PLL_CKK_GATE_DSI1_CCK (1 << 5) +#define DSI_PLL_LOCK (1 << 0) +#define CCK_REG_DSI_PLL_DIVIDER 0x4c +#define DSI_PLL_LFSR (1 << 31) +#define DSI_PLL_FRACTION_EN (1 << 30) +#define DSI_PLL_FRAC_COUNTER_SHIFT 27 +#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) +#define DSI_PLL_USYNC_CNT_SHIFT 18 +#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) +#define DSI_PLL_N1_DIV_SHIFT 16 +#define DSI_PLL_N1_DIV_MASK (3 << 16) +#define DSI_PLL_M1_DIV_SHIFT 0 +#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) +/* * DPIO - a special bus for various display related registers to hide behind *
drivers/gpu/drm/i915/intel_dsi.c +7 -0
@@ -83,6 +83,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,static void intel_dsi_pre_pll_enable (struct intel_encoder *encoder) {DRM_DEBUG_KMS ("\n" ); + +vlv_enable_dsi_pll (encoder); }static void intel_dsi_pre_enable (struct intel_encoder *encoder)
@@ -167,6 +169,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)static void intel_dsi_post_disable (struct intel_encoder *encoder) {DRM_DEBUG_KMS ("\n" ); + +vlv_disable_dsi_pll (encoder); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -303,6 +307,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)DRM_DEBUG_KMS ("pipe %d\n" , pipe); +/* Update the DSI PLL */ +vlv_enable_dsi_pll (intel_encoder); +/* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ tmp =I915_READ (MIPI_CTRL (0 ));
drivers/gpu/drm/i915/intel_dsi.h +3 -0
@@ -96,4 +96,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) return container_of(encoder, struct intel_dsi, base.base); } +extern void vlv_enable_dsi_pll (struct intel_encoder *encoder); +extern void vlv_disable_dsi_pll (struct intel_encoder *encoder); +#endif /* _INTEL_DSI_H */
drivers/gpu/drm/i915/intel_dsi_pll.c new file +317 -0
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Signature · 6 lines
1.7.9.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v3 09/15] drm/i915: add VLV DSI PLL Calculations
Quoted 55 lines · Jani Nikula
From: ymohanma <[email protected]>
v2:
- Grabdpio_lockmutex invlv_enable_dsi_pll().
- Add and callvlv_disable_dsi_pll().v3: Mostly based on Ville's review comments.
- Only pipe A has DSI PLL lock bit.
- Add more of CCK REG bit definitions for DSI PLL.
- Make tables static.
- Move clock gating out of the clock calculation functions.
- DSI PLL LDO power gating.
- Put alternative MNP from table calc behind #ifdef.Signed-off-by ymohanma <[email protected]>Signed-off-by Shobhit Kumar <[email protected]>Signed-off-by Jani Nikula <[email protected]>--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_reg.h | 32 ++++ drivers/gpu/drm/i915/intel_dsi.c | 7 + drivers/gpu/drm/i915/intel_dsi.h | 3 + drivers/gpu/drm/i915/intel_dsi_pll.c | 317 ++++++++++++++++++++++++++++++++++ 5 files changed, 360 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.cdrivers/gpu/drm/i915/Makefile +1
-0@@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_lvds.o \ intel_dsi.o \ intel_dsi_cmd.o \ + intel_dsi_pll.o \ intel_bios.o \ intel_ddi.o \ intel_dp.o \drivers/gpu/drm/i915/i915_reg.h +9
-0@@ -390,6 +390,38 @@#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +/* vlv2 north clock has */ +#define CCK_REG_DSI_PLL_FUSE 0x44 +#define CCK_REG_DSI_PLL_CONTROL 0x48 +#define DSI_PLL_VCO_EN (1 << 31) +#define DSI_PLL_LDO_GATE (1 << 30) +#define DSI_PLL_P1_POST_DIV_SHIFT 17 +#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) +#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) +#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
drivers/gpu/drm/i915/i915_reg.h line 411
Quoted 10 lines
drivers/gpu/drm/i915/i915_reg.h +10
-0+#define DSI_PLL_MUX_MASK (3 << 9) +#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) +#define DSI_PLL_MUX_DSI0_CCK (1 << 10) +#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) +#define DSI_PLL_MUX_DSI1_CCK (1 << 9) +#define DSI_PLL_CLK_GATE_MASK (0xf << 5) +#define DSI_PLL_CKK_GATE_DSI0_DSIPLL (1 << 8) +#define DSI_PLL_CKK_GATE_DSI1_DSIPLL (1 << 7) +#define DSI_PLL_CKK_GATE_DSI0_CCK (1 << 6) +#define DSI_PLL_CKK_GATE_DSI1_CCK (1 << 5)
s/CKK/CLK ?
Otherwise seems good enough, so:
Reviewed-by Ville Syrjälä <[email protected]>
Quoted 385 lines
drivers/gpu/drm/i915/i915_reg.h +13
-0+#define DSI_PLL_LOCK (1 << 0) +#define CCK_REG_DSI_PLL_DIVIDER 0x4c +#define DSI_PLL_LFSR (1 << 31) +#define DSI_PLL_FRACTION_EN (1 << 30) +#define DSI_PLL_FRAC_COUNTER_SHIFT 27 +#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) +#define DSI_PLL_USYNC_CNT_SHIFT 18 +#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) +#define DSI_PLL_N1_DIV_SHIFT 16 +#define DSI_PLL_N1_DIV_MASK (3 << 16) +#define DSI_PLL_M1_DIV_SHIFT 0 +#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) +/* * DPIO - a special bus for various display related registers to hide behind * drivers/gpu/drm/i915/intel_dsi.c +7
-0@@ -83,6 +83,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,static void intel_dsi_pre_pll_enable (struct intel_encoder *encoder) {DRM_DEBUG_KMS ("\n" ); + +vlv_enable_dsi_pll (encoder); }static void intel_dsi_pre_enable (struct intel_encoder *encoder)@@ -167,6 +169,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)static void intel_dsi_post_disable (struct intel_encoder *encoder) {DRM_DEBUG_KMS ("\n" ); + +vlv_disable_dsi_pll (encoder); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,@@ -303,6 +307,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)DRM_DEBUG_KMS ("pipe %d\n" , pipe); +/* Update the DSI PLL */ +vlv_enable_dsi_pll (intel_encoder); +/* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ tmp =I915_READ (MIPI_CTRL (0 ));drivers/gpu/drm/i915/intel_dsi.h +3
-0@@ -96,4 +96,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) return container_of(encoder, struct intel_dsi, base.base); } +extern void vlv_enable_dsi_pll (struct intel_encoder *encoder); +extern void vlv_disable_dsi_pll (struct intel_encoder *encoder); +#endif /* _INTEL_DSI_H */ drivers/gpu/drm/i915/intel_dsi_pll.c new file +317
-0@@ -0,0 +1,317 @@ +/* +* Copyright © 2013 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice (including the next +* paragraph) shall be included in all copies or substantial portions of the +* Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +* +* Authors: +* Shobhit Kumar <[email protected]> +* Yogesh Mohan Marimuthu <[email protected]> +*/ + +#include <linux/kernel.h> +#include "intel_drv.h" +#include "i915_drv.h" +#include "intel_dsi.h" + +#define DSI_HSS_PACKET_SIZE 4 +#define DSI_HSE_PACKET_SIZE 4 +#define DSI_HSA_PACKET_EXTRA_SIZE 6 +#define DSI_HBP_PACKET_EXTRA_SIZE 6 +#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 +#define DSI_HFP_PACKET_EXTRA_SIZE 6 +#define DSI_EOTP_PACKET_SIZE 4 + +struct dsi_mnp { +u32 dsi_pll_ctrl; +u32 dsi_pll_div; +}; + +static const u32 lfsr_converts[] = { +426 ,469 ,234 ,373 ,442 ,221 ,110 ,311 ,411 ,/* 62 - 70 */ +461 ,486 ,243 ,377 ,188 ,350 ,175 ,343 ,427 ,213 ,/* 71 - 80 */ +106 ,53 ,282 ,397 ,354 ,227 ,113 ,56 ,284 ,142 ,/* 81 - 90 */ +71 ,35 /* 91 - 92 */ +}; + +static u32 dsi_rr_formula (struct drm_display_mode *mode, +int pixel_format,int video_mode_format, +int lane_count,bool eotp) +{ +u32 bpp; +u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; +u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; +u32 bytes_per_line, bytes_per_frame; +u32 num_frames; +u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; +u32 dsi_bit_clock_hz; +u32 dsi_clk; + +switch (pixel_format) { +default : +case VID_MODE_FORMAT_RGB888 : +case VID_MODE_FORMAT_RGB666_LOOSE : + bpp =24 ; +break ; +case VID_MODE_FORMAT_RGB666 : + bpp =18 ; +break ; +case VID_MODE_FORMAT_RGB565 : + bpp =16 ; +break ; + } + + hactive = mode->hdisplay; + vactive = mode->vdisplay; + hfp = mode->hsync_start - mode->hdisplay; + hsync = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsync = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + hsync_bytes =DIV_ROUND_UP (hsync * bpp,8 ); + hbp_bytes =DIV_ROUND_UP (hbp * bpp,8 ); + hactive_bytes =DIV_ROUND_UP (hactive * bpp,8 ); + hfp_bytes =DIV_ROUND_UP (hfp * bpp,8 ); + + bytes_per_line =DSI_HSS_PACKET_SIZE + hsync_bytes + +DSI_HSA_PACKET_EXTRA_SIZE +DSI_HSE_PACKET_SIZE + + hbp_bytes +DSI_HBP_PACKET_EXTRA_SIZE + + hactive_bytes +DSI_HACTIVE_PACKET_EXTRA_SIZE + + hfp_bytes +DSI_HFP_PACKET_EXTRA_SIZE ; + +/* +* XXX: Need to accurately calculate LP to HS transition timeout and add +* it to bytes_per_line/bytes_per_frame. +*/ + +if (eotp && video_mode_format ==VIDEO_MODE_BURST ) + bytes_per_line +=DSI_EOTP_PACKET_SIZE ; + + bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + + vactive * bytes_per_line + vfp * bytes_per_line; + +if (eotp && + (video_mode_format ==VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || + video_mode_format ==VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS )) + bytes_per_frame +=DSI_EOTP_PACKET_SIZE ; + + num_frames =drm_mode_vrefresh (mode); + bytes_per_x_frames = num_frames * bytes_per_frame; + + bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; + +/* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ + dsi_bit_clock_hz = bytes_per_x_frames_x_lanes *8 ; + dsi_clk = dsi_bit_clock_hz / (1000 *1000 ); + +if (eotp && video_mode_format ==VIDEO_MODE_BURST ) + dsi_clk *=2 ; + +return dsi_clk; +} + +#ifdef MNP_FROM_TABLE + +struct dsi_clock_table { +u32 freq; +u8 m; +u8 p; +}; + +static const struct dsi_clock_table dsi_clk_tbl[] = { + {300 ,72 ,6 }, {313 ,75 ,6 }, {323 ,78 ,6 }, {333 ,80 ,6 }, + {343 ,82 ,6 }, {353 ,85 ,6 }, {363 ,87 ,6 }, {373 ,90 ,6 }, + {383 ,92 ,6 }, {390 ,78 ,5 }, {393 ,79 ,5 }, {400 ,80 ,5 }, + {401 ,80 ,5 }, {402 ,80 ,5 }, {403 ,81 ,5 }, {404 ,81 ,5 }, + {405 ,81 ,5 }, {406 ,81 ,5 }, {407 ,81 ,5 }, {408 ,82 ,5 }, + {409 ,82 ,5 }, {410 ,82 ,5 }, {411 ,82 ,5 }, {412 ,82 ,5 }, + {413 ,83 ,5 }, {414 ,83 ,5 }, {415 ,83 ,5 }, {416 ,83 ,5 }, + {417 ,83 ,5 }, {418 ,84 ,5 }, {419 ,84 ,5 }, {420 ,84 ,5 }, + {430 ,86 ,5 }, {440 ,88 ,5 }, {450 ,90 ,5 }, {460 ,92 ,5 }, + {470 ,75 ,4 }, {480 ,77 ,4 }, {490 ,78 ,4 }, {500 ,80 ,4 }, + {510 ,82 ,4 }, {520 ,83 ,4 }, {530 ,85 ,4 }, {540 ,86 ,4 }, + {550 ,88 ,4 }, {560 ,90 ,4 }, {570 ,91 ,4 }, {580 ,70 ,3 }, + {590 ,71 ,3 }, {600 ,72 ,3 }, {610 ,73 ,3 }, {620 ,74 ,3 }, + {630 ,76 ,3 }, {640 ,77 ,3 }, {650 ,78 ,3 }, {660 ,79 ,3 }, + {670 ,80 ,3 }, {680 ,82 ,3 }, {690 ,83 ,3 }, {700 ,84 ,3 }, + {710 ,85 ,3 }, {720 ,86 ,3 }, {730 ,88 ,3 }, {740 ,89 ,3 }, + {750 ,90 ,3 }, {760 ,91 ,3 }, {770 ,92 ,3 }, {780 ,62 ,2 }, + {790 ,63 ,2 }, {800 ,64 ,2 }, {880 ,70 ,2 }, {900 ,72 ,2 }, + {1000 ,80 ,2 },/* dsi clock frequency in Mhz*/ +}; + +static int dsi_calc_mnp (u32 dsi_clk,struct dsi_mnp *dsi_mnp) +{ +unsigned int i; +u8 m; +u8 n; +u8 p; +u32 m_seed; + +if (dsi_clk <300 || dsi_clk >1000 ) +return -ECHRNG ; + +for (i =0 ; i <=ARRAY_SIZE (dsi_clk_tbl); i++) { +if (dsi_clk_tbl[i].freq > dsi_clk) +break ; + } + + m = dsi_clk_tbl[i].m; + p = dsi_clk_tbl[i].p; + m_seed = lfsr_converts[m -62 ]; + n =1 ; + dsi_mnp->dsi_pll_ctrl =1 << (DSI_PLL_P1_POST_DIV_SHIFT + p -2 ); + dsi_mnp->dsi_pll_div = (n -1 ) <<DSI_PLL_N1_DIV_SHIFT | + m_seed <<DSI_PLL_M1_DIV_SHIFT ; + +return 0 ; +} + +#else + +static int dsi_calc_mnp (u32 dsi_clk,struct dsi_mnp *dsi_mnp) +{ +u32 m, n, p; +u32 ref_clk; +u32 error; +u32 tmp_error; +u32 target_dsi_clk; +u32 calc_dsi_clk; +u32 calc_m; +u32 calc_p; +u32 m_seed; + +if (dsi_clk <300 || dsi_clk >1150 ) { +DRM_ERROR ("DSI CLK Out of Range\n" ); +return -ECHRNG ; + } + + ref_clk =25000 ; + target_dsi_clk = dsi_clk *1000 ; + error =0xFFFFFFFF ; + calc_m =0 ; + calc_p =0 ; + +for (m =62 ; m <=92 ; m++) { +for (p =2 ; p <=6 ; p++) { + + calc_dsi_clk = (m * ref_clk) / p; +if (calc_dsi_clk >= target_dsi_clk) { + tmp_error = calc_dsi_clk - target_dsi_clk; +if (tmp_error < error) { + error = tmp_error; + calc_m = m; + calc_p = p; + } + } + } + } + + m_seed = lfsr_converts[calc_m -62 ]; + n =1 ; + dsi_mnp->dsi_pll_ctrl =1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p -2 ); + dsi_mnp->dsi_pll_div = (n -1 ) <<DSI_PLL_N1_DIV_SHIFT | + m_seed <<DSI_PLL_M1_DIV_SHIFT ; + +return 0 ; +} + +#endif + +/* +* XXX: The muxing and gating is hard coded for now. Need to add support for +* sharing PLLs with two DSI outputs. +*/ +static void vlv_configure_dsi_pll (struct intel_encoder *encoder) +{ +struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; +struct intel_crtc *intel_crtc =to_intel_crtc (encoder->base.crtc); +struct drm_display_mode *mode = &intel_crtc->config.requested_mode; +struct intel_dsi *intel_dsi =enc_to_intel_dsi (&encoder->base); +int ret; +struct dsi_mnp dsi_mnp; +u32 dsi_clk; + + dsi_clk =dsi_rr_formula (mode, intel_dsi->pixel_format, + intel_dsi->video_mode_format, + intel_dsi->lane_count, !intel_dsi->eot_disable); + + ret =dsi_calc_mnp (dsi_clk, &dsi_mnp); +if (ret) { +DRM_DEBUG_KMS ("dsi_calc_mnp failed\n" ); +return ; + } + + dsi_mnp.dsi_pll_ctrl |=DSI_PLL_CKK_GATE_DSI0_DSIPLL ; + +DRM_DEBUG_KMS ("dsi pll div %08x, ctrl %08x\n" , + dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); + +vlv_cck_write (dev_priv,CCK_REG_DSI_PLL_CONTROL ,0 ); +vlv_cck_write (dev_priv,CCK_REG_DSI_PLL_DIVIDER , dsi_mnp.dsi_pll_div); +vlv_cck_write (dev_priv,CCK_REG_DSI_PLL_CONTROL , dsi_mnp.dsi_pll_ctrl); +} + +void vlv_enable_dsi_pll (struct intel_encoder *encoder) +{ +struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; +u32 tmp; + +DRM_DEBUG_KMS ("\n" ); + +mutex_lock (&dev_priv->dpio_lock); + +vlv_configure_dsi_pll (encoder); + +/* wait at least 0.5 us after ungating before enabling VCO */ +usleep_range (1 ,10 ); + + tmp =vlv_cck_read (dev_priv,CCK_REG_DSI_PLL_CONTROL ); + tmp |=DSI_PLL_VCO_EN ; +vlv_cck_write (dev_priv,CCK_REG_DSI_PLL_CONTROL , tmp); + +mutex_unlock (&dev_priv->dpio_lock); + +if (wait_for (I915_READ (PIPECONF (PIPE_A )) &PIPECONF_DSI_PLL_LOCKED ,20 )) { +DRM_ERROR ("DSI PLL lock failed\n" ); +return ; + } + +DRM_DEBUG_KMS ("DSI PLL locked\n" ); +} + +void vlv_disable_dsi_pll (struct intel_encoder *encoder) +{ +struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; +u32 tmp; + +DRM_DEBUG_KMS ("\n" ); + +mutex_lock (&dev_priv->dpio_lock); + + tmp =vlv_cck_read (dev_priv,CCK_REG_DSI_PLL_CONTROL ); + tmp &= ~DSI_PLL_VCO_EN ; + tmp |=DSI_PLL_LDO_GATE ; +vlv_cck_write (dev_priv,CCK_REG_DSI_PLL_CONTROL , tmp); + +mutex_unlock (&dev_priv->dpio_lock); +}Signature · 1 line
1.7.9.5
Signature · 2 lines
Ville Syrjälä Intel OTC
PATCH v3 9/15 drm/i915: add VLV DSI PLL Calculations
From: ymohanma <[email protected]>
v2:
- Grab dpio_lock mutex in vlv_enable_dsi_pll().
- Add and call vlv_disable_dsi_pll().
v3: Mostly based on Ville's review comments.
- Only pipe A has DSI PLL lock bit.
- Add more of CCK REG bit definitions for DSI PLL.
- Make tables static.
- Move clock gating out of the clock calculation functions.
- DSI PLL LDO power gating.
- Put alternative MNP from table calc behind #ifdef.
v4: s/CKK/CLK/ in the CCK REG bit definitions (Ville).
Signed-off-by ymohanma <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_reg.h | 32 ++++ drivers/gpu/drm/i915/intel_dsi.c | 7 + drivers/gpu/drm/i915/intel_dsi.h | 3 + drivers/gpu/drm/i915/intel_dsi_pll.c | 317 ++++++++++++++++++++++++++++++++++ 5 files changed, 360 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c
drivers/gpu/drm/i915/Makefile +1 -0
@@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_lvds.o \ intel_dsi.o \ intel_dsi_cmd.o \ + intel_dsi_pll.o \ intel_bios.o \ intel_ddi.o \ intel_dp.o \
drivers/gpu/drm/i915/i915_reg.h +32 -0
@@ -390,6 +390,38 @@#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +/* vlv2 north clock has */ +#define CCK_REG_DSI_PLL_FUSE 0x44 +#define CCK_REG_DSI_PLL_CONTROL 0x48 +#define DSI_PLL_VCO_EN (1 << 31) +#define DSI_PLL_LDO_GATE (1 << 30) +#define DSI_PLL_P1_POST_DIV_SHIFT 17 +#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) +#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) +#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) +#define DSI_PLL_MUX_MASK (3 << 9) +#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) +#define DSI_PLL_MUX_DSI0_CCK (1 << 10) +#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) +#define DSI_PLL_MUX_DSI1_CCK (1 << 9) +#define DSI_PLL_CLK_GATE_MASK (0xf << 5) +#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) +#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) +#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) +#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) +#define DSI_PLL_LOCK (1 << 0) +#define CCK_REG_DSI_PLL_DIVIDER 0x4c +#define DSI_PLL_LFSR (1 << 31) +#define DSI_PLL_FRACTION_EN (1 << 30) +#define DSI_PLL_FRAC_COUNTER_SHIFT 27 +#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) +#define DSI_PLL_USYNC_CNT_SHIFT 18 +#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) +#define DSI_PLL_N1_DIV_SHIFT 16 +#define DSI_PLL_N1_DIV_MASK (3 << 16) +#define DSI_PLL_M1_DIV_SHIFT 0 +#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) +/* * DPIO - a special bus for various display related registers to hide behind *
drivers/gpu/drm/i915/intel_dsi.c +7 -0
@@ -83,6 +83,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,static void intel_dsi_pre_pll_enable (struct intel_encoder *encoder) {DRM_DEBUG_KMS ("\n" ); + +vlv_enable_dsi_pll (encoder); }static void intel_dsi_pre_enable (struct intel_encoder *encoder)
@@ -167,6 +169,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)static void intel_dsi_post_disable (struct intel_encoder *encoder) {DRM_DEBUG_KMS ("\n" ); + +vlv_disable_dsi_pll (encoder); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -303,6 +307,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)DRM_DEBUG_KMS ("pipe %d\n" , pipe); +/* Update the DSI PLL */ +vlv_enable_dsi_pll (intel_encoder); +/* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ tmp =I915_READ (MIPI_CTRL (0 ));
drivers/gpu/drm/i915/intel_dsi.h +3 -0
@@ -96,4 +96,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) return container_of(encoder, struct intel_dsi, base.base); } +extern void vlv_enable_dsi_pll (struct intel_encoder *encoder); +extern void vlv_disable_dsi_pll (struct intel_encoder *encoder); +#endif /* _INTEL_DSI_H */
drivers/gpu/drm/i915/intel_dsi_pll.c new file +317 -0
317 lines not on this page · raw message
Signature · 6 lines
1.7.10.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v3 09/15] drm/i915: add VLV DSI PLL Calculations
In reply to Ville SyrjäläQuoted 11 lines · Ville Syrjälä
drivers/gpu/drm/i915/i915_reg.h line 411
Quoted 5 lines · Jani Nikula
drivers/gpu/drm/i915/i915_reg.h +5
-0+#define DSI_PLL_CLK_GATE_MASK (0xf << 5) +#define DSI_PLL_CKK_GATE_DSI0_DSIPLL (1 << 8) +#define DSI_PLL_CKK_GATE_DSI1_DSIPLL (1 << 7) +#define DSI_PLL_CKK_GATE_DSI0_CCK (1 << 6) +#define DSI_PLL_CKK_GATE_DSI1_CCK (1 << 5)s/CKK/CLK ?
Otherwise seems good enough, so:
Reviewed-by Ville Syrjälä <[email protected]>
I just sent the updated patch, but fumbled the in-reply-to. The new version is [1].
Jani.
[1] http://mid.gmane.org/5d3b656372d2f72e7ce536498f5fdd46bea1ac14.1377635967.git.jani.nikula@intel.com
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PATCH v3 10/15 drm/i915: fix PLL assertions for DSI PLL
In reply to Jani NikulaFor DSI, we need to be asserting DSI PLL, not DPLL.
This is a somewhat stopgap implementation. It's slightly ugly to have to pass the dsi parameter to intel_enable_pipe().
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/intel_display.c | 44 +++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 8 deletions(-)
drivers/gpu/drm/i915/intel_display.c +36 -8
@@ -929,6 +929,24 @@ void assert_pll(struct drm_i915_private *dev_priv, state_string(state), state_string(cur_state)); } +/* XXX: the dsi pll is shared between MIPI DSI ports */ +static void assert_dsi_pll (struct drm_i915_private *dev_priv,bool state) +{ +u32 val; +bool cur_state; + +mutex_lock (&dev_priv->dpio_lock); + val =vlv_cck_read (dev_priv,CCK_REG_DSI_PLL_CONTROL ); +mutex_unlock (&dev_priv->dpio_lock); + + cur_state = val &DSI_PLL_VCO_EN ; +WARN (cur_state != state, +"DSI PLL state assertion failure (expected %s, current %s)\n" , +state_string (state),state_string (cur_state)); +} +#define assert_dsi_pll_enabled (d) assert_dsi_pll(d, true) +#define assert_dsi_pll_disabled (d) assert_dsi_pll(d, false) +struct intel_shared_dpll *intel_crtc_to_shared_dpll (struct intel_crtc *crtc) {
@@ -1661,7 +1679,7 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)* returning. */ static void intel_enable_pipe (struct drm_i915_private *dev_priv,enum pipe pipe, -bool pch_port) +bool pch_port,bool dsi) {enum transcoder cpu_transcoder =intel_pipe_to_cpu_transcoder (dev_priv, pipe);
@@ -1683,7 +1701,10 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,* need the check. */ if (!HAS_PCH_SPLIT (dev_priv->dev)) -assert_pll_enabled (dev_priv, pipe); +if (dsi) +assert_dsi_pll_enabled (dev_priv); +else +assert_pll_enabled (dev_priv, pipe);else {if (pch_port) {/* if driving the PCH, we need FDI enabled */
@@ -3282,7 +3303,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)intel_crtc_load_lut (crtc);intel_enable_pipe (dev_priv, pipe, - intel_crtc->config.has_pch_encoder); + intel_crtc->config.has_pch_encoder, false);intel_enable_plane (dev_priv, plane, pipe);intel_enable_planes (crtc);intel_crtc_update_cursor (crtc, true);
@@ -3390,7 +3411,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)intel_ddi_enable_transcoder_func (crtc);intel_enable_pipe (dev_priv, pipe, - intel_crtc->config.has_pch_encoder); + intel_crtc->config.has_pch_encoder, false);intel_enable_plane (dev_priv, plane, pipe);intel_enable_planes (crtc);intel_crtc_update_cursor (crtc, true);
@@ -3648,6 +3669,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)struct intel_encoder *encoder;int pipe = intel_crtc->pipe;int plane = intel_crtc->plane; +bool is_dsi;WARN_ON (!crtc->enabled);
@@ -3661,6 +3683,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)if (encoder->pre_pll_enable) encoder->pre_pll_enable (encoder); + is_dsi =intel_pipe_has_type (crtc,INTEL_OUTPUT_DSI ); +vlv_enable_pll (intel_crtc);for_each_encoder_on_crtc (dev, crtc, encoder)
@@ -3671,7 +3695,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)intel_crtc_load_lut (crtc); -intel_enable_pipe (dev_priv, pipe, false); +intel_enable_pipe (dev_priv, pipe, false, is_dsi);intel_enable_plane (dev_priv, plane, pipe);intel_enable_planes (crtc);intel_crtc_update_cursor (crtc, true);
@@ -3709,7 +3733,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)intel_crtc_load_lut (crtc); -intel_enable_pipe (dev_priv, pipe, false); +intel_enable_pipe (dev_priv, pipe, false, false);intel_enable_plane (dev_priv, plane, pipe);intel_enable_planes (crtc);/* The fixup needs to happen before cursor is enabled */
@@ -6661,8 +6685,12 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)if (!crtc->enabled || !intel_crtc->active)return ; -if (!HAS_PCH_SPLIT (dev_priv->dev)) -assert_pll_enabled (dev_priv, pipe); +if (!HAS_PCH_SPLIT (dev_priv->dev)) { +if (intel_pipe_has_type (crtc,INTEL_OUTPUT_DSI )) +assert_dsi_pll_enabled (dev_priv); +else +assert_pll_enabled (dev_priv, pipe); + }/* use legacy palette for Ironlake */ if (HAS_PCH_SPLIT (dev))
Signature · 1 line
1.7.9.5
PATCH v3 11/15 drm/i915: don't enable DPLL for DSI
In reply to Jani NikulaDPLL is not needed for DSI
v2: Rebase due to added DSI PLL assertion patch.
Signed-off-by Jani Nikula <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
--- drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++-------------- 1 file changed, 30 insertions(+), 20 deletions(-)
drivers/gpu/drm/i915/intel_display.c +30 -20
@@ -3685,7 +3685,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) is_dsi =intel_pipe_has_type (crtc,INTEL_OUTPUT_DSI ); -vlv_enable_pll (intel_crtc); +if (!is_dsi) +vlv_enable_pll (intel_crtc);for_each_encoder_on_crtc (dev, crtc, encoder)if (encoder->pre_enable)
@@ -3800,7 +3801,8 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)if (encoder->post_disable) encoder->post_disable (encoder); -i9xx_disable_pll (dev_priv, pipe); +if (!intel_pipe_has_type (crtc,INTEL_OUTPUT_DSI )) +i9xx_disable_pll (dev_priv, pipe); intel_crtc->active = false;intel_update_fbc (dev);
@@ -4868,7 +4870,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,intel_clock_t clock, reduced_clock;u32 dspcntr;bool ok, has_reduced_clock = false; -bool is_lvds = false; +bool is_lvds = false, is_dsi = false;struct intel_encoder *encoder;const intel_limit_t *limit;int ret;
@@ -4878,6 +4880,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,case INTEL_OUTPUT_LVDS : is_lvds = true;break ; +case INTEL_OUTPUT_DSI : + is_dsi = true; +break ; } num_connectors++;
@@ -4885,24 +4890,27 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, refclk =i9xx_get_refclk (crtc, num_connectors); -/* -* Returns a set of divisors for the desired target clock with the given -* refclk, or FALSE. The returned values represent the clock equation: -* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. -*/ - limit =intel_limit (crtc, refclk); - ok = dev_priv->display.find_dpll (limit, crtc, - intel_crtc->config.port_clock, - refclk,NULL , &clock); -if (!ok && !intel_crtc->config.clock_set) { -DRM_ERROR ("Couldn't find PLL settings for mode!\n" ); -return -EINVAL ; +if (!is_dsi) { +/* +* Returns a set of divisors for the desired target clock with +* the given refclk, or FALSE. The returned values represent +* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + +* 2) / p1 / p2. +*/ + limit =intel_limit (crtc, refclk); + ok = dev_priv->display.find_dpll (limit, crtc, + intel_crtc->config.port_clock, + refclk,NULL , &clock); +if (!ok && !intel_crtc->config.clock_set) { +DRM_ERROR ("Couldn't find PLL settings for mode!\n" ); +return -EINVAL ; + } }/* Ensure that the cursor is valid for the new mode before changing... */ intel_crtc_update_cursor (crtc, true); -if (is_lvds && dev_priv->lvds_downclock_avail) { +if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {/* * Ensure we match the reduced clock's P to the target clock. * If the clocks don't match, we can't switch the display clock
@@ -4924,16 +4932,18 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, intel_crtc->config.dpll.p2 = clock.p2; } -if (IS_GEN2 (dev)) +if (IS_GEN2 (dev)) {i8xx_update_pll (intel_crtc, has_reduced_clock ? &reduced_clock :NULL , num_connectors); -else if (IS_VALLEYVIEW (dev)) -vlv_update_pll (intel_crtc); -else + }else if (IS_VALLEYVIEW (dev)) { +if (!is_dsi) +vlv_update_pll (intel_crtc); + }else {i9xx_update_pll (intel_crtc, has_reduced_clock ? &reduced_clock :NULL , num_connectors); + }/* Set up the display plane register */ dspcntr =DISPPLANE_GAMMA_ENABLE ;
Signature · 1 line
1.7.9.5
PATCH v3 12/15 drm/i915: Band Gap WA
In reply to Jani NikulaFrom: Shobhit Kumar <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
Signed-off-by ymohanma <[email protected]>
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/intel_dsi.c | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
drivers/gpu/drm/i915/intel_dsi.c +48 -0
@@ -37,6 +37,51 @@static const struct intel_dsi_device intel_dsi_devices[] = { }; + +static void vlv_cck_modify (struct drm_i915_private *dev_priv,u32 reg,u32 val, +u32 mask) +{ +u32 tmp =vlv_cck_read (dev_priv, reg); + tmp &= ~mask; + tmp |= val; +vlv_cck_write (dev_priv, reg, tmp); +} + +static void band_gap_wa (struct drm_i915_private *dev_priv) +{ +mutex_lock (&dev_priv->dpio_lock); + +/* Enable bandgap fix in GOP driver */ +vlv_cck_modify (dev_priv,0x6D ,0x00010000 ,0x00030000 ); +msleep (20 ); +vlv_cck_modify (dev_priv,0x6E ,0x00010000 ,0x00030000 ); +msleep (20 ); +vlv_cck_modify (dev_priv,0x6F ,0x00010000 ,0x00030000 ); +msleep (20 ); +vlv_cck_modify (dev_priv,0x00 ,0x00008000 ,0x00008000 ); +msleep (20 ); +vlv_cck_modify (dev_priv,0x00 ,0x00000000 ,0x00008000 ); +msleep (20 ); + +/* Turn Display Trunk on */ +vlv_cck_modify (dev_priv,0x6B ,0x00020000 ,0x00030000 ); +msleep (20 ); + +vlv_cck_modify (dev_priv,0x6C ,0x00020000 ,0x00030000 ); +msleep (20 ); + +vlv_cck_modify (dev_priv,0x6D ,0x00020000 ,0x00030000 ); +msleep (20 ); +vlv_cck_modify (dev_priv,0x6E ,0x00020000 ,0x00030000 ); +msleep (20 ); +vlv_cck_modify (dev_priv,0x6F ,0x00020000 ,0x00030000 ); + +mutex_unlock (&dev_priv->dpio_lock); + +/* Need huge delay, otherwise clock is not stable */ +msleep (100 ); +} +static struct intel_dsi *intel_attached_dsi (struct drm_connector *connector) { return container_of(intel_attached_encoder(connector),
@@ -310,6 +355,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)/* Update the DSI PLL */ vlv_enable_dsi_pll (intel_encoder); +/* XXX: Location of the call */ +band_gap_wa (dev_priv); +/* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ tmp =I915_READ (MIPI_CTRL (0 ));
Signature · 1 line
1.7.9.5
Re: [PATCH v3 12/15] drm/i915: Band Gap WA
drivers/gpu/drm/i915/intel_dsi.c line 55
Quoted 6 lines · Jani Nikula
drivers/gpu/drm/i915/intel_dsi.c +6
-0+static void band_gap_wa (struct drm_i915_private *dev_priv) +{ +mutex_lock (&dev_priv->dpio_lock); + +/* Enable bandgap fix in GOP driver */ +vlv_cck_modify (dev_priv,0x6D ,0x00010000 ,0x00030000 );
I hear that the new way of doing the band gap reset is through the flisdsi sideband interface (instead of CCK) to shave off non necessary delays.
Yogesh, should we upstream the flisdsi version of this patch instead?
Signature · 1 line
Damien
PATCH v3 13/15 drm/i915: Parse the MIPI related VBT Block and store relevant info
In reply to Jani NikulaFrom: Shobhit Kumar <[email protected]>
Initial parsing of the VBT MIPI block. For now, just store the panel id if found.
Signed-off-by Shobhit Kumar <[email protected]>
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/i915_drv.h | 5 +++++ drivers/gpu/drm/i915/intel_bios.c | 16 +++++++++++++++ drivers/gpu/drm/i915/intel_bios.h | 41 +++++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+)
drivers/gpu/drm/i915/i915_drv.h +5 -0
@@ -1064,6 +1064,11 @@ struct intel_vbt_data {int edp_bpp;struct edp_power_seq edp_pps; +/* MIPI DSI */ +struct { +u16 panel_id; + } dsi; +int crt_ddc_pin;int child_dev_num;
drivers/gpu/drm/i915/intel_bios.c +16 -0
@@ -569,6 +569,21 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) }static void +parse_mipi (struct drm_i915_private *dev_priv,struct bdb_header *bdb) +{ +struct bdb_mipi *mipi; + + mipi =find_section (bdb,BDB_MIPI ); +if (!mipi) { +DRM_DEBUG_KMS ("No MIPI BDB found" ); +return ; + } + +/* XXX: add more info */ + dev_priv->vbt.dsi.panel_id = mipi->panel_id; +} + +static void parse_device_mapping (struct drm_i915_private *dev_priv,struct bdb_header *bdb) {
@@ -745,6 +760,7 @@ intel_parse_bios(struct drm_device *dev)parse_device_mapping (dev_priv, bdb);parse_driver_features (dev_priv, bdb);parse_edp (dev_priv, bdb); +parse_mipi (dev_priv, bdb);if (bios)pci_unmap_rom (pdev, bios);
drivers/gpu/drm/i915/intel_bios.h +41 -0
51 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v3 14/15 drm/i915: initialize DSI output on VLV
In reply to Jani NikulaSigned-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/gpu/drm/i915/intel_display.c +2 -0
@@ -9559,6 +9559,8 @@ static void intel_setup_outputs(struct drm_device *dev)if (I915_READ (VLV_DISPLAY_BASE +DP_B ) &DP_DETECTED )intel_dp_init (dev,VLV_DISPLAY_BASE +DP_B ,PORT_B ); } + +intel_dsi_init (dev); }else if (SUPPORTS_DIGITAL_OUTPUTS (dev)) {bool found = false;
Signature · 1 line
1.7.9.5
PATCH v3 15/15 drm/i915: add AUO MIPI DSI display sub-encoder
In reply to Jani NikulaFrom: Shobhit Kumar <[email protected]>
Signed-off-by Shobhit Kumar <[email protected]>
Signed-off-by Jani Nikula <[email protected]>
--- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/auo_dsi_display.c | 182 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi.c | 5 + drivers/gpu/drm/i915/intel_dsi.h | 3 + 4 files changed, 191 insertions(+) create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c
drivers/gpu/drm/i915/Makefile +1 -0
@@ -42,6 +42,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_opregion.o \ intel_sideband.o \ intel_uncore.o \ + auo_dsi_display.o \ dvo_ch7xxx.o \ dvo_ch7017.o \ dvo_ivch.o \
drivers/gpu/drm/i915/auo_dsi_display.c new file +182 -0
182 lines not on this page · raw message
drivers/gpu/drm/i915/intel_dsi.c +5 -0
@@ -35,6 +35,11 @@/* the sub-encoders aka panel drivers */ static const struct intel_dsi_device intel_dsi_devices[] = { + { + .type =INTEL_DSI_VIDEO_MODE , + .name ="auo-dsi-vid-mode-display" , + .dev_ops = &auo_dsi_display_ops, + }, };
drivers/gpu/drm/i915/intel_dsi.h +3 -0
@@ -99,4 +99,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)extern void vlv_enable_dsi_pll (struct intel_encoder *encoder);extern void vlv_disable_dsi_pll (struct intel_encoder *encoder); +/* the panel drivers */ +extern struct intel_dsi_dev_ops auo_dsi_display_ops; +#endif /* _INTEL_DSI_H */
Signature · 6 lines
1.7.9.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 3 lines · Jani Nikula
Hi all, v3 of [1] addressing (most of) Ville's review comments.
I am not reposting patch 1/15 to dri-devel, as it's unchanged since [2].
Didn't really look at the AUO and VBT patches (15 and 13) since I have no specs for those. I commented earlier on the band gap patch (12) earlier, but since no one really knows anything more about it, I can't really review it properly. Patch 9 had a small typo which I pointed out.
For rest (patches 1-8, 10-11, 14):
Reviewed-by Ville Syrjälä <[email protected]>
Quoted 53 lines
BR,
Jani.[1] http://mid.gmane.org/[email protected]
[2] http://mid.gmane.org/[email protected]Jani Nikula (10):
drm/i915: add more VLV IOSF sideband ports accessors drm/i915: add VLV pipeconf bit definition for DSI PLL lock drm/i915: add MIPI DSI register definitions drm/i915: add MIPI DSI output type and subtypes drm/i915: add structs for MIPI DSI output drm/i915: add MIPI DSI command sending routines drm/i915: add basic MIPI DSI output support drm/i915: fix PLL assertions for DSI PLL drm/i915: don't enable DPLL for DSI
drm/i915: initialize DSI output on VLVShobhit Kumar (4):
drm: add MIPI DSI encoder and connector types
drm/i915: Band Gap WA
drm/i915: Parse the MIPI related VBT Block and store relevant info drm/i915: add AUO MIPI DSI display sub-encoderymohanma (1):
drm/i915: add VLV DSI PLL Calculationsdrivers/gpu/drm/drm_crtc.c | 2 + drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/auo_dsi_display.c | 182 ++++++++++ drivers/gpu/drm/i915/i915_drv.h | 13 + drivers/gpu/drm/i915/i915_reg.h | 447 +++++++++++++++++++++++ drivers/gpu/drm/i915/intel_bios.c | 16 + drivers/gpu/drm/i915/intel_bios.h | 41 +++ drivers/gpu/drm/i915/intel_display.c | 96 +++-- drivers/gpu/drm/i915/intel_drv.h | 7 +- drivers/gpu/drm/i915/intel_dsi.c | 626 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi.h | 105 ++++++ drivers/gpu/drm/i915/intel_dsi_cmd.c | 427 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 ++++++ drivers/gpu/drm/i915/intel_dsi_pll.c | 317 ++++++++++++++++ drivers/gpu/drm/i915/intel_sideband.c | 56 +++ include/uapi/drm/drm_mode.h | 2 + 16 files changed, 2421 insertions(+), 29 deletions(-) create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c create mode 100644 drivers/gpu/drm/i915/intel_dsi.c create mode 100644 drivers/gpu/drm/i915/intel_dsi.h create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.cSignature · 1 line
1.7.9.5
Signature · 2 lines
Ville Syrjälä Intel OTC