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DWC3 support for Amlogic Meson AXG and GXL SoCs

PATCH Superseded Martin Blumenstingl 3 participants 8 messages Feb 11, 2018 – Mar 8, 2018

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Device tree bindings USB Arm/Amlogic Meson SoC support DesignWare USB3 DRD IP driver
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Martin Blumenstingl

author reviewer
#0 lore raw

v2 cover DWC3 support for Amlogic Meson AXG and GXL SoCs

Amlogic Meson AXG and GXL SoCs can use the dwc3-of-simple with little modifications. These SoCs use:
- a gate clock for the USB components (DWC3, USB PHYs)
- a reset line which is shared across all USB components (DWC3, USB2 and USB3 PHYs, OTG detection logic inside the USB3 PHY registers)
- a reset pulse to trigger the reset
- depending on the SoC two or more PHYs (AXG: 1x USB2 and 1x USB3 PHY,
GXL: 2x USB2 and 1x USB3 PHY)

This extends the dwc3-of-simple so it supports (depending on the platform) shared and level resets. Additionally it adds new bindings for the Amlogic Meson AXG and GXL SoCs, along with the documentation (dt-bindings).

NOTE: for full support on Amlogic Meson GXL SoCs my other series called "initialize (multiple) PHYs for a HCD" (see [0] for v8 of that series) is required. However, there is no direct dependency on that series. Especially since Meson AXG doesn't need it (since it only has one USB2 and one USB3 PHY, which is already supported by the current dwc3 driver, unlike the 2x USB2 and 1x USB3 PHYs on Meson GXL).
So I believe that this series can still be merged, even if the other patchset is not ready yet.

changes since v1 at [1]:
- use of_device_is_compatible() instead of struct dwc3_of_simple_params as requested by Felipe Balbi (affects PATCH #2 and #3)
- added Rob's Acked-by to the dt-bindings patch
- added Yixun Lan's Tested-by to the whole series as he tested this successfully (along with other patches) on the Amlogic Meson AXG SoC

[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006274.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006286.html

Martin Blumenstingl (3):
dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
usb: dwc3: of-simple: add support for shared and pulsed reset lines
usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG
SoCs

 .../devicetree/bindings/usb/amlogic,dwc3.txt       | 42 ++++++++++++++++++++++
 drivers/usb/dwc3/dwc3-of-simple.c                  | 31 ++++++++++++----
 2 files changed, 67 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
Signature · 1 line
2.16.1
author reviewer
#1 lore raw

PATCH v2 1/3 dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX

Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB controller. This requires a clock to be enabled and a reset line to be pulsed to get the hardware into a known state.
Add the documentation for this IP block, similar to "qcom,dwc3.txt".

Signed-off-by Martin Blumenstingl <[email protected]>
Reviewed-by Rob Herring <[email protected]>
Tested-by Yixun Lan <[email protected]>
---
 .../devicetree/bindings/usb/amlogic,dwc3.txt       | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
Documentation/devicetree/bindings/usb/amlogic,dwc3.txt new file +42 -0
new file mode 100644
index 000000000000..9a8b631904fd
@@ -0,0 +1,42 @@
+Amlogic Meson GX DWC3 USB SoC controller
+
+Required properties:
+- compatible:	depending on the SoC this should contain one of:
+			* amlogic,meson-axg-dwc3
+			* amlogic,meson-gxl-dwc3
+- clocks:	a handle for the "USB general" clock
+- clock-names:	must be "usb_general"
+- resets:	a handle for the shared "USB OTG" reset line
+- reset-names:	must be "usb_otg"
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+PHY documentation is provided in the following places:
+- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
+- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
+
+Example device nodes:
+		usb0: usb at ff500000 {
+			compatible = "amlogic,meson-axg-dwc3";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&clkc CLKID_USB>;
+			clock-names = "usb_general";
+			resets = <&reset RESET_USB_OTG>;
+			reset-names = "usb_otg";
+
+			dwc3: dwc3 at ff500000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0xff500000 0x0 0x100000>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				maximum-speed = "high-speed";
+				snps,dis_u2_susphy_quirk;
+				phys = <&usb3_phy>, <&usb2_phy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
Signature · 1 line
2.16.1
author reviewer
#2 lore raw

PATCH v2 2/3 usb: dwc3: of-simple: add support for shared and pulsed reset lines

In reply to Martin Blumenstingl

Some SoCs (such as Amlogic Meson GXL for example) share the reset line with other components (in case of the Meson GXL example there's a shared reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller). Additionally SoC implementations may prefer a reset pulse over level resets.

For now this falls back to the old defaults, which are:
- reset lines are exclusive
- level resets are being used

Signed-off-by Martin Blumenstingl <[email protected]>
Tested-by Yixun Lan <[email protected]>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)
drivers/usb/dwc3/dwc3-of-simple.c +17 -6
index 7ae0eefc7cc7..d2e4928c8d62 100644
@@ -27,6 +27,7 @@ struct dwc3_of_simple {
 	struct clk		**clks;
 	int			num_clocks;
 	struct reset_control	*resets;
+	bool			pulse_resets;
 };
 
 static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)

@@ -83,6 +84,7 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 
 	int			ret;
 	int			i;
+	bool			shared_resets = false;
 
 	simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
 	if (!simple)

@@ -91,16 +93,22 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, simple);
 	simple->dev = dev;
 
-	simple->resets = of_reset_control_array_get_optional_exclusive(np);
+	simple->resets = of_reset_control_array_get(np, shared_resets, true);
 	if (IS_ERR(simple->resets)) {
 		ret = PTR_ERR(simple->resets);
 		dev_err(dev, "failed to get device resets, err=%d\n", ret);
 		return ret;
 	}
 
-	ret = reset_control_deassert(simple->resets);
-	if (ret)
-		goto err_resetc_put;
+	if (simple->pulse_resets) {
+		ret = reset_control_reset(simple->resets);
+		if (ret)
+			goto err_resetc_put;
+	} else {
+		ret = reset_control_deassert(simple->resets);
+		if (ret)
+			goto err_resetc_put;
+	}
 
 	ret = dwc3_of_simple_clk_init(simple, of_count_phandle_with_args(np,
 						"clocks", "#clock-cells"));

@@ -124,7 +132,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 	return 0;
 
 err_resetc_assert:
-	reset_control_assert(simple->resets);
+	if (!simple->pulse_resets)
+		reset_control_assert(simple->resets);
 
 err_resetc_put:
 	reset_control_put(simple->resets);

@@ -144,7 +153,9 @@ static int dwc3_of_simple_remove(struct platform_device *pdev)
 		clk_put(simple->clks[i]);
 	}
 
-	reset_control_assert(simple->resets);
+	if (!simple->pulse_resets)
+		reset_control_assert(simple->resets);
+
 	reset_control_put(simple->resets);
 
 	pm_runtime_put_sync(dev);
Signature · 1 line
2.16.1
author reviewer
#3 lore raw

PATCH v2 3/3 usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG SoCs

In reply to Martin Blumenstingl

Amlogic Meson GXL and AXG SoCs come with a (host-only) dwc3 USB controller. To use this controller a clock has to be enabled and a reset line has to be pulsed.
Enabling the clock works identical to other SoCs. However, the reset line has to be pulsed (using reset_control_reset) instead of using a level reset (reset_control_{assert,deassert}).

Signed-off-by Martin Blumenstingl <[email protected]>
Tested-by Yixun Lan <[email protected]>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 8 ++++++++
 1 file changed, 8 insertions(+)
drivers/usb/dwc3/dwc3-of-simple.c +8 -0
index d2e4928c8d62..66cdc79017cf 100644
@@ -93,6 +93,12 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, simple);
 	simple->dev = dev;
 
+	if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
+	    of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) {
+		shared_resets = true;
+		simple->pulse_resets = true;
+	}
+
 	simple->resets = of_reset_control_array_get(np, shared_resets, true);
 	if (IS_ERR(simple->resets)) {
 		ret = PTR_ERR(simple->resets);

@@ -206,6 +212,8 @@ static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "xlnx,zynqmp-dwc3" },
 	{ .compatible = "cavium,octeon-7130-usb-uctl" },
 	{ .compatible = "sprd,sc9860-dwc3" },
+	{ .compatible = "amlogic,meson-axg-dwc3" },
+	{ .compatible = "amlogic,meson-gxl-dwc3" },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
Signature · 1 line
2.16.1
author reviewer
#4 lore raw

v2 cover DWC3 support for Amlogic Meson AXG and GXL SoCs

In reply to Martin Blumenstingl

Hello Felipe,

Quoted 32 lines · Martin Blumenstingl

Amlogic Meson AXG and GXL SoCs can use the dwc3-of-simple with little modifications. These SoCs use:
- a gate clock for the USB components (DWC3, USB PHYs)
- a reset line which is shared across all USB components (DWC3, USB2 and USB3 PHYs, OTG detection logic inside the USB3 PHY registers)
- a reset pulse to trigger the reset
- depending on the SoC two or more PHYs (AXG: 1x USB2 and 1x USB3 PHY,
GXL: 2x USB2 and 1x USB3 PHY)

This extends the dwc3-of-simple so it supports (depending on the platform) shared and level resets. Additionally it adds new bindings for the Amlogic Meson AXG and GXL SoCs, along with the documentation (dt-bindings).

NOTE: for full support on Amlogic Meson GXL SoCs my other series called "initialize (multiple) PHYs for a HCD" (see [0] for v8 of that series) is required. However, there is no direct dependency on that series. Especially since Meson AXG doesn't need it (since it only has one USB2 and one USB3 PHY, which is already supported by the current dwc3 driver, unlike the 2x USB2 and 1x USB3 PHYs on Meson GXL).
So I believe that this series can still be merged, even if the other patchset is not ready yet.

changes since v1 at [1]:
- use of_device_is_compatible() instead of struct dwc3_of_simple_params as requested by Felipe Balbi (affects PATCH #2 and #3)
- added Rob's Acked-by to the dt-bindings patch
- added Yixun Lan's Tested-by to the whole series as he tested this successfully (along with other patches) on the Amlogic Meson AXG SoC

Quoted 8 lines

[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006274.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006286.html

Martin Blumenstingl (3):
dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
usb: dwc3: of-simple: add support for shared and pulsed reset lines
usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG
SoCs

could you please let me know if you spotted any problems, code-style issues in v2 or whether you are waiting for feedback from another maintainer?
in case everything is fine: will you take this series through your tree?

Regards
Martin

author reviewer
#5 lore raw

v2 cover DWC3 support for Amlogic Meson AXG and GXL SoCs

Hello Felipe, Hello Greg,

Quoted 44 lines · Martin Blumenstingl

Hello Felipe,

Quoted 32 lines · Martin Blumenstingl

Amlogic Meson AXG and GXL SoCs can use the dwc3-of-simple with little modifications. These SoCs use:
- a gate clock for the USB components (DWC3, USB PHYs)
- a reset line which is shared across all USB components (DWC3, USB2 and USB3 PHYs, OTG detection logic inside the USB3 PHY registers)
- a reset pulse to trigger the reset
- depending on the SoC two or more PHYs (AXG: 1x USB2 and 1x USB3 PHY,
GXL: 2x USB2 and 1x USB3 PHY)

This extends the dwc3-of-simple so it supports (depending on the platform) shared and level resets. Additionally it adds new bindings for the Amlogic Meson AXG and GXL SoCs, along with the documentation (dt-bindings).

NOTE: for full support on Amlogic Meson GXL SoCs my other series called "initialize (multiple) PHYs for a HCD" (see [0] for v8 of that series) is required. However, there is no direct dependency on that series. Especially since Meson AXG doesn't need it (since it only has one USB2 and one USB3 PHY, which is already supported by the current dwc3 driver, unlike the 2x USB2 and 1x USB3 PHYs on Meson GXL).
So I believe that this series can still be merged, even if the other patchset is not ready yet.

changes since v1 at [1]:
- use of_device_is_compatible() instead of struct dwc3_of_simple_params as requested by Felipe Balbi (affects PATCH #2 and #3)
- added Rob's Acked-by to the dt-bindings patch
- added Yixun Lan's Tested-by to the whole series as he tested this successfully (along with other patches) on the Amlogic Meson AXG SoC

Quoted 8 lines

[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006274.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006286.html

Martin Blumenstingl (3):
dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
usb: dwc3: of-simple: add support for shared and pulsed reset lines
usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG
SoCs

Quoted 4 lines

could you please let me know if you spotted any problems, code-style issues in v2 or whether you are waiting for feedback from another maintainer?
in case everything is fine: will you take this series through your tree?

could you please let me know how this series is supposed to land in the next kernel release:
- Felipe, will you take it through your usb tree (which contains many other dwc2/dwc3 driver changes)?
- Greg, will you take it through your usb-next tree?
- should Kevin apply it to his linux-amlogic tree (drivers branch, which goes to the the arm-soc tree)?

as noted in the cover-letter Meson AXG support does not depend on any other series

Regards
Martin

#6 lore raw

v2 cover DWC3 support for Amlogic Meson AXG and GXL SoCs

Hi,

Quoted 5 lines · Martin Blumenstingl
Quoted 5 lines
Quoted 5 lines

Martin Blumenstingl (3):
dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
usb: dwc3: of-simple: add support for shared and pulsed reset lines
usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG
SoCs

Quoted 8 lines
Quoted 4 lines

could you please let me know if you spotted any problems, code-style issues in v2 or whether you are waiting for feedback from another maintainer?
in case everything is fine: will you take this series through your tree?

could you please let me know how this series is supposed to land in the next kernel release:
- Felipe, will you take it through your usb tree (which contains many other dwc2/dwc3 driver changes)?

it'll go through my tree. I'm about to merge it into my testing/next.

Signature · 8 lines
balbi
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#7 lore raw

v2 cover DWC3 support for Amlogic Meson AXG and GXL SoCs

In reply to Martin Blumenstingl
Quoted 41 lines · Martin Blumenstingl

Amlogic Meson AXG and GXL SoCs can use the dwc3-of-simple with little modifications. These SoCs use:
- a gate clock for the USB components (DWC3, USB PHYs)
- a reset line which is shared across all USB components (DWC3, USB2 and USB3 PHYs, OTG detection logic inside the USB3 PHY registers)
- a reset pulse to trigger the reset
- depending on the SoC two or more PHYs (AXG: 1x USB2 and 1x USB3 PHY,
GXL: 2x USB2 and 1x USB3 PHY)

This extends the dwc3-of-simple so it supports (depending on the platform) shared and level resets. Additionally it adds new bindings for the Amlogic Meson AXG and GXL SoCs, along with the documentation (dt-bindings).

NOTE: for full support on Amlogic Meson GXL SoCs my other series called "initialize (multiple) PHYs for a HCD" (see [0] for v8 of that series) is required. However, there is no direct dependency on that series. Especially since Meson AXG doesn't need it (since it only has one USB2 and one USB3 PHY, which is already supported by the current dwc3 driver, unlike the 2x USB2 and 1x USB3 PHYs on Meson GXL).
So I believe that this series can still be merged, even if the other patchset is not ready yet.

changes since v1 at [1]:
- use of_device_is_compatible() instead of struct dwc3_of_simple_params as requested by Felipe Balbi (affects PATCH #2 and #3)
- added Rob's Acked-by to the dt-bindings patch
- added Yixun Lan's Tested-by to the whole series as he tested this successfully (along with other patches) on the Amlogic Meson AXG SoC

[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006274.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006286.html

Martin Blumenstingl (3):
dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX
usb: dwc3: of-simple: add support for shared and pulsed reset lines
usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG
SoCs

Quoted 5 lines
 .../devicetree/bindings/usb/amlogic,dwc3.txt       | 42 ++++++++++++++++++++++
 drivers/usb/dwc3/dwc3-of-simple.c                  | 31 ++++++++++++----
 2 files changed, 67 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt

Hi Martin,

Successfully tested on Amlogic Q200 Reference Design board with a Meson GXM S912 SoC.

Other patchsets included :
- improvements and fixes for the phy-meson-gxl-usb2 driver https://lkml.kernel.org/r/20180128202245.25021-1-martin.blumenstingl at googlemail.com
- initialize (multiple) PHYs for a HCD V11 https://lkml.kernel.org/r/20180303214309.25643-1-martin.blumenstingl at googlemail.com
- Meson GXL USB3 PHY driver V4 https://lkml.kernel.org/r/20180303184700.21480-1-martin.blumenstingl at googlemail.com

Tested-by Neil Armstrong <[email protected]>

Thanks,
Neil