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KVM/arm64: Add NV support for ERET and PAuth

PATCH Applied Marc Zyngier 4 participants 24 messages Apr 19, 2024 – Apr 23, 2024

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Marc Zyngier

author maintainer
#0 lore raw

v4 cover KVM/arm64: Add NV support for ERET and PAuth

This is the fourth version of this series introducing ERET and PAuth support for NV guests, and now the base prefix for the NV support series.

Unless someone shouts, I intend to take this in for 6.10.

* From v3 [3]

- Check for NV support before checking for HCR_EL2.NV on vpcu exit

- Rebased on 6.9-rc1

* From v2 [2]

- Enforce that both Address and Generic authentication use the same algorithm

- Reduce PAuth trapping by eagerly setting the HCR_EL2.API/APK bits

- Collected RBs, with thanks

- Rebased on kvmarm-6.9

* From v1 [1]:

- Don't repaint the ISS_ERET* definitions, but provide reasonable helpers instead

- Dropped superfluous VNCR_EL2 definition

- Amended comments and creative spelling

[1] https://lore.kernel.org/r/[email protected]
[2] https://lore.kernel.org/r/[email protected]
[3] https://lore.kernel.org/r/[email protected]

Marc Zyngier (15):
KVM: arm64: Harden __ctxt_sys_reg() against out-of-range values
KVM: arm64: Add helpers for ESR_ELx_ERET_ISS_ERET*
KVM: arm64: Constraint PAuth support to consistent implementations
KVM: arm64: nv: Drop VCPU_HYP_CONTEXT flag
KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2
KVM: arm64: nv: Add trap forwarding for ERET and SMC
KVM: arm64: nv: Fast-track 'InHost' exception returns
KVM: arm64: nv: Honor HFGITR_EL2.ERET being set
KVM: arm64: nv: Handle HCR_EL2.{API,APK} independently
KVM: arm64: nv: Reinject PAC exceptions caused by HCR_EL2.API==0
KVM: arm64: nv: Add kvm_has_pauth() helper
KVM: arm64: nv: Add emulation for ERETAx instructions
KVM: arm64: nv: Handle ERETA[AB] instructions
KVM: arm64: nv: Advertise support for PAuth
KVM: arm64: Drop trapping of PAuth instructions/keys

 arch/arm64/include/asm/esr.h            |  12 ++
 arch/arm64/include/asm/kvm_emulate.h    |  10 --
 arch/arm64/include/asm/kvm_host.h       |  26 +++-
 arch/arm64/include/asm/kvm_nested.h     |  13 ++
 arch/arm64/include/asm/kvm_ptrauth.h    |  21 +++
 arch/arm64/include/asm/pgtable-hwdef.h  |   1 +
 arch/arm64/kvm/Makefile                 |   1 +
 arch/arm64/kvm/arm.c                    |  83 +++++++++-
 arch/arm64/kvm/emulate-nested.c         |  66 +++++---
 arch/arm64/kvm/handle_exit.c            |  36 ++++-
 arch/arm64/kvm/hyp/include/hyp/switch.h |  62 +-------
 arch/arm64/kvm/hyp/nvhe/switch.c        |   4 +-
 arch/arm64/kvm/hyp/vhe/switch.c         |  96 +++++++++++-
 arch/arm64/kvm/nested.c                 |   8 +-
 arch/arm64/kvm/pauth.c                  | 196 ++++++++++++++++++++++++
 15 files changed, 514 insertions(+), 121 deletions(-)
 create mode 100644 arch/arm64/kvm/pauth.c
Signature · 1 line
2.39.2
author maintainer
#1 lore raw

PATCH v4 1/15 KVM: arm64: Harden __ctxt_sys_reg() against out-of-range values

The unsuspecting kernel tinkerer can be easily confused into writing something that looks like this:

	ikey.lo = __vcpu_sys_reg(vcpu, SYS_APIAKEYLO_EL1);

which seems vaguely sensible, until you realise that the second parameter is the encoding of a sysreg, and not the index into the vcpu sysreg file... Debugging what happens in this case is an interesting exercise in head<->wall interactions.

As they often say: "Any resemblance to actual persons, living or dead, or actual events is purely coincidental".

In order to save people's time, add some compile-time hardening that will at least weed out the "stupidly out of range" values. This will *not* catch anything that isn't a compile-time constant.

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_host.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm64/include/asm/kvm_host.h +8 -1
index 9e8a496fb284..e24bd876ec9a 100644
@@ -896,7 +896,7 @@ struct kvm_vcpu_arch {
  * Don't bother with VNCR-based accesses in the nVHE code, it has no
  * business dealing with NV.
  */
-static inline u64 *__ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
+static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
 {
 #if !defined (__KVM_NVHE_HYPERVISOR__)
 	if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&

@@ -906,6 +906,13 @@ static inline u64 *__ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
 	return (u64 *)&ctxt->sys_regs[r];
 }
 
+#define __ctxt_sys_reg(c,r)						\
+	({								\
+	    	BUILD_BUG_ON(__builtin_constant_p(r) &&			\
+			     (r) >= NR_SYS_REGS);			\
+		___ctxt_sys_reg(c, r);					\
+	})
+
 #define ctxt_sys_reg(c,r)	(*__ctxt_sys_reg(c,r))
 
 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
Signature · 1 line
2.39.2
author maintainer
#2 lore raw

PATCH v4 2/15 KVM: arm64: Add helpers for ESR_ELx_ERET_ISS_ERET*

In reply to Marc Zyngier

The ESR_ELx_ERET_ISS_ERET* macros are a bit confusing:

- ESR_ELx_ERET_ISS_ERET really indicates that we have trapped an ERETA* instruction, as opposed to an ERET

- ESR_ELx_ERET_ISS_ERETA really indicates that we have trapped an ERETAB instruction, as opposed to an ERETAA.

We could repaint those to make more sense, but these are the names that are present in the ARM ARM, and we are sentimentally attached to those.

Instead, add two new helpers:

- esr_iss_is_eretax() being true tells you that you need to authenticate the ERET

- esr_iss_is_eretab() tells you that you need to use the B key instead of the A key

Following patches will make use of these primitives.

Suggested-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/esr.h | 12 ++++++++++++
 arch/arm64/kvm/handle_exit.c |  2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)
arch/arm64/include/asm/esr.h +12 -0
index 81606bf7d5ac..7abf09df7033 100644
@@ -404,6 +404,18 @@ static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
 	return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_ACCESS;
 }
 
+/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */
+static inline bool esr_iss_is_eretax(unsigned long esr)
+{
+	return esr & ESR_ELx_ERET_ISS_ERET;
+}
+
+/* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */
+static inline bool esr_iss_is_eretab(unsigned long esr)
+{
+	return esr & ESR_ELx_ERET_ISS_ERETA;
+}
+
 const char *esr_get_class_string(unsigned long esr);
 #endif /* __ASSEMBLY */
arch/arm64/kvm/handle_exit.c +1 -1
index 617ae6dea5d5..15221e481ccd 100644
@@ -219,7 +219,7 @@ static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu)
 
 static int kvm_handle_eret(struct kvm_vcpu *vcpu)
 {
-	if (kvm_vcpu_get_esr(vcpu) & ESR_ELx_ERET_ISS_ERET)
+	if (esr_iss_is_eretax(kvm_vcpu_get_esr(vcpu)))
 		return kvm_handle_ptrauth(vcpu);
 
 	/*
Signature · 1 line
2.39.2
author maintainer
#3 lore raw

PATCH v4 3/15 KVM: arm64: Constraint PAuth support to consistent implementations

In reply to Marc Zyngier

PAuth comes it two parts: address authentication, and generic authentication. So far, KVM mandates that both are implemented.

PAuth also comes in three flavours: Q5, Q3, and IMPDEF. Only one can be implemented for any of address and generic authentication.

Crucially, the architecture doesn't mandate that address and generic authentication implement the *same* flavour. This would make implementing ERETAx very difficult for NV, something we are not terribly keen on.

So only allow PAuth support for KVM on systems that are not totally insane. Which is so far 100% of the known HW.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/arm.c | 38 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)
arch/arm64/kvm/arm.c +36 -2
index 3dee5490eea9..a7178af1ab0c 100644
@@ -218,6 +218,40 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
 	kvm_arm_teardown_hypercalls(kvm);
 }
 
+static bool kvm_has_full_ptr_auth(void)
+{
+	bool apa, gpa, api, gpi, apa3, gpa3;
+	u64 isar1, isar2, val;
+
+	/*
+	 * Check that:
+	 *
+	 * - both Address and Generic auth are implemented for a given
+         *   algorithm (Q5, IMPDEF or Q3)
+	 * - only a single algorithm is implemented.
+	 */
+	if (!system_has_full_ptr_auth())
+		return false;
+
+	isar1 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);
+	isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
+
+	apa = !!FIELD_GET(ID_AA64ISAR1_EL1_APA_MASK, isar1);
+	val = FIELD_GET(ID_AA64ISAR1_EL1_GPA_MASK, isar1);
+	gpa = (val == ID_AA64ISAR1_EL1_GPA_IMP);
+
+	api = !!FIELD_GET(ID_AA64ISAR1_EL1_API_MASK, isar1);
+	val = FIELD_GET(ID_AA64ISAR1_EL1_GPI_MASK, isar1);
+	gpi = (val == ID_AA64ISAR1_EL1_GPI_IMP);
+
+	apa3 = !!FIELD_GET(ID_AA64ISAR2_EL1_APA3_MASK, isar2);
+	val  = FIELD_GET(ID_AA64ISAR2_EL1_GPA3_MASK, isar2);
+	gpa3 = (val == ID_AA64ISAR2_EL1_GPA3_IMP);
+
+	return (apa == gpa && api == gpi && apa3 == gpa3 &&
+		(apa + api + apa3) == 1);
+}
+
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 {
 	int r;

@@ -311,7 +345,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 		break;
 	case KVM_CAP_ARM_PTRAUTH_ADDRESS:
 	case KVM_CAP_ARM_PTRAUTH_GENERIC:
-		r = system_has_full_ptr_auth();
+		r = kvm_has_full_ptr_auth();
 		break;
 	case KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE:
 		if (kvm)

@@ -1270,7 +1304,7 @@ static unsigned long system_supported_vcpu_features(void)
 	if (!system_supports_sve())
 		clear_bit(KVM_ARM_VCPU_SVE, &features);
 
-	if (!system_has_full_ptr_auth()) {
+	if (!kvm_has_full_ptr_auth()) {
 		clear_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, &features);
 		clear_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features);
 	}
Signature · 1 line
2.39.2
author maintainer
#4 lore raw

PATCH v4 4/15 KVM: arm64: nv: Drop VCPU_HYP_CONTEXT flag

In reply to Marc Zyngier

It has become obvious that HCR_EL2.NV serves the exact same use as VCPU_HYP_CONTEXT, only in an architectural way. So just drop the flag for good.

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_host.h | 2 --
 arch/arm64/kvm/hyp/vhe/switch.c   | 7 +------
 2 files changed, 1 insertion(+), 8 deletions(-)
arch/arm64/include/asm/kvm_host.h +0 -2
index e24bd876ec9a..5566191d646a 100644
@@ -817,8 +817,6 @@ struct kvm_vcpu_arch {
 #define DEBUG_STATE_SAVE_SPE	__vcpu_single_flag(iflags, BIT(5))
 /* Save TRBE context if active  */
 #define DEBUG_STATE_SAVE_TRBE	__vcpu_single_flag(iflags, BIT(6))
-/* vcpu running in HYP context */
-#define VCPU_HYP_CONTEXT	__vcpu_single_flag(iflags, BIT(7))
 
 /* SVE enabled for host EL0 */
 #define HOST_SVE_ENABLED	__vcpu_single_flag(sflags, BIT(0))
arch/arm64/kvm/hyp/vhe/switch.c +1 -6
index 1581df6aec87..07fd9f70f870 100644
@@ -197,7 +197,7 @@ static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
 	 * If we were in HYP context on entry, adjust the PSTATE view
 	 * so that the usual helpers work correctly.
 	 */
-	if (unlikely(vcpu_get_flag(vcpu, VCPU_HYP_CONTEXT))) {
+	if (vcpu_has_nv(vcpu) && (read_sysreg(hcr_el2) & HCR_NV)) {
 		u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
 
 		switch (mode) {

@@ -240,11 +240,6 @@ static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 	sysreg_restore_guest_state_vhe(guest_ctxt);
 	__debug_switch_to_guest(vcpu);
 
-	if (is_hyp_ctxt(vcpu))
-		vcpu_set_flag(vcpu, VCPU_HYP_CONTEXT);
-	else
-		vcpu_clear_flag(vcpu, VCPU_HYP_CONTEXT);
-
 	do {
 		/* Jump in the fire! */
 		exit_code = __guest_enter(vcpu);
Signature · 1 line
2.39.2
author maintainer
#5 lore raw

PATCH v4 5/15 KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2

In reply to Marc Zyngier

Add the HCR_EL2 configuration for FEAT_NV2, adding the required bits for running a guest hypervisor, and overall merging the allowed bits provided by the guest.

This heavily replies on unavaliable features being sanitised when the HCR_EL2 shadow register is accessed, and only a couple of bits must be explicitly disabled.

Non-NV guests are completely unaffected by any of this.

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/hyp/include/hyp/switch.h |  4 +--
 arch/arm64/kvm/hyp/nvhe/switch.c        |  2 +-
 arch/arm64/kvm/hyp/vhe/switch.c         | 35 ++++++++++++++++++++++++-
 3 files changed, 36 insertions(+), 5 deletions(-)
arch/arm64/kvm/hyp/include/hyp/switch.h +1 -3
index e3fcf8c4d5b4..f5f701f309a9 100644
@@ -271,10 +271,8 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
 	__deactivate_traps_hfgxtr(vcpu);
 }
 
-static inline void ___activate_traps(struct kvm_vcpu *vcpu)
+static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
 {
-	u64 hcr = vcpu->arch.hcr_el2;
-
 	if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
 		hcr |= HCR_TVM;
arch/arm64/kvm/hyp/nvhe/switch.c +1 -1
index c50f8459e4fc..4103625e46c5 100644
@@ -40,7 +40,7 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
 {
 	u64 val;
 
-	___activate_traps(vcpu);
+	___activate_traps(vcpu, vcpu->arch.hcr_el2);
 	__activate_traps_common(vcpu);
 
 	val = vcpu->arch.cptr_el2;
arch/arm64/kvm/hyp/vhe/switch.c +34 -1
index 07fd9f70f870..6b82f0907882 100644
@@ -33,11 +33,44 @@ DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
 
+/*
+ * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1
+ * semantics, irrespective of the configuration), but that cannot be
+ * applied to the actual HW as things would otherwise break badly.
+ *
+ * - TGE: we want the guest to use EL1, which is incompatible with
+ *   this bit being set
+ *
+ * - API/APK: for hysterical raisins, we enable PAuth lazily, which
+ *   means that the guest's bits cannot be directly applied (we really
+ *   want to see the traps). Revisit this at some point.
+ */
+#define NV_HCR_GUEST_EXCLUDE	(HCR_TGE | HCR_API | HCR_APK)
+
+static u64 __compute_hcr(struct kvm_vcpu *vcpu)
+{
+	u64 hcr = vcpu->arch.hcr_el2;
+
+	if (!vcpu_has_nv(vcpu))
+		return hcr;
+
+	if (is_hyp_ctxt(vcpu)) {
+		hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB;
+
+		if (!vcpu_el2_e2h_is_set(vcpu))
+			hcr |= HCR_NV1;
+
+		write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2);
+	}
+
+	return hcr | (__vcpu_sys_reg(vcpu, HCR_EL2) & ~NV_HCR_GUEST_EXCLUDE);
+}
+
 static void __activate_traps(struct kvm_vcpu *vcpu)
 {
 	u64 val;
 
-	___activate_traps(vcpu);
+	___activate_traps(vcpu, __compute_hcr(vcpu));
 
 	if (has_cntpoff()) {
 		struct timer_map map;
Signature · 1 line
2.39.2
author maintainer
#6 lore raw

PATCH v4 6/15 KVM: arm64: nv: Add trap forwarding for ERET and SMC

In reply to Marc Zyngier

Honor the trap forwarding bits for both ERET and SMC, using a new helper that checks for common conditions.

Reviewed-by Joey Gouly <[email protected]>
Co-developed-by Jintack Lim <[email protected]>
Signed-off-by Jintack Lim <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_nested.h |  1 +
 arch/arm64/kvm/emulate-nested.c     | 27 +++++++++++++++++++++++++++
 arch/arm64/kvm/handle_exit.c        |  7 +++++++
 3 files changed, 35 insertions(+)
arch/arm64/include/asm/kvm_nested.h +1 -0
index c77d795556e1..dbc4e3a67356 100644
@@ -60,6 +60,7 @@ static inline u64 translate_ttbr0_el2_to_ttbr0_el1(u64 ttbr0)
 	return ttbr0 & ~GENMASK_ULL(63, 48);
 }
 
+extern bool forward_smc_trap(struct kvm_vcpu *vcpu);
 
 int kvm_init_nv_sysregs(struct kvm *kvm);
arch/arm64/kvm/emulate-nested.c +27 -0
index 4697ba41b3a9..2d80e81ae650 100644
@@ -2117,6 +2117,26 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *sr_index)
 	return true;
 }
 
+static bool forward_traps(struct kvm_vcpu *vcpu, u64 control_bit)
+{
+	bool control_bit_set;
+
+	if (!vcpu_has_nv(vcpu))
+		return false;
+
+	control_bit_set = __vcpu_sys_reg(vcpu, HCR_EL2) & control_bit;
+	if (!is_hyp_ctxt(vcpu) && control_bit_set) {
+		kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
+		return true;
+	}
+	return false;
+}
+
+bool forward_smc_trap(struct kvm_vcpu *vcpu)
+{
+	return forward_traps(vcpu, HCR_TSC);
+}
+
 static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
 {
 	u64 mode = spsr & PSR_MODE_MASK;

@@ -2155,6 +2175,13 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
 	u64 spsr, elr, mode;
 	bool direct_eret;
 
+	/*
+	 * Forward this trap to the virtual EL2 if the virtual
+	 * HCR_EL2.NV bit is set and this is coming from !EL2.
+	 */
+	if (forward_traps(vcpu, HCR_NV))
+		return;
+
 	/*
 	 * Going through the whole put/load motions is a waste of time
 	 * if this is a VHE guest hypervisor returning to its own
arch/arm64/kvm/handle_exit.c +7 -0
index 15221e481ccd..6a88ec024e2f 100644
@@ -55,6 +55,13 @@ static int handle_hvc(struct kvm_vcpu *vcpu)
 
 static int handle_smc(struct kvm_vcpu *vcpu)
 {
+	/*
+	 * Forward this trapped smc instruction to the virtual EL2 if
+	 * the guest has asked for it.
+	 */
+	if (forward_smc_trap(vcpu))
+		return 1;
+
 	/*
 	 * "If an SMC instruction executed at Non-secure EL1 is
 	 * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a
Signature · 1 line
2.39.2
author maintainer
#7 lore raw

PATCH v4 7/15 KVM: arm64: nv: Fast-track 'InHost' exception returns

In reply to Marc Zyngier

A significant part of the FEAT_NV extension is to trap ERET instructions so that the hypervisor gets a chance to switch from a vEL2 L1 guest to an EL1 L2 guest.

But this also has the unfortunate consequence of trapping ERET in unsuspecting circumstances, such as staying at vEL2 (interrupt handling while being in the guest hypervisor), or returning to host userspace in the case of a VHE guest.

Although we already make some effort to handle these ERET quicker by not doing the put/load dance, it is still way too far down the line for it to be efficient enough.

For these cases, it would ideal to ERET directly, no question asked. Of course, we can't do that. But the next best thing is to do it as early as possible, in fixup_guest_exit(), much as we would handle FPSIMD exceptions.

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/emulate-nested.c | 29 +++-------------------
 arch/arm64/kvm/hyp/vhe/switch.c | 44 +++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 26 deletions(-)
arch/arm64/kvm/emulate-nested.c +3 -26
index 2d80e81ae650..63a74c0330f1 100644
@@ -2172,8 +2172,7 @@ static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
 
 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
 {
-	u64 spsr, elr, mode;
-	bool direct_eret;
+	u64 spsr, elr;
 
 	/*
 	 * Forward this trap to the virtual EL2 if the virtual

@@ -2182,33 +2181,11 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
 	if (forward_traps(vcpu, HCR_NV))
 		return;
 
-	/*
-	 * Going through the whole put/load motions is a waste of time
-	 * if this is a VHE guest hypervisor returning to its own
-	 * userspace, or the hypervisor performing a local exception
-	 * return. No need to save/restore registers, no need to
-	 * switch S2 MMU. Just do the canonical ERET.
-	 */
-	spsr = vcpu_read_sys_reg(vcpu, SPSR_EL2);
-	spsr = kvm_check_illegal_exception_return(vcpu, spsr);
-
-	mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT);
-
-	direct_eret  = (mode == PSR_MODE_EL0t &&
-			vcpu_el2_e2h_is_set(vcpu) &&
-			vcpu_el2_tge_is_set(vcpu));
-	direct_eret |= (mode == PSR_MODE_EL2h || mode == PSR_MODE_EL2t);
-
-	if (direct_eret) {
-		*vcpu_pc(vcpu) = vcpu_read_sys_reg(vcpu, ELR_EL2);
-		*vcpu_cpsr(vcpu) = spsr;
-		trace_kvm_nested_eret(vcpu, *vcpu_pc(vcpu), spsr);
-		return;
-	}
-
 	preempt_disable();
 	kvm_arch_vcpu_put(vcpu);
 
+	spsr = __vcpu_sys_reg(vcpu, SPSR_EL2);
+	spsr = kvm_check_illegal_exception_return(vcpu, spsr);
 	elr = __vcpu_sys_reg(vcpu, ELR_EL2);
 
 	trace_kvm_nested_eret(vcpu, elr, spsr);
arch/arm64/kvm/hyp/vhe/switch.c +44 -0

56 lines not on this page · raw message

Signature · 1 line
2.39.2
author maintainer
#8 lore raw

PATCH v4 8/15 KVM: arm64: nv: Honor HFGITR_EL2.ERET being set

In reply to Marc Zyngier

If the L1 hypervisor decides to trap ERETs while running L2, make sure we don't try to emulate it, just like we wouldn't if it had its NV bit set.

The exception will be reinjected from the core handler.

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/hyp/vhe/switch.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm64/kvm/hyp/vhe/switch.c +2 -1
index 390c7d99f617..26395171621b 100644
@@ -220,7 +220,8 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
 	 * Unless the trap has to be forwarded further down the line,
 	 * of course...
 	 */
-	if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV)
+	if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) ||
+	    (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET))
 		return false;
 
 	spsr = read_sysreg_el1(SYS_SPSR);
Signature · 1 line
2.39.2
author maintainer
#9 lore raw

PATCH v4 9/15 KVM: arm64: nv: Handle HCR_EL2.{API,APK} independently

In reply to Marc Zyngier

Although KVM couples API and APK for simplicity, the architecture makes no such requirement, and the two can be independently set or cleared.

Check for which of the two possible reasons we have trapped here, and if the corresponding L1 control bit isn't set, delegate the handling for forwarding.

Otherwise, set this exact bit in HCR_EL2 and resume the guest. Of course, in the non-NV case, we keep setting both bits and be done with it. Note that the entry core already saves/restores the keys should any of the two control bits be set.

This results in a bit of rework, and the removal of the (trivial) vcpu_ptrauth_enable() helper.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_emulate.h    |  5 ----
 arch/arm64/kvm/hyp/include/hyp/switch.h | 32 +++++++++++++++++++++----
 2 files changed, 27 insertions(+), 10 deletions(-)
arch/arm64/include/asm/kvm_emulate.h +0 -5
index 975af30af31f..87f2c31f3206 100644
@@ -125,11 +125,6 @@ static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
 	vcpu->arch.hcr_el2 |= HCR_TWI;
 }
 
-static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
-{
-	vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
-}
-
 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
 {
 	vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
arch/arm64/kvm/hyp/include/hyp/switch.h +27 -5
index f5f701f309a9..a0908d7a8f56 100644
@@ -480,11 +480,35 @@ DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
 {
 	struct kvm_cpu_context *ctxt;
-	u64 val;
+	u64 enable = 0;
 
 	if (!vcpu_has_ptrauth(vcpu))
 		return false;
 
+	/*
+	 * NV requires us to handle API and APK independently, just in
+	 * case the hypervisor is totally nuts. Please barf >here<.
+	 */
+	if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
+		switch (ESR_ELx_EC(kvm_vcpu_get_esr(vcpu))) {
+		case ESR_ELx_EC_PAC:
+			if (!(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_API))
+				return false;
+
+			enable |= HCR_API;
+			break;
+
+		case ESR_ELx_EC_SYS64:
+			if (!(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_APK))
+				return false;
+
+			enable |= HCR_APK;
+			break;
+		}
+	} else {
+		enable = HCR_API | HCR_APK;
+	}
+
 	ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
 	__ptrauth_save_key(ctxt, APIA);
 	__ptrauth_save_key(ctxt, APIB);

@@ -492,11 +516,9 @@ static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
 	__ptrauth_save_key(ctxt, APDB);
 	__ptrauth_save_key(ctxt, APGA);
 
-	vcpu_ptrauth_enable(vcpu);
 
-	val = read_sysreg(hcr_el2);
-	val |= (HCR_API | HCR_APK);
-	write_sysreg(val, hcr_el2);
+	vcpu->arch.hcr_el2 |= enable;
+	sysreg_clear_set(hcr_el2, 0, enable);
 
 	return true;
 }
Signature · 1 line
2.39.2
author maintainer
#10 lore raw

PATCH v4 10/15 KVM: arm64: nv: Reinject PAC exceptions caused by HCR_EL2.API==0

In reply to Marc Zyngier

In order for a L1 hypervisor to correctly handle PAuth instructions, it must observe traps caused by a L1 PAuth instruction when HCR_EL2.API==0. Since we already handle the case for API==1 as a fixup, only the exception injection case needs to be handled.

Rework the kvm_handle_ptrauth() callback to reinject the trap in this case. Note that APK==0 is already handled by the exising triage_sysreg_trap() helper.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/handle_exit.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)
arch/arm64/kvm/handle_exit.c +25 -3
index 6a88ec024e2f..1ba2f788b2c3 100644
@@ -214,12 +214,34 @@ static int handle_sve(struct kvm_vcpu *vcpu)
 }
 
 /*
- * Guest usage of a ptrauth instruction (which the guest EL1 did not turn into
- * a NOP). If we get here, it is that we didn't fixup ptrauth on exit, and all
- * that we can do is give the guest an UNDEF.
+ * Two possibilities to handle a trapping ptrauth instruction:
+ *
+ * - Guest usage of a ptrauth instruction (which the guest EL1 did not
+ *   turn into a NOP). If we get here, it is that we didn't fixup
+ *   ptrauth on exit, and all that we can do is give the guest an
+ *   UNDEF (as the guest isn't supposed to use ptrauth without being
+ *   told it could).
+ *
+ * - Running an L2 NV guest while L1 has left HCR_EL2.API==0, and for
+ *   which we reinject the exception into L1. API==1 is handled as a
+ *   fixup so the only way to get here is when API==0.
+ *
+ * Anything else is an emulation bug (hence the WARN_ON + UNDEF).
  */
 static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu)
 {
+	if (!vcpu_has_ptrauth(vcpu)) {
+		kvm_inject_undefined(vcpu);
+		return 1;
+	}
+
+	if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
+		kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
+		return 1;
+	}
+
+	/* Really shouldn't be here! */
+	WARN_ON_ONCE(1);
 	kvm_inject_undefined(vcpu);
 	return 1;
 }
Signature · 1 line
2.39.2
author maintainer
#11 lore raw

PATCH v4 11/15 KVM: arm64: nv: Add kvm_has_pauth() helper

In reply to Marc Zyngier

Pointer Authentication comes in many flavors, and a faithful emulation relies on correctly handling the flavour implemented by the HW.

For this, provide a new kvm_has_pauth() that checks whether we expose to the guest a particular level of support. This checks across all 3 possible authentication algorithms (Q5, Q3 and IMPDEF).

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_host.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm64/include/asm/kvm_host.h +15 -0
index 5566191d646a..ed4d82017b87 100644
@@ -1336,4 +1336,19 @@ bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
 	(get_idreg_field((kvm), id, fld) >= expand_field_sign(id, fld, min) && \
 	 get_idreg_field((kvm), id, fld) <= expand_field_sign(id, fld, max))
 
+/* Check for a given level of PAuth support */
+#define kvm_has_pauth(k, l)						\
+	({								\
+		bool pa, pi, pa3;					\
+									\
+		pa  = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l);	\
+		pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP);	\
+		pi  = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l);	\
+		pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP);	\
+		pa3  = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l);	\
+		pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP);	\
+									\
+		(pa + pi + pa3) == 1;					\
+	})
+
 #endif /* __ARM64_KVM_HOST_H__ */
Signature · 1 line
2.39.2
author maintainer
#12 lore raw

PATCH v4 12/15 KVM: arm64: nv: Add emulation for ERETAx instructions

In reply to Marc Zyngier

FEAT_NV has the interesting property of relying on ERET being trapped. An added complexity is that it also traps ERETAA and ERETAB, meaning that the Pointer Authentication aspect of these instruction must be emulated.

Add an emulation of Pointer Authentication, limited to ERETAx (always using SP_EL2 as the modifier and ELR_EL2 as the pointer), using the Generic Authentication instructions.

The emulation, however small, is placed in its own compilation unit so that it can be avoided if the configuration doesn't include it (or the toolchan in not up to the task).

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_nested.h    |  12 ++
 arch/arm64/include/asm/pgtable-hwdef.h |   1 +
 arch/arm64/kvm/Makefile                |   1 +
 arch/arm64/kvm/pauth.c                 | 196 +++++++++++++++++++++++++
 4 files changed, 210 insertions(+)
 create mode 100644 arch/arm64/kvm/pauth.c
arch/arm64/include/asm/kvm_nested.h +12 -0
index dbc4e3a67356..5e0ab0596246 100644
@@ -64,4 +64,16 @@ extern bool forward_smc_trap(struct kvm_vcpu *vcpu);
 
 int kvm_init_nv_sysregs(struct kvm *kvm);
 
+#ifdef CONFIG_ARM64_PTR_AUTH
+bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr);
+#else
+static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr)
+{
+	/* We really should never execute this... */
+	WARN_ON_ONCE(1);
+	*elr = 0xbad9acc0debadbad;
+	return false;
+}
+#endif
+
 #endif /* __ARM64_KVM_NESTED_H */
arch/arm64/include/asm/pgtable-hwdef.h +1 -0
index ef207a0d4f0d..9943ff0af4c9 100644
@@ -297,6 +297,7 @@
 #define TCR_TBI1		(UL(1) << 38)
 #define TCR_HA			(UL(1) << 39)
 #define TCR_HD			(UL(1) << 40)
+#define TCR_TBID0		(UL(1) << 51)
 #define TCR_TBID1		(UL(1) << 52)
 #define TCR_NFD0		(UL(1) << 53)
 #define TCR_NFD1		(UL(1) << 54)
arch/arm64/kvm/Makefile +1 -0
index c0c050e53157..04882b577575 100644
@@ -23,6 +23,7 @@ kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \
 	 vgic/vgic-its.o vgic/vgic-debug.o
 
 kvm-$(CONFIG_HW_PERF_EVENTS)  += pmu-emul.o pmu.o
+kvm-$(CONFIG_ARM64_PTR_AUTH)  += pauth.o
 
 always-y := hyp_constants.h hyp-constants.s
arch/arm64/kvm/pauth.c new file +196 -0

196 lines not on this page · raw message

Signature · 1 line
2.39.2
maintainer
#13 lore raw

Re: [PATCH v4 12/15] KVM: arm64: nv: Add emulation for ERETAx instructions

Hi Marc,

Quoted 105 lines · Marc Zyngier

FEAT_NV has the interesting property of relying on ERET being trapped. An added complexity is that it also traps ERETAA and ERETAB, meaning that the Pointer Authentication aspect of these instruction must be emulated.

Add an emulation of Pointer Authentication, limited to ERETAx (always using SP_EL2 as the modifier and ELR_EL2 as the pointer), using the Generic Authentication instructions.

The emulation, however small, is placed in its own compilation unit so that it can be avoided if the configuration doesn't include it (or the toolchan in not up to the task).

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
  arch/arm64/include/asm/kvm_nested.h    |  12 ++
  arch/arm64/include/asm/pgtable-hwdef.h |   1 +
  arch/arm64/kvm/Makefile                |   1 +
  arch/arm64/kvm/pauth.c                 | 196 +++++++++++++++++++++++++
  4 files changed, 210 insertions(+)

create mode 100644 arch/arm64/kvm/pauth.c

arch/arm64/include/asm/kvm_nested.h +12 -0
index dbc4e3a67356..5e0ab0596246 100644
@@ -64,4 +64,16 @@ extern bool forward_smc_trap(struct kvm_vcpu *vcpu);
 
  int kvm_init_nv_sysregs(struct kvm *kvm);
 
+#ifdef CONFIG_ARM64_PTR_AUTH
+bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr);
+#else
+static inline bool kvm_auth_eretax(struct kvm_vcpu *vcpu, u64 *elr)
+{
+	/* We really should never execute this... */
+	WARN_ON_ONCE(1);
+	*elr = 0xbad9acc0debadbad;
+	return false;
+}
+#endif
+
  #endif /* __ARM64_KVM_NESTED_H */
arch/arm64/include/asm/pgtable-hwdef.h +1 -0
index ef207a0d4f0d..9943ff0af4c9 100644
@@ -297,6 +297,7 @@
  #define TCR_TBI1		(UL(1) << 38)
  #define TCR_HA			(UL(1) << 39)
  #define TCR_HD			(UL(1) << 40)
+#define TCR_TBID0		(UL(1) << 51)
  #define TCR_TBID1		(UL(1) << 52)
  #define TCR_NFD0		(UL(1) << 53)
  #define TCR_NFD1		(UL(1) << 54)
arch/arm64/kvm/Makefile +1 -0
index c0c050e53157..04882b577575 100644
@@ -23,6 +23,7 @@ kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \
  	 vgic/vgic-its.o vgic/vgic-debug.o
 
  kvm-$(CONFIG_HW_PERF_EVENTS)  += pmu-emul.o pmu.o
+kvm-$(CONFIG_ARM64_PTR_AUTH)  += pauth.o
 
  always-y := hyp_constants.h hyp-constants.s
arch/arm64/kvm/pauth.c new file +31 -0
new file mode 100644
index 000000000000..a3a5c404375b
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 - Google LLC
+ * Author: Marc Zyngier <[email protected]>
+ *
+ * Primitive PAuth emulation for ERETAA/ERETAB.
+ *
+ * This code assumes that is is run from EL2, and that it is part of
+ * the emulation of ERETAx for a guest hypervisor. That's a lot of
+ * baked-in assumptions and shortcuts.
+ *
+ * Do no reuse for anything else!
+ */
+
+#include <linux/kvm_host.h>
+
+#include <asm/kvm_emulate.h>
+#include <asm/pointer_auth.h>
+
+static u64 compute_pac(struct kvm_vcpu *vcpu, u64 ptr,
+		       struct ptrauth_key ikey)
+{
+	struct ptrauth_key gkey;
+	u64 mod, pac = 0;
+
+	preempt_disable();
+
+	if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
+		mod = __vcpu_sys_reg(vcpu, SP_EL2);
+	else
+		mod = read_sysreg(sp_el1);

arch/arm64/kvm/pauth.c line 41

Quoted 10 lines
arch/arm64/kvm/pauth.c new file +10 -0
+
+	gkey.lo = read_sysreg_s(SYS_APGAKEYLO_EL1);
+	gkey.hi = read_sysreg_s(SYS_APGAKEYHI_EL1);
+
+	__ptrauth_key_install_nosync(APGA, ikey);
+	isb();
+
+	asm volatile(ARM64_ASM_PREAMBLE ".arch_extension pauth\n"
+		     "pacga %0, %1, %2" : "=r" (pac) : "r" (ptr), "r" (mod));
+	isb();

Some of our builders currently have an older version of GCC (v6) and after this change I am seeing ...

CC arch/arm64/kvm/pauth.o
/tmp/ccohst0v.s: Assembler messages:
/tmp/ccohst0v.s:1177: Error: unknown architectural extension `pauth'
/tmp/ccohst0v.s:1177: Error: unknown mnemonic pacga' -- pacga x21,x22,x0' /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:244: recipe for target 'arch/arm64/kvm/pauth.o' failed make[5]: *** [arch/arm64/kvm/pauth.o] Error 1 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485: recipe for target 'arch/arm64/kvm' failed make[4]: *** [arch/arm64/kvm] Error 2 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485: recipe for target 'arch/arm64' failed make[3]: *** [arch/arm64] Error 2

I know this is pretty old now and I am trying to get these builders updated. However, the kernel docs still show that GCC v5.1 is supported [0].

Jon

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/process/changes.rst

Signature · 1 line
nvpublic
reviewer
#14 lore raw

Re: [PATCH v4 12/15] KVM: arm64: nv: Add emulation for ERETAx instructions

Quoted 16 lines · Jon Hunter

Some of our builders currently have an older version of GCC (v6) and after this change I am seeing ...

  CC      arch/arm64/kvm/pauth.o
/tmp/ccohst0v.s: Assembler messages:
/tmp/ccohst0v.s:1177: Error: unknown architectural extension `pauth'
/tmp/ccohst0v.s:1177: Error: unknown mnemonic pacga' -- pacga x21,x22,x0' /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:244: recipe for target 'arch/arm64/kvm/pauth.o' failed make[5]: *** [arch/arm64/kvm/pauth.o] Error 1 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485: recipe for target 'arch/arm64/kvm' failed make[4]: *** [arch/arm64/kvm] Error 2 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485: recipe for target 'arch/arm64' failed make[3]: *** [arch/arm64] Error 2

Quoted 3 lines

I know this is pretty old now and I am trying to get these builders updated. However, the kernel docs still show that GCC v5.1 is supported [0].

Was just looking at the discussion [1] ;-) . FYI there is already a patch on the list [2] which should be merged soon.

[1] https://lore.kernel.org/r/CA+G9fYsCL5j-9JzqNH5X03kikL=O+BaCQQ8Ao3ADQvxDuZvqcg@mail.gmail.com
[2] https://lore.kernel.org/r/[email protected]

Zenghui

author maintainer
#15 lore raw

Re: [PATCH v4 12/15] KVM: arm64: nv: Add emulation for ERETAx instructions

Quoted 21 lines · Zenghui Yu
Quoted 19 lines · Jon Hunter

Some of our builders currently have an older version of GCC (v6) and after this change I am seeing ...

  CC      arch/arm64/kvm/pauth.o
/tmp/ccohst0v.s: Assembler messages:
/tmp/ccohst0v.s:1177: Error: unknown architectural extension pauth' /tmp/ccohst0v.s:1177: Error: unknown mnemonic pacga' -- `pacga x21,x22,x0' /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:244:
recipe for target 'arch/arm64/kvm/pauth.o' failed
make[5]: *** [arch/arm64/kvm/pauth.o] Error 1 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485:
recipe for target 'arch/arm64/kvm' failed
make[4]: *** [arch/arm64/kvm] Error 2 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485:
recipe for target 'arch/arm64' failed
make[3]: *** [arch/arm64] Error 2

Quoted 6 lines
Quoted 3 lines

I know this is pretty old now and I am trying to get these builders updated. However, the kernel docs still show that GCC v5.1 is supported [0].

Was just looking at the discussion [1] ;-) . FYI there is already a patch on the list [2] which should be merged soon.

Indeed. -next as of today already has the fix, although I'm reworking it to take Mark's remarks into account.

Jon, can you confirm that next-20240423 builds with your setup?

Thanks,

	M.
Signature · 1 line
Without deviation from the norm, progress is not possible.
maintainer Tested-by
#16 lore raw

Re: [PATCH v4 12/15] KVM: arm64: nv: Add emulation for ERETAx instructions

Quoted 27 lines · Marc Zyngier
Quoted 25 lines · Zenghui Yu
Quoted 22 lines · Jon Hunter

Some of our builders currently have an older version of GCC (v6) and after this change I am seeing ...

  CC      arch/arm64/kvm/pauth.o
/tmp/ccohst0v.s: Assembler messages:
/tmp/ccohst0v.s:1177: Error: unknown architectural extension pauth' /tmp/ccohst0v.s:1177: Error: unknown mnemonic pacga' -- `pacga x21,x22,x0' /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:244:
recipe for target 'arch/arm64/kvm/pauth.o' failed
make[5]: *** [arch/arm64/kvm/pauth.o] Error 1 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485:
recipe for target 'arch/arm64/kvm' failed
make[4]: *** [arch/arm64/kvm] Error 2 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485:
recipe for target 'arch/arm64' failed
make[3]: *** [arch/arm64] Error 2

I know this is pretty old now and I am trying to get these builders updated. However, the kernel docs still show that GCC v5.1 is supported [0].

Quoted 7 lines
Quoted 2 lines

Was just looking at the discussion [1] ;-) . FYI there is already a patch on the list [2] which should be merged soon.

Indeed. -next as of today already has the fix, although I'm reworking it to take Mark's remarks into account.

Jon, can you confirm that next-20240423 builds with your setup?

Yes that is building fine today too. Thanks!

Feel free to add my ...

Tested-by Jon Hunter <[email protected]>

Jon

Signature · 1 line
nvpublic
maintainer
#17 lore raw

Re: [PATCH v4 12/15] KVM: arm64: nv: Add emulation for ERETAx instructions

In reply to Zenghui Yu
Quoted 21 lines · Zenghui Yu
Quoted 16 lines · Jon Hunter

Some of our builders currently have an older version of GCC (v6) and after this change I am seeing ...

   CC      arch/arm64/kvm/pauth.o
/tmp/ccohst0v.s: Assembler messages:
/tmp/ccohst0v.s:1177: Error: unknown architectural extension `pauth'
/tmp/ccohst0v.s:1177: Error: unknown mnemonic pacga' -- pacga x21,x22,x0' /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:244: recipe for target 'arch/arm64/kvm/pauth.o' failed make[5]: *** [arch/arm64/kvm/pauth.o] Error 1 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485: recipe for target 'arch/arm64/kvm' failed make[4]: *** [arch/arm64/kvm] Error 2 /local/workdir/tegra/mlt-linux_next/kernel/scripts/Makefile.build:485: recipe for target 'arch/arm64' failed make[3]: *** [arch/arm64] Error 2

Quoted 3 lines

I know this is pretty old now and I am trying to get these builders updated. However, the kernel docs still show that GCC v5.1 is supported [0].

Quoted 5 lines

Was just looking at the discussion [1] ;-) . FYI there is already a patch on the list [2] which should be merged soon.

[1] https://lore.kernel.org/r/CA+G9fYsCL5j-9JzqNH5X03kikL=O+BaCQQ8Ao3ADQvxDuZvqcg@mail.gmail.com
[2] https://lore.kernel.org/r/[email protected]

Thanks for sharing! That does work for me.

Cheers
Jon

Signature · 1 line
nvpublic
author maintainer
#18 lore raw

PATCH v4 13/15 KVM: arm64: nv: Handle ERETA[AB] instructions

In reply to Marc Zyngier

Now that we have some emulation in place for ERETA[AB], we can plug it into the exception handling machinery.

As for a bare ERET, an "easy" ERETAx instruction is processed as a fixup, while something that requires a translation regime transition or an exception delivery is left to the slow path.

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/emulate-nested.c | 22 ++++++++++++++++++++--
 arch/arm64/kvm/handle_exit.c    |  3 ++-
 arch/arm64/kvm/hyp/vhe/switch.c | 13 +++++++++++--
 3 files changed, 33 insertions(+), 5 deletions(-)
arch/arm64/kvm/emulate-nested.c +20 -2
index 63a74c0330f1..72d733c74a38 100644
@@ -2172,7 +2172,7 @@ static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr)
 
 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
 {
-	u64 spsr, elr;
+	u64 spsr, elr, esr;
 
 	/*
 	 * Forward this trap to the virtual EL2 if the virtual

@@ -2181,12 +2181,30 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
 	if (forward_traps(vcpu, HCR_NV))
 		return;
 
+	/* Check for an ERETAx */
+	esr = kvm_vcpu_get_esr(vcpu);
+	if (esr_iss_is_eretax(esr) && !kvm_auth_eretax(vcpu, &elr)) {
+		/*
+		 * Oh no, ERETAx failed to authenticate.  If we have
+		 * FPACCOMBINE, deliver an exception right away.  If we
+		 * don't, then let the mangled ELR value trickle down the
+		 * ERET handling, and the guest will have a little surprise.
+		 */
+		if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE)) {
+			esr &= ESR_ELx_ERET_ISS_ERETA;
+			esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC);
+			kvm_inject_nested_sync(vcpu, esr);
+			return;
+		}
+	}
+
 	preempt_disable();
 	kvm_arch_vcpu_put(vcpu);
 
 	spsr = __vcpu_sys_reg(vcpu, SPSR_EL2);
 	spsr = kvm_check_illegal_exception_return(vcpu, spsr);
-	elr = __vcpu_sys_reg(vcpu, ELR_EL2);
+	if (!esr_iss_is_eretax(esr))
+		elr = __vcpu_sys_reg(vcpu, ELR_EL2);
 
 	trace_kvm_nested_eret(vcpu, elr, spsr);
arch/arm64/kvm/handle_exit.c +2 -1
index 1ba2f788b2c3..407bdfbb572b 100644
@@ -248,7 +248,8 @@ static int kvm_handle_ptrauth(struct kvm_vcpu *vcpu)
 
 static int kvm_handle_eret(struct kvm_vcpu *vcpu)
 {
-	if (esr_iss_is_eretax(kvm_vcpu_get_esr(vcpu)))
+	if (esr_iss_is_eretax(kvm_vcpu_get_esr(vcpu)) &&
+	    !vcpu_has_ptrauth(vcpu))
 		return kvm_handle_ptrauth(vcpu);
 
 	/*
arch/arm64/kvm/hyp/vhe/switch.c +11 -2
index 26395171621b..8e1d98b691c1 100644
@@ -208,7 +208,8 @@ void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)
 
 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
 {
-	u64 spsr, mode;
+	u64 esr = kvm_vcpu_get_esr(vcpu);
+	u64 spsr, elr, mode;
 
 	/*
 	 * Going through the whole put/load motions is a waste of time

@@ -242,10 +243,18 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
 		return false;
 	}
 
+	/* If ERETAx fails, take the slow path */
+	if (esr_iss_is_eretax(esr)) {
+		if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr)))
+			return false;
+	} else {
+		elr = read_sysreg_el1(SYS_ELR);
+	}
+
 	spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
 
 	write_sysreg_el2(spsr, SYS_SPSR);
-	write_sysreg_el2(read_sysreg_el1(SYS_ELR), SYS_ELR);
+	write_sysreg_el2(elr, SYS_ELR);
 
 	return true;
 }
Signature · 1 line
2.39.2
author maintainer
#19 lore raw

PATCH v4 14/15 KVM: arm64: nv: Advertise support for PAuth

In reply to Marc Zyngier

Now that we (hopefully) correctly handle ERETAx, drop the masking of the PAuth feature (something that was not even complete, as APA3 and AGA3 were still exposed).

Reviewed-by Joey Gouly <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/kvm/nested.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)
arch/arm64/kvm/nested.c +2 -6
index ced30c90521a..6813c7c7f00a 100644
@@ -35,13 +35,9 @@ static u64 limit_nv_id_reg(u32 id, u64 val)
 		break;
 
 	case SYS_ID_AA64ISAR1_EL1:
-		/* Support everything but PtrAuth and Spec Invalidation */
+		/* Support everything but Spec Invalidation */
 		val &= ~(GENMASK_ULL(63, 56)	|
-			 NV_FTR(ISAR1, SPECRES)	|
-			 NV_FTR(ISAR1, GPI)	|
-			 NV_FTR(ISAR1, GPA)	|
-			 NV_FTR(ISAR1, API)	|
-			 NV_FTR(ISAR1, APA));
+			 NV_FTR(ISAR1, SPECRES));
 		break;
 
 	case SYS_ID_AA64PFR0_EL1:
Signature · 1 line
2.39.2
author maintainer
#20 lore raw

PATCH v4 15/15 KVM: arm64: Drop trapping of PAuth instructions/keys

In reply to Marc Zyngier

We currently insist on disabling PAuth on vcpu_load(), and get to enable it on first guest use of an instruction or a key (ignoring the NV case for now).

It isn't clear at all what this is trying to achieve: guests tend to use PAuth when available, and nothing forces you to expose it to the guest if you don't want to. This also isn't totally free:
we take a full GPR save/restore between host and guest, only to write ten 64bit registers. The "value proposition" escapes me.

So let's forget this stuff and enable PAuth eagerly if exposed to the guest. This results in much simpler code. Performance wise, that's not bad either (tested on M2 Pro running a fully automated Debian installer as the workload):

- On a non-NV guest, I can see reduction of 0.24% in the number of cycles (measured with perf over 10 consecutive runs)

- On a NV guest (L2), I see a 2% reduction in wall-clock time (measured with 'time', as M2 doesn't have a PMUv3 and NV doesn't support it either)

So overall, a much reduced complexity and a (small) performance improvement.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm64/include/asm/kvm_emulate.h    |  5 --
 arch/arm64/include/asm/kvm_ptrauth.h    | 21 +++++++
 arch/arm64/kvm/arm.c                    | 45 +++++++++++++-
 arch/arm64/kvm/handle_exit.c            | 10 ++--
 arch/arm64/kvm/hyp/include/hyp/switch.h | 80 +------------------------
 arch/arm64/kvm/hyp/nvhe/switch.c        |  2 -
 arch/arm64/kvm/hyp/vhe/switch.c         |  6 +-
 7 files changed, 70 insertions(+), 99 deletions(-)
arch/arm64/include/asm/kvm_emulate.h +0 -5
index 87f2c31f3206..382164d791f4 100644
@@ -125,11 +125,6 @@ static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
 	vcpu->arch.hcr_el2 |= HCR_TWI;
 }
 
-static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
-{
-	vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
-}
-
 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
 {
 	return vcpu->arch.vsesr_el2;
arch/arm64/include/asm/kvm_ptrauth.h +21 -0
index 0cd0965255d2..d81bac256abc 100644
@@ -99,5 +99,26 @@ alternative_else_nop_endif
 .macro ptrauth_switch_to_hyp g_ctxt, h_ctxt, reg1, reg2, reg3
 .endm
 #endif /* CONFIG_ARM64_PTR_AUTH */
+
+#else  /* !__ASSEMBLY */
+
+#define __ptrauth_save_key(ctxt, key)					\
+	do {								\
+		u64 __val;                                              \
+		__val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1);	\
+		ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val;		\
+		__val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1);	\
+		ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val;		\
+	} while(0)
+
+#define ptrauth_save_keys(ctxt)						\
+	do {								\
+		__ptrauth_save_key(ctxt, APIA);				\
+		__ptrauth_save_key(ctxt, APIB);				\
+		__ptrauth_save_key(ctxt, APDA);				\
+		__ptrauth_save_key(ctxt, APDB);				\
+		__ptrauth_save_key(ctxt, APGA);				\
+	} while(0)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_KVM_PTRAUTH_H */
arch/arm64/kvm/arm.c +42 -3

66 lines not on this page · raw message

arch/arm64/kvm/handle_exit.c +4 -6
index 407bdfbb572b..b037f0a0e27e 100644
@@ -217,14 +217,12 @@ static int handle_sve(struct kvm_vcpu *vcpu)
  * Two possibilities to handle a trapping ptrauth instruction:
  *
  * - Guest usage of a ptrauth instruction (which the guest EL1 did not
- *   turn into a NOP). If we get here, it is that we didn't fixup
- *   ptrauth on exit, and all that we can do is give the guest an
- *   UNDEF (as the guest isn't supposed to use ptrauth without being
- *   told it could).
+ *   turn into a NOP). If we get here, it is because we didn't enable
+ *   ptrauth for the guest. This results in an UNDEF, as it isn't
+ *   supposed to use ptrauth without being told it could.
  *
  * - Running an L2 NV guest while L1 has left HCR_EL2.API==0, and for
- *   which we reinject the exception into L1. API==1 is handled as a
- *   fixup so the only way to get here is when API==0.
+ *   which we reinject the exception into L1.
  *
  * Anything else is an emulation bug (hence the WARN_ON + UNDEF).
  */
arch/arm64/kvm/hyp/include/hyp/switch.h +1 -79

98 lines not on this page · raw message

arch/arm64/kvm/hyp/nvhe/switch.c +0 -2
index 4103625e46c5..9dfe704bdb69 100644
@@ -191,7 +191,6 @@ static const exit_handler_fn hyp_exit_handlers[] = {
 	[ESR_ELx_EC_IABT_LOW]		= kvm_hyp_handle_iabt_low,
 	[ESR_ELx_EC_DABT_LOW]		= kvm_hyp_handle_dabt_low,
 	[ESR_ELx_EC_WATCHPT_LOW]	= kvm_hyp_handle_watchpt_low,
-	[ESR_ELx_EC_PAC]		= kvm_hyp_handle_ptrauth,
 	[ESR_ELx_EC_MOPS]		= kvm_hyp_handle_mops,
 };
 

@@ -203,7 +202,6 @@ static const exit_handler_fn pvm_exit_handlers[] = {
 	[ESR_ELx_EC_IABT_LOW]		= kvm_hyp_handle_iabt_low,
 	[ESR_ELx_EC_DABT_LOW]		= kvm_hyp_handle_dabt_low,
 	[ESR_ELx_EC_WATCHPT_LOW]	= kvm_hyp_handle_watchpt_low,
-	[ESR_ELx_EC_PAC]		= kvm_hyp_handle_ptrauth,
 	[ESR_ELx_EC_MOPS]		= kvm_hyp_handle_mops,
 };
arch/arm64/kvm/hyp/vhe/switch.c +2 -4
index 8e1d98b691c1..f374bcdab4d4 100644
@@ -41,9 +41,8 @@ DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
  * - TGE: we want the guest to use EL1, which is incompatible with
  *   this bit being set
  *
- * - API/APK: for hysterical raisins, we enable PAuth lazily, which
- *   means that the guest's bits cannot be directly applied (we really
- *   want to see the traps). Revisit this at some point.
+ * - API/APK: they are already accounted for by vcpu_load(), and can
+ *   only take effect across a load/put cycle (such as ERET)
  */
 #define NV_HCR_GUEST_EXCLUDE	(HCR_TGE | HCR_API | HCR_APK)
 

@@ -268,7 +267,6 @@ static const exit_handler_fn hyp_exit_handlers[] = {
 	[ESR_ELx_EC_IABT_LOW]		= kvm_hyp_handle_iabt_low,
 	[ESR_ELx_EC_DABT_LOW]		= kvm_hyp_handle_dabt_low,
 	[ESR_ELx_EC_WATCHPT_LOW]	= kvm_hyp_handle_watchpt_low,
-	[ESR_ELx_EC_PAC]		= kvm_hyp_handle_ptrauth,
 	[ESR_ELx_EC_ERET]		= kvm_hyp_handle_eret,
 	[ESR_ELx_EC_MOPS]		= kvm_hyp_handle_mops,
 };
Signature · 1 line
2.39.2
Reviewed-by on the v4 series
#21 lore raw
In reply to Marc Zyngier
Quoted 5 lines · Marc Zyngier

This is the fourth version of this series introducing ERET and PAuth support for NV guests, and now the base prefix for the NV support series.

Unless someone shouts, I intend to take this in for 6.10.

Meant to do this for the last spin, sorry:

Reviewed-by Oliver Upton <[email protected]>
Signature · 2 lines
Thanks,
Oliver
author maintainer
#22 lore raw
Quoted 11 lines · Oliver Upton
Quoted 5 lines · Marc Zyngier

This is the fourth version of this series introducing ERET and PAuth support for NV guests, and now the base prefix for the NV support series.

Unless someone shouts, I intend to take this in for 6.10.

Meant to do this for the last spin, sorry:

Reviewed-by Oliver Upton <[email protected]>

Thanks! I'll queue the series shortly so that it can simmer in -next for a bit. Potential fixes can go on top if required.

	M.
Signature · 1 line
Without deviation from the norm, progress is not possible.
author maintainer Applied
#23 lore raw
In reply to Marc Zyngier
Quoted 9 lines · Marc Zyngier

This is the fourth version of this series introducing ERET and PAuth support for NV guests, and now the base prefix for the NV support series.

Unless someone shouts, I intend to take this in for 6.10.

* From v3 [3]

[...]

Applied to next, thanks!

[01/15] KVM: arm64: Harden __ctxt_sys_reg() against out-of-range values

        commit: 1b06b99f25e0c957feb488ff8117a37f592c3866
[02/15] KVM: arm64: Add helpers for ESR_ELx_ERET_ISS_ERET*
        commit: 80d8b55a57a18b0b1dac951ea28bfd657b14facc
[03/15] KVM: arm64: Constraint PAuth support to consistent implementations
        commit: a07e9345615fb7e7dd4fd5d88d5aaf49085739d0
[04/15] KVM: arm64: nv: Drop VCPU_HYP_CONTEXT flag
        commit: 6f57c6be2a0889cc0fd32b0cd2eb25dfee20dde3
[05/15] KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2
        commit: 04ab519bb86df10bb8b72054fce9af1d72c36805
[06/15] KVM: arm64: nv: Add trap forwarding for ERET and SMC
        commit: 95537f06b9e826766f32e513d714e1cda468ef15
[07/15] KVM: arm64: nv: Fast-track 'InHost' exception returns
        commit: dd0717a998f77f449c70bee82626cbf9913fe78d
[08/15] KVM: arm64: nv: Honor HFGITR_EL2.ERET being set
        commit: 4cc3f31914d6df9dba8825db933d19c60028f5a8
[09/15] KVM: arm64: nv: Handle HCR_EL2.{API,APK} independently
        commit: 279946ada1f26a905061d0d6f134fff9e7b14239
[10/15] KVM: arm64: nv: Reinject PAC exceptions caused by HCR_EL2.API==0
        commit: 15db034733e4df3ca8ab4bf0a593a8a9b4860541
[11/15] KVM: arm64: nv: Add kvm_has_pauth() helper
        commit: 719f5206a8fd8336d23ccda6fe2a3287fbfb4c92
[12/15] KVM: arm64: nv: Add emulation for ERETAx instructions
        commit: 6ccc971ee2c61a1ffb487e46bf6184f7df6aacfb
[13/15] KVM: arm64: nv: Handle ERETA[AB] instructions
        commit: 213b3d1ea1612c6d26153be446923831c4534689
[14/15] KVM: arm64: nv: Advertise support for PAuth
        commit: f4f6a95bac49144c0d507c24af9905bb999a4579
[15/15] KVM: arm64: Drop trapping of PAuth instructions/keys
        commit: 814ad8f96e929fa9c60bd360d2f7bccfc1df0111

Cheers,

	M.
Signature · 1 line
Without deviation from the norm, progress is not possible.