enable Hisilicon HiP04 SoC

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               | 9 ++++++++-
 arch/arm/mach-berlin/Kconfig   | 2 +-
 arch/arm/mach-highbank/Kconfig | 2 +-
 arch/arm/mach-mvebu/Kconfig    | 6 +++---
 arch/arm/mach-omap2/Kconfig    | 4 ++--
 arch/arm/mach-qcom/Kconfig     | 2 +-
 arch/arm/mach-shmobile/Kconfig | 2 +-
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-vexpress/Kconfig | 2 +-
 9 files changed, 19 insertions(+), 12 deletions(-)

arch/arm/Kconfig +0 -0

index ab438cb..9a2214e 100644

arch/arm/Kconfig +5 -0

+	select ARCH_MULTI_V6_V7
+	select CPU_V7
+	select HAVE_SMP
+	select ARM_LPAE if !(ARCH_MULTI_V6 || ARCH_MULTI_V7)
+
 config ARCH_MULTI_V6_V7
 	bool
 	select MIGHT_HAVE_CACHE_L2X0

arch/arm/mach-berlin/Kconfig +1 -1

index b0cb072..be0512d 100644
@@ -1,5 +1,5 @@
 config ARCH_BERLIN
-	bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
+	bool "Marvell Berlin SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V7_LPAE)
 	select ARM_GIC
 	select GENERIC_IRQ_CHIP
 	select DW_APB_ICTL

arch/arm/mach-highbank/Kconfig +1 -1

index 830b76e..9b6b3f8 100644
@@ -1,5 +1,5 @@
 config ARCH_HIGHBANK
-	bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
+	bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7_LPAE
 	select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_HOLES_MEMORYMODEL

arch/arm/mach-mvebu/Kconfig +1 -1

index 3f73eec..16f69ae 100644
@@ -1,5 +1,5 @@
 config ARCH_MVEBU
-	bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5)
+	bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V7_LPAE || ARCH_MULTI_V5)
 	select ARCH_SUPPORTS_BIG_ENDIAN
 	select CLKSRC_MMIO
 	select GENERIC_IRQ_CHIP

Hi Haojian,

Quoted 23 lines · Haojian Zhuang

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               | 9 ++++++++-
 arch/arm/mach-berlin/Kconfig   | 2 +-
 arch/arm/mach-highbank/Kconfig | 2 +-
 arch/arm/mach-mvebu/Kconfig    | 6 +++---
 arch/arm/mach-omap2/Kconfig    | 4 ++--
 arch/arm/mach-qcom/Kconfig     | 2 +-
 arch/arm/mach-shmobile/Kconfig | 2 +-
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-vexpress/Kconfig | 2 +-
 9 files changed, 19 insertions(+), 12 deletions(-)

arch/arm/Kconfig +0 -0

index ab438cb..9a2214e 100644

arch/arm/Kconfig config ARCH_MULTI_V6 · line 921

Quoted 5 lines

arch/arm/Kconfig +1 -1

@@ -918,12 +918,19 @@ config ARCH_MULTI_V6
      select CPU_V6K
 
 config ARCH_MULTI_V7
-     bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
+     bool "ARMv7 non-LPAE based platforms (Cortex-A5/A8/A9, PJ4, Scorpion)"

Actually some PJ4B are also non LPAE capable

Quoted 5 lines

arch/arm/Kconfig +0 -0

      default y
      select ARCH_MULTI_V6_V7
      select CPU_V7
      select HAVE_SMP
 

arch/arm/Kconfig config ARCH_MULTI_V6 · line 928

Quoted 2 lines

arch/arm/Kconfig +2 -0

+config ARCH_MULTI_V7_LPAE
+     bool "ARMv7 LPAE based platforms (Cortex-A7/A12/A15/A17, Brahma-B15, PJ4B, Krait)"

Only Armada XP is LPAE capable, and and the CPU is not a "simple" PJ4B but a PJ4B-MP

arch/arm/Kconfig config ARCH_MULTI_V6 · line 930

Quoted 4 lines

arch/arm/Kconfig +1 -1

 config MACH_ARMADA_370
-     bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
+     bool "Marvell Armada 370 boards" if ARCH_MULTI_V7_LPAE

Armada 370 is not LPAE capable

arch/arm/Kconfig config MACH_ARMADA_38X · line 65

Quoted 12 lines

arch/arm/Kconfig +1 -1

      select ARMADA_370_CLK
      select CPU_PJ4B
      select MACH_MVEBU_V7

@@ -59,7 +59,7 @@ config MACH_ARMADA_38X
        on the Marvell Armada 380/385 SoC with device tree.
 
 config MACH_ARMADA_XP
-     bool "Marvell Armada XP boards" if ARCH_MULTI_V7
+     bool "Marvell Armada XP boards" if ARCH_MULTI_V7_LPAE
      select ARMADA_XP_CLK
      select CPU_PJ4B
      select MACH_MVEBU_V7

Thanks,

Gregory

--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Quoted 39 lines · Gregory CLEMENT

Hi Haojian,

Quoted 23 lines · Haojian Zhuang

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               | 9 ++++++++-
 arch/arm/mach-berlin/Kconfig   | 2 +-
 arch/arm/mach-highbank/Kconfig | 2 +-
 arch/arm/mach-mvebu/Kconfig    | 6 +++---
 arch/arm/mach-omap2/Kconfig    | 4 ++--
 arch/arm/mach-qcom/Kconfig     | 2 +-
 arch/arm/mach-shmobile/Kconfig | 2 +-
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-vexpress/Kconfig | 2 +-
 9 files changed, 19 insertions(+), 12 deletions(-)

arch/arm/Kconfig +0 -0

index ab438cb..9a2214e 100644

arch/arm/Kconfig config ARCH_MULTI_V6 · line 921

Quoted 5 lines

arch/arm/Kconfig +1 -1

@@ -918,12 +918,19 @@ config ARCH_MULTI_V6
      select CPU_V6K
 
 config ARCH_MULTI_V7
-     bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
+     bool "ARMv7 non-LPAE based platforms (Cortex-A5/A8/A9, PJ4, Scorpion)"

Actually some PJ4B are also non LPAE capable

Quoted 5 lines

arch/arm/Kconfig +0 -0

      default y
      select ARCH_MULTI_V6_V7
      select CPU_V7
      select HAVE_SMP
 

Quoted 4 lines

arch/arm/Kconfig config ARCH_MULTI_V6 · line 928

Quoted 2 lines

arch/arm/Kconfig +2 -0

+config ARCH_MULTI_V7_LPAE
+     bool "ARMv7 LPAE based platforms (Cortex-A7/A12/A15/A17, Brahma-B15, PJ4B, Krait)"

Only Armada XP is LPAE capable, and and the CPU is not a "simple" PJ4B but a PJ4B-MP

Do you mind that I append CPU_PJ4B_MP?

Quoted 31 lines

arch/arm/Kconfig config ARCH_MULTI_V6 · line 930

Quoted 5 lines

arch/arm/Kconfig +1 -1

 config MACH_ARMADA_370
-     bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
+     bool "Marvell Armada 370 boards" if ARCH_MULTI_V7_LPAE

Armada 370 is not LPAE capable

arch/arm/Kconfig config MACH_ARMADA_38X · line 65

Quoted 12 lines

arch/arm/Kconfig +1 -1

      select ARMADA_370_CLK
      select CPU_PJ4B
      select MACH_MVEBU_V7

@@ -59,7 +59,7 @@ config MACH_ARMADA_38X
        on the Marvell Armada 380/385 SoC with device tree.
 
 config MACH_ARMADA_XP
-     bool "Marvell Armada XP boards" if ARCH_MULTI_V7
+     bool "Marvell Armada XP boards" if ARCH_MULTI_V7_LPAE
      select ARMADA_XP_CLK
      select CPU_PJ4B
      select MACH_MVEBU_V7

Thanks,

Gregory

--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Quoted 46 lines · Haojian Zhuang

Quoted 43 lines · Gregory CLEMENT

Hi Haojian,

Quoted 23 lines · Haojian Zhuang

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               | 9 ++++++++-
 arch/arm/mach-berlin/Kconfig   | 2 +-
 arch/arm/mach-highbank/Kconfig | 2 +-
 arch/arm/mach-mvebu/Kconfig    | 6 +++---
 arch/arm/mach-omap2/Kconfig    | 4 ++--
 arch/arm/mach-qcom/Kconfig     | 2 +-
 arch/arm/mach-shmobile/Kconfig | 2 +-
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-vexpress/Kconfig | 2 +-
 9 files changed, 19 insertions(+), 12 deletions(-)

arch/arm/Kconfig +0 -0

index ab438cb..9a2214e 100644

arch/arm/Kconfig config ARCH_MULTI_V6 · line 921

Quoted 5 lines

arch/arm/Kconfig +1 -1

@@ -918,12 +918,19 @@ config ARCH_MULTI_V6
      select CPU_V6K
 
 config ARCH_MULTI_V7
-     bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
+     bool "ARMv7 non-LPAE based platforms (Cortex-A5/A8/A9, PJ4, Scorpion)"

Actually some PJ4B are also non LPAE capable

arch/arm/Kconfig config ARCH_MULTI_V6 · line 928

Quoted 7 lines

arch/arm/Kconfig +2 -0

      default y
      select ARCH_MULTI_V6_V7
      select CPU_V7
      select HAVE_SMP
 
+config ARCH_MULTI_V7_LPAE
+     bool "ARMv7 LPAE based platforms (Cortex-A7/A12/A15/A17, Brahma-B15, PJ4B, Krait)"

Only Armada XP is LPAE capable, and and the CPU is not a "simple" PJ4B but a PJ4B-MP

Quoted 1 line

Do you mind that I append CPU_PJ4B_MP?

Currently we make no difference in the code between PJ4B and PJ4B-MP. Moreover the ARCH_MULTI_V7_LPAE vs ARCH_MULTI_V7 si done by SoC not by CPU.

Maybe I missed something, what is your proposal?

Quoted 53 lines · Gregory CLEMENT

Quoted 41 lines · Haojian Zhuang

Quoted 39 lines · Gregory CLEMENT

Hi Haojian,

Quoted 23 lines · Haojian Zhuang

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               | 9 ++++++++-
 arch/arm/mach-berlin/Kconfig   | 2 +-
 arch/arm/mach-highbank/Kconfig | 2 +-
 arch/arm/mach-mvebu/Kconfig    | 6 +++---
 arch/arm/mach-omap2/Kconfig    | 4 ++--
 arch/arm/mach-qcom/Kconfig     | 2 +-
 arch/arm/mach-shmobile/Kconfig | 2 +-
 arch/arm/mach-tegra/Kconfig    | 2 +-
 arch/arm/mach-vexpress/Kconfig | 2 +-
 9 files changed, 19 insertions(+), 12 deletions(-)

arch/arm/Kconfig +0 -0

index ab438cb..9a2214e 100644

arch/arm/Kconfig config ARCH_MULTI_V6 · line 921

Quoted 5 lines

arch/arm/Kconfig +1 -1

@@ -918,12 +918,19 @@ config ARCH_MULTI_V6
      select CPU_V6K
 
 config ARCH_MULTI_V7
-     bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
+     bool "ARMv7 non-LPAE based platforms (Cortex-A5/A8/A9, PJ4, Scorpion)"

Actually some PJ4B are also non LPAE capable

Quoted 5 lines

arch/arm/Kconfig +0 -0

      default y
      select ARCH_MULTI_V6_V7
      select CPU_V7
      select HAVE_SMP
 

Quoted 6 lines

Quoted 4 lines

arch/arm/Kconfig config ARCH_MULTI_V6 · line 928

Quoted 2 lines

arch/arm/Kconfig +2 -0

+config ARCH_MULTI_V7_LPAE
+     bool "ARMv7 LPAE based platforms (Cortex-A7/A12/A15/A17, Brahma-B15, PJ4B, Krait)"

Only Armada XP is LPAE capable, and and the CPU is not a "simple" PJ4B but a PJ4B-MP

Do you mind that I append CPU_PJ4B_MP?

Currently we make no difference in the code between PJ4B and PJ4B-MP. Moreover the ARCH_MULTI_V7_LPAE vs ARCH_MULTI_V7 si done by SoC not by CPU.

Quoted 2 lines

Maybe I missed something, what is your proposal?

Since they're same between PJ4B & PJ4B-MP, I shouldn't append a new PJ4B_MP.

I'll only use both ARCH_MULTI_V7 & ARCH_MULTI_V7_LPAE as the precondition on ARMADA_XP. I'll keep ARCH_MULTI_V7 as the precondition on other armada chips in mach-berlin directory.

So when multi_v7_lpae_defconfig is appended, only ARMADA_XP is built from mach-berlin directory. Is it OK?

Regards
Haojian

There's a little difference between ARM GIC and HiP04 GIC.

* HiP04 GIC could support 16 cores at most, and ARM GIC could support 8 cores at most. So the difination on GIC_DIST_SGIR,

GIC_DIST_SGI_PENDING_SET, GIC_DIST_SGI_PENDING_CLEAR
& GIC_DIST_TARGET registers are different since CPU interfaces are increased from 8-bit to 16-bit.

* HiP04 GIC could support 510 interrupts at most, and ARM GIC could support 1020 interrupts at most.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/irq-gic.c | 153 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 109 insertions(+), 44 deletions(-)

drivers/irqchip/irq-gic.c +0 -0

index 8fd27bf..18f3d56 100644

drivers/irqchip/irq-gic.c +0 -0

 };
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);

@@ -76,9 +78,14 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  * The GIC mapping of CPU interfaces does not necessarily match
  * the logical CPU numbering.  Let's use a mapping as returned
  * by the GIC itself.

drivers/irqchip/irq-gic.c +16 -9

+       u32 mask;
+       /* ARM GIC, nr_cpu_if == 8; HiP04 GIC, nr_cpu_if == 16 */
+       mask = (1 << nr_cpu_if) - 1;
+       return (mask << irq_to_core_shift(i, nr_cpu_if));
+}
+
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-       unsigned int shift = (gic_irq(d) % 4) * 8;
+       void __iomem *reg;
+       unsigned int i = gic_irq(d);
+       unsigned int shift = irq_to_core_shift(i, gic_data[0].nr_cpu_if);
        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
        u32 val, mask, bit;
-
-       if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
+       if (cpu >= gic_data[0].nr_cpu_if || cpu >= nr_cpu_ids)
                return -EINVAL;
 
+       reg = gic_dist_base(d) + GIC_DIST_TARGET +
+             irq_to_core_offset(i, gic_data[0].nr_cpu_if);
+
        raw_spin_lock(&irq_controller_lock);
-       mask = 0xff << shift;
+       mask = irq_to_core_mask(i, gic_data[0].nr_cpu_if);
        bit = gic_cpu_map[cpu] << shift;
        val = readl_relaxed(reg) & ~mask;
        writel_relaxed(val | bit, reg);

@@ -354,15 +392,16 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
-static u8 gic_get_cpumask(struct gic_chip_data *gic)
+static u16 gic_get_cpumask(struct gic_chip_data *gic)
 {
        void __iomem *base = gic_data_dist_base(gic);
-       u32 mask, i;
+       u32 mask, i, j, nr_if = gic->nr_if_per_reg;
 
-       for (i = mask = 0; i < 32; i += 4) {
-               mask = readl_relaxed(base + GIC_DIST_TARGET + i);

drivers/irqchip/irq-gic.c +5 -1

@@ -370,12 +409,16 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
        if (!mask)
                pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 
+       /* ARM GIC needs 8-bit cpu mask, HiP04 GIC needs 16-bit cpu mask. */
+       if (gic->nr_cpu_if == 8)
+               mask &= 0xff;
+
        return mask;
 }
 
 static void __init gic_dist_init(struct gic_chip_data *gic)
 {
-       unsigned int i;
+       unsigned int i, nr_if = gic->nr_if_per_reg;
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        void __iomem *base = gic_data_dist_base(gic);

drivers/irqchip/irq-gic.c +0 -2

        /*
         * Set priority on all global interrupts.
         */
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);

drivers/irqchip/irq-gic.c +11 -10

+       for (; i < DIV_ROUND_UP(gic_irqs, GIC_REG_BITS); i++)
+               writel_relaxed(0xffffffff,
+                              base + GIC_DIST_ENABLE_CLEAR + i * 4);
 
        writel_relaxed(1, base + GIC_DIST_CTRL);
 }

@@ -423,7 +468,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Get what the GIC says our CPU mask is.
         */
-       BUG_ON(cpu >= NR_GIC_CPU_IF);
+       BUG_ON(cpu >= gic->nr_cpu_if);
        cpu_mask = gic_get_cpumask(gic);
        gic_cpu_map[cpu] = cpu_mask;
 

@@ -431,7 +476,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
         * Clear our mask from the other map entries in case they're
         * still undefined.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
+       for (i = 0; i < gic->nr_cpu_if; i++)
                if (i != cpu)
                        gic_cpu_map[i] &= ~cpu_mask;
 

@@ -445,8 +490,8 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Set priority on PPI and SGI interrupts
         */
-       for (i = 0; i < 32; i += 4)
-               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+       for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
+               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
 
        writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
        writel_relaxed(1, base + GIC_CPU_CTRL);

@@ -467,7 +512,7 @@ void gic_cpu_if_down(void)
  */
 static void gic_dist_save(unsigned int gic_nr)
 {
-       unsigned int gic_irqs;
+       unsigned int gic_irqs, nr_if = gic_data[gic_nr].nr_if_per_reg;
        void __iomem *dist_base;
        int i;
 

@@ -484,7 +529,7 @@ static void gic_dist_save(unsigned int gic_nr)
                gic_data[gic_nr].saved_spi_conf[i] =
                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                gic_data[gic_nr].saved_spi_target[i] =
                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -502,7 +547,7 @@ static void gic_dist_save(unsigned int gic_nr)
  */
 static void gic_dist_restore(unsigned int gic_nr)
 {
-       unsigned int gic_irqs;
+       unsigned int gic_irqs, nr_if = gic_data[gic_nr].nr_if_per_reg;
        unsigned int i;
        void __iomem *dist_base;
 

@@ -525,7 +570,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                writel_relaxed(0xa0a0a0a0,
                        dist_base + GIC_DIST_PRI + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
                        dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -665,9 +710,15 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
         */
        dmb(ishst);
 
-       /* this always happens on GIC0 */
-       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

drivers/irqchip/irq-gic.c +0 -0

        raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 #endif

drivers/irqchip/irq-gic.c +1 -1

 }
 
 /*

@@ -700,7 +752,7 @@ int gic_get_cpu_id(unsigned int cpu)
 {
        unsigned int cpu_bit;
 
-       if (cpu >= NR_GIC_CPU_IF)
+       if (cpu >= gic_data[0].nr_cpu_if)
                return -1;
        cpu_bit = gic_cpu_map[cpu];
        if (cpu_bit & (cpu_bit - 1))

drivers/irqchip/irq-gic.c +2 -1

                for (j = i; j < i + 4; j++) {
                        if (val & 0xff)
                                writel_relaxed((1 << (new_cpu_id + 16)) | j,

@@ -931,7 +983,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
        irq_hw_number_t hwirq_base;
        struct gic_chip_data *gic;
        int gic_irqs, irq_base, i;
-       int nr_routable_irqs;
+       int nr_routable_irqs, max_nr_irq;
 
        BUG_ON(gic_nr >= MAX_GIC_NR);
 

@@ -967,12 +1019,23 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                gic_set_base_accessor(gic, gic_get_common_base);
        }
 
+       if (of_device_is_compatible(node, "hisilicon,hip04-gic")) {

drivers/irqchip/irq-gic.c +6 -5

        /*
         * Initialize the CPU interface map to all CPUs.
         * It will be refined as each CPU probes its ID.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               gic_cpu_map[i] = 0xff;
+       for (i = 0; i < gic->nr_cpu_if; i++)
+               gic_cpu_map[i] = (1 << gic->nr_cpu_if) - 1;
 
        /*
         * For primary GICs, skip over SGIs.

@@ -988,12 +1051,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 
        /*
         * Find out how many interrupts are supported.
-        * The GIC only supports up to 1020 interrupt sources.
+        * The ARM/Qualcomm GIC only supports up to 1020 interrupt sources.
+        * The HiP04 GIC only supports up to 510 interrupt sources.
         */
        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
-       if (gic_irqs > 1020)
-               gic_irqs = 1020;
+       if (gic_irqs > max_nr_irq)
+               gic_irqs = max_nr_irq;
        gic->gic_irqs = gic_irqs;
 
        gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */

Hi Haojian,

Quoted 4 lines · Haojian Zhuang

There's a little difference between ARM GIC and HiP04 GIC.

* HiP04 GIC could support 16 cores at most, and ARM GIC could support 8 cores at most. So the difination on GIC_DIST_SGIR,

definitions of

Quoted 12 lines

GIC_DIST_SGI_PENDING_SET, GIC_DIST_SGI_PENDING_CLEAR
& GIC_DIST_TARGET registers are different since CPU interfaces are increased from 8-bit to 16-bit.

* HiP04 GIC could support 510 interrupts at most, and ARM GIC could support 1020 interrupts at most.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/irq-gic.c | 153 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 109 insertions(+), 44 deletions(-)

drivers/irqchip/irq-gic.c struct gic_chip_data { · line 72

Quoted 10 lines

drivers/irqchip/irq-gic.c +2 -0

index 8fd27bf..18f3d56 100644
@@ -68,6 +68,8 @@ struct gic_chip_data {
 #ifdef CONFIG_GIC_NON_BANKED
        void __iomem *(*get_base)(union gic_base *);
 #endif
+       u32 nr_cpu_if;
+       u32 nr_if_per_reg;

Which register? Surely you can compute that at runtime.

Quoted 12 lines

drivers/irqchip/irq-gic.c +2 -1

 };
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);

@@ -76,9 +78,14 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  * The GIC mapping of CPU interfaces does not necessarily match
  * the logical CPU numbering.  Let's use a mapping as returned
  * by the GIC itself.
+ *
+ * Hisilicon HiP04 extends the number of CPU interface from 8 to 16.
  */
-#define NR_GIC_CPU_IF 8

drivers/irqchip/irq-gic.c static DEFINE_RAW_SPINLOCK(irq_controller_lock); · line 88

Quoted 6 lines

drivers/irqchip/irq-gic.c +5 -1

-static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+#define NR_GIC_CPU_IF  16
+static u16 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+
+/* GIC register is always 32-bit long whatever it's in ARM64 or ARM32 */
+#define GIC_REG_BITS   32

What doesn this buy us? I'm not sure we gain much from it.

Quoted 6 lines

drivers/irqchip/irq-gic.c +0 -0

 /*
  * Supported arch specific GIC irq extension.

@@ -242,19 +249,50 @@ static int gic_retrigger(struct irq_data *d)
 }
 

drivers/irqchip/irq-gic.c static int gic_retrigger(struct irq_data *d) · line 253

Quoted 3 lines

drivers/irqchip/irq-gic.c +2 -0

 #ifdef CONFIG_SMP
+static inline u32 irq_to_core_offset(u32 i, u32 nr_cpu_if)
+{

Make this function take an irq_data pointer, and use the accessor to find out about the number of CPU interfaces.

drivers/irqchip/irq-gic.c static int gic_retrigger(struct irq_data *d) · line 256

Quoted 4 lines

drivers/irqchip/irq-gic.c +3 -0

+       if (nr_cpu_if == 8) {
+               /* ARM GIC, i / 4 * 4 */
+               return ((i >> 2) << 2);

Why does the comment has one expression and the code another? I know they give the same result, but this is pretty useless.

Quoted 44 lines

drivers/irqchip/irq-gic.c +16 -9

+       u32 mask;
+       /* ARM GIC, nr_cpu_if == 8; HiP04 GIC, nr_cpu_if == 16 */
+       mask = (1 << nr_cpu_if) - 1;
+       return (mask << irq_to_core_shift(i, nr_cpu_if));
+}
+
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-       unsigned int shift = (gic_irq(d) % 4) * 8;
+       void __iomem *reg;
+       unsigned int i = gic_irq(d);
+       unsigned int shift = irq_to_core_shift(i, gic_data[0].nr_cpu_if);
        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
        u32 val, mask, bit;
-
-       if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
+       if (cpu >= gic_data[0].nr_cpu_if || cpu >= nr_cpu_ids)
                return -EINVAL;
 
+       reg = gic_dist_base(d) + GIC_DIST_TARGET +
+             irq_to_core_offset(i, gic_data[0].nr_cpu_if);
+
        raw_spin_lock(&irq_controller_lock);
-       mask = 0xff << shift;
+       mask = irq_to_core_mask(i, gic_data[0].nr_cpu_if);
        bit = gic_cpu_map[cpu] << shift;
        val = readl_relaxed(reg) & ~mask;
        writel_relaxed(val | bit, reg);

@@ -354,15 +392,16 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
-static u8 gic_get_cpumask(struct gic_chip_data *gic)
+static u16 gic_get_cpumask(struct gic_chip_data *gic)
 {
        void __iomem *base = gic_data_dist_base(gic);
-       u32 mask, i;
+       u32 mask, i, j, nr_if = gic->nr_if_per_reg;
 
-       for (i = mask = 0; i < 32; i += 4) {
-               mask = readl_relaxed(base + GIC_DIST_TARGET + i);

drivers/irqchip/irq-gic.c void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) · line 407

Quoted 10 lines

drivers/irqchip/irq-gic.c +5 -2

-               mask |= mask >> 16;
-               mask |= mask >> 8;
+       /* get the number of CPU fields in GIC_DIST_TARGET register */
+       for (i = mask = 0; i < DIV_ROUND_UP(32, nr_if); i++) {
+               mask = readl_relaxed(base + GIC_DIST_TARGET + i * 4);
+               for (j = GIC_REG_BITS >> 1; j >= gic->nr_cpu_if; j >>= 1)
+                       mask |= mask >> j;
                if (mask)
                        break;
        }

This looks incredibly convoluted. How about something like the code below, which is way simpler and doesn't involve changing so much stuff (completely untested, of course):

int nr_target_regs = 32 / (gic->nr_cpu_if == 8 ? 4 : 2);

for (i = mask = 0; i < nr_target_regs; i++) {
        mask = readl_relaxed(base + GIC_DIST_TARGET + i * 4);
        mask |= mask >> 16;
        if (gic->nr_cpu_if == 8)
                mask |= mask >> 8;

        if (mask)
                break;
}

Quoted 20 lines

drivers/irqchip/irq-gic.c +5 -1

@@ -370,12 +409,16 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
        if (!mask)
                pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 
+       /* ARM GIC needs 8-bit cpu mask, HiP04 GIC needs 16-bit cpu mask. */
+       if (gic->nr_cpu_if == 8)
+               mask &= 0xff;
+
        return mask;
 }
 
 static void __init gic_dist_init(struct gic_chip_data *gic)
 {
-       unsigned int i;
+       unsigned int i, nr_if = gic->nr_if_per_reg;
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        void __iomem *base = gic_data_dist_base(gic);

drivers/irqchip/irq-gic.c static void __init gic_dist_init(struct gic_chip_data *gic) · line 439

Quoted 9 lines

drivers/irqchip/irq-gic.c +2 -4

@@ -392,23 +435,25 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         * Set all global interrupts to this CPU only.
         */
        cpumask = gic_get_cpumask(gic);
-       cpumask |= cpumask << 8;
-       cpumask |= cpumask << 16;
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+       for (i = gic->nr_cpu_if; i < GIC_REG_BITS; i <<= 1)
+               cpumask |= cpumask << i;

Really, you should stop adding bit arithmetics all over the place. You're just making a simple problem way too complex. What is wrong with:

        if (gic->nr_cpu_if == 8)
                cpumask |= cpumask << 8;

?

drivers/irqchip/irq-gic.c static void __init gic_dist_init(struct gic_chip_data *gic) · line 441

Quoted 3 lines

drivers/irqchip/irq-gic.c +2 -0

+       for (i = 32 / nr_if; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
+               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4);

Why do you need to DIV_ROUND_UP? GIC interrupts are always a multiple of 32.

Quoted 5 lines

drivers/irqchip/irq-gic.c +0 -2

        /*
         * Set priority on all global interrupts.
         */
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);

drivers/irqchip/irq-gic.c static void __init gic_dist_init(struct gic_chip_data *gic) · line 453

Quoted 10 lines

drivers/irqchip/irq-gic.c +3 -2

+       for (i = 32 / nr_if; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+               writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4);
 
        /*
         * Disable all interrupts.  Leave the PPI and SGIs alone
         * as these enables are banked registers.
         */
-       for (i = 32; i < gic_irqs; i += 32)
-               writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+       i = 32 / GIC_REG_BITS;

I predict this value to be the grand total of one.

Quoted 75 lines

drivers/irqchip/irq-gic.c +11 -8

+       for (; i < DIV_ROUND_UP(gic_irqs, GIC_REG_BITS); i++)
+               writel_relaxed(0xffffffff,
+                              base + GIC_DIST_ENABLE_CLEAR + i * 4);
 
        writel_relaxed(1, base + GIC_DIST_CTRL);
 }

@@ -423,7 +468,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Get what the GIC says our CPU mask is.
         */
-       BUG_ON(cpu >= NR_GIC_CPU_IF);
+       BUG_ON(cpu >= gic->nr_cpu_if);
        cpu_mask = gic_get_cpumask(gic);
        gic_cpu_map[cpu] = cpu_mask;
 

@@ -431,7 +476,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
         * Clear our mask from the other map entries in case they're
         * still undefined.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
+       for (i = 0; i < gic->nr_cpu_if; i++)
                if (i != cpu)
                        gic_cpu_map[i] &= ~cpu_mask;
 

@@ -445,8 +490,8 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Set priority on PPI and SGI interrupts
         */
-       for (i = 0; i < 32; i += 4)
-               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+       for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
+               writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
 
        writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
        writel_relaxed(1, base + GIC_CPU_CTRL);

@@ -467,7 +512,7 @@ void gic_cpu_if_down(void)
  */
 static void gic_dist_save(unsigned int gic_nr)
 {
-       unsigned int gic_irqs;
+       unsigned int gic_irqs, nr_if = gic_data[gic_nr].nr_if_per_reg;
        void __iomem *dist_base;
        int i;
 

@@ -484,7 +529,7 @@ static void gic_dist_save(unsigned int gic_nr)
                gic_data[gic_nr].saved_spi_conf[i] =
                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                gic_data[gic_nr].saved_spi_target[i] =
                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -502,7 +547,7 @@ static void gic_dist_save(unsigned int gic_nr)
  */
 static void gic_dist_restore(unsigned int gic_nr)
 {
-       unsigned int gic_irqs;
+       unsigned int gic_irqs, nr_if = gic_data[gic_nr].nr_if_per_reg;
        unsigned int i;
        void __iomem *dist_base;
 

@@ -525,7 +570,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                writel_relaxed(0xa0a0a0a0,
                        dist_base + GIC_DIST_PRI + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
                        dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -665,9 +710,15 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
         */
        dmb(ishst);
 

drivers/irqchip/irq-gic.c static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) · line 721

Quoted 12 lines

drivers/irqchip/irq-gic.c +9 -3

-       /* this always happens on GIC0 */
-       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
-
+       /*
+        * CPUTargetList -- bit[23:16] in GIC_DIST_SOFTINT in ARM GIC.
+        *                  bit[23:8] in HIP04_GIC_DIST_SOFTINT in HiP04 GIC.
+        * NSATT -- bit[15] in GIC_DIST_SOFTINT in ARM GIC.
+        *          bit[7] in HIP04_GIC_DIST_SOFTINT in HiP04 GIC.
+        * this always happens on GIC0
+        */
+       writel_relaxed(map << (16 + 8 - gic_data[0].nr_cpu_if) | irq,
+                      gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

Make this two cases. This bit arithmetic makes it unreadable. Also, why does the comment makes the GIC_DIST_SOFTINT/HIP04_GIC_DIST_SOFTINT distinction, while the code only refers to GIC_DIST_SOFTINT?

Quoted 5 lines

drivers/irqchip/irq-gic.c +0 -0

        raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 #endif

drivers/irqchip/irq-gic.c static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) · line 739

Quoted 10 lines

drivers/irqchip/irq-gic.c +3 -2

@@ -681,10 +732,11 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
  */
 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 {
-       BUG_ON(cpu_id >= NR_GIC_CPU_IF);
+       BUG_ON(cpu_id >= gic_data[0].nr_cpu_if);
        cpu_id = 1 << cpu_id;
        /* this always happens on GIC0 */
-       writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+       writel_relaxed((cpu_id << (16 + 8 - gic_data[0].nr_cpu_if)) | irq,
+                      gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

Same here.

Quoted 13 lines

drivers/irqchip/irq-gic.c +1 -1

 }
 
 /*

@@ -700,7 +752,7 @@ int gic_get_cpu_id(unsigned int cpu)
 {
        unsigned int cpu_bit;
 
-       if (cpu >= NR_GIC_CPU_IF)
+       if (cpu >= gic_data[0].nr_cpu_if)
                return -1;
        cpu_bit = gic_cpu_map[cpu];
        if (cpu_bit & (cpu_bit - 1))

drivers/irqchip/irq-gic.c void gic_migrate_target(unsigned int new_cpu_id) · line 829

Quoted 9 lines

drivers/irqchip/irq-gic.c +2 -2

@@ -771,10 +823,10 @@ void gic_migrate_target(unsigned int new_cpu_id)
         */
        for (i = 0; i < 16; i += 4) {
                int j;
-               val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
+               val = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i);
                if (!val)
                        continue;
-               writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
+               writel_relaxed(val, dist_base + GIC_DIST_PENDING_CLEAR + i);

What? Hell no. This is the SGI sources we're dealing with. And I'd expect your implementation to be quite different.

Quoted 16 lines

drivers/irqchip/irq-gic.c +1 -1

                for (j = i; j < i + 4; j++) {
                        if (val & 0xff)
                                writel_relaxed((1 << (new_cpu_id + 16)) | j,

@@ -931,7 +983,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
        irq_hw_number_t hwirq_base;
        struct gic_chip_data *gic;
        int gic_irqs, irq_base, i;
-       int nr_routable_irqs;
+       int nr_routable_irqs, max_nr_irq;
 
        BUG_ON(gic_nr >= MAX_GIC_NR);
 

@@ -967,12 +1019,23 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                gic_set_base_accessor(gic, gic_get_common_base);
        }
 

drivers/irqchip/irq-gic.c void __init gic_init_bases(unsigned int gic_nr, int irq_start, · line 1032

Quoted 11 lines

drivers/irqchip/irq-gic.c +11 -0

+       if (of_device_is_compatible(node, "hisilicon,hip04-gic")) {
+               /* HiP04 GIC supports 16 CPUs at most */
+               gic->nr_cpu_if = 16;
+               max_nr_irq = 510;
+       } else {
+               /* ARM/Qualcomm GIC supports 8 CPUs at most */
+               gic->nr_cpu_if = 8;
+               max_nr_irq = 1020;
+       }
+       gic->nr_if_per_reg = GIC_REG_BITS / gic->nr_cpu_if;
+

Loose this last line, and do the explicit computation. where needed. I don't this this adds anything.

Quoted 30 lines

drivers/irqchip/irq-gic.c +6 -5

        /*
         * Initialize the CPU interface map to all CPUs.
         * It will be refined as each CPU probes its ID.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               gic_cpu_map[i] = 0xff;
+       for (i = 0; i < gic->nr_cpu_if; i++)
+               gic_cpu_map[i] = (1 << gic->nr_cpu_if) - 1;
 
        /*
         * For primary GICs, skip over SGIs.

@@ -988,12 +1051,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 
        /*
         * Find out how many interrupts are supported.
-        * The GIC only supports up to 1020 interrupt sources.
+        * The ARM/Qualcomm GIC only supports up to 1020 interrupt sources.
+        * The HiP04 GIC only supports up to 510 interrupt sources.
         */
        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
-       if (gic_irqs > 1020)
-               gic_irqs = 1020;
+       if (gic_irqs > max_nr_irq)
+               gic_irqs = max_nr_irq;
        gic->gic_irqs = gic_irqs;
 
        gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */

drivers/irqchip/irq-gic.c gic_of_init(struct device_node *node, struct device_node *parent) · line 1138

Quoted 6 lines

drivers/irqchip/irq-gic.c +1 -0

@@ -1069,6 +1133,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 }
 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+IRQCHIP_DECLARE(hip04_gic, "hisilicon,hip04-gic", gic_of_init);
 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);

Overall, there is still some work required to make this patch acceptable. The whole change could be much simpler and less controvertial if you didn't obfuscate the handling of the 16 CPU-IF case with so much bit arithmetic. Most of this code is on a slow path anyway, so you're not even optimizing anything that would be performance critical.

Cheers,

        M.

--
Jazz is not dead. It just smells funny.

Since 16 Cortex-A15 cores are used in HiP04 SoC, enlarge the maximum clusters from 2 to 4 if HiP04 SoC is built without CONFIG_BIG_LITTLE.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig            | 8 ++++++++
 arch/arm/include/asm/mcpm.h | 5 +++++
 2 files changed, 13 insertions(+)

arch/arm/Kconfig +0 -0

index 9a2214e..f2a25be 100644

arch/arm/Kconfig +0 -0

 config BIG_LITTLE
 	bool "big.LITTLE support (Experimental)"
 	depends on CPU_V7 && SMP

arch/arm/include/asm/mcpm.h +5 -0

index 608516e..fc8d70d 100644
@@ -20,7 +20,12 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER	4
+
+#ifdef CONFIG_MCPM_QUAD_CLUSTER
+#define MAX_NR_CLUSTERS		4
+#else
 #define MAX_NR_CLUSTERS		2
+#endif
 
 #ifndef __ASSEMBLY__
 

Signature · 1 line

1.8.3.2

Hisilicon Hi3xxx is based on Cortex A9 Core. Now HiP04 SoC is based on Cortex A15 Core. Since multiple clusters is used in HiP04 SoC, it could be based on MCPM.

And HiP04 supports LPAE to support large memory.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               |   2 +-
 arch/arm/mach-hisi/Kconfig     |   9 +-
 arch/arm/mach-hisi/Makefile    |   1 +
 arch/arm/mach-hisi/core.h      |   2 +
 arch/arm/mach-hisi/hisilicon.c |  12 ++
 arch/arm/mach-hisi/platmcpm.c  | 334 +++++++++++++++++++++++++++++++++++++++++
 6 files changed, 358 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-hisi/platmcpm.c

arch/arm/Kconfig +1 -1

index f2a25be..2961627 100644
@@ -1113,7 +1113,7 @@ source arch/arm/mm/Kconfig
 
 config ARM_NR_BANKS
 	int
-	default 16 if ARCH_EP93XX
+	default 16 if ARCH_EP93XX || ARCH_HIP04
 	default 8
 
 config IWMMXT

arch/arm/mach-hisi/Kconfig +0 -0

index da16efd..0bfd739 100644

arch/arm/mach-hisi/Kconfig +2 -0

+	help
+	  Support for Hisilicon HiP04 SoC family
 
 endmenu
 

arch/arm/mach-hisi/platmcpm.c new file +98 -0

new file mode 100644
index 0000000..4ac8d4b
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2013-2014 Linaro Ltd.
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "core.h"
+
+/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
+ * 1 -- unreset; 0 -- reset
+ */
+#define CORE_RESET_BIT(x)		(1 << x)
+#define NEON_RESET_BIT(x)		(1 << (x + 4))
+#define CORE_DEBUG_RESET_BIT(x)		(1 << (x + 9))
+#define CLUSTER_L2_RESET_BIT		(1 << 8)
+#define CLUSTER_DEBUG_RESET_BIT		(1 << 13)
+
+/*
+ * bits definition in SC_CPU_RESET_STATUS[x]
+ * 1 -- reset status; 0 -- unreset status
+ */
+#define CORE_RESET_STATUS(x)		(1 << x)
+#define NEON_RESET_STATUS(x)		(1 << (x + 4))
+#define CORE_DEBUG_RESET_STATUS(x)	(1 << (x + 9))
+#define CLUSTER_L2_RESET_STATUS		(1 << 8)
+#define CLUSTER_DEBUG_RESET_STATUS	(1 << 13)
+#define CORE_WFI_STATUS(x)		(1 << (x + 16))
+#define CORE_WFE_STATUS(x)		(1 << (x + 20))
+#define CORE_DEBUG_ACK(x)		(1 << (x + 24))
+
+#define SC_CPU_RESET_REQ(x)		(0x520 + (x << 3))	/* reset */
+#define SC_CPU_RESET_DREQ(x)		(0x524 + (x << 3))	/* unreset */
+#define SC_CPU_RESET_STATUS(x)		(0x1520 + (x << 3))
+
+#define FAB_SF_MODE			0x0c
+#define FAB_SF_INVLD			0x10
+
+/* bits definition in FB_SF_INVLD */
+#define FB_SF_INVLD_START		(1 << 8)
+
+#define HIP04_MAX_CLUSTERS		4
+#define HIP04_MAX_CPUS_PER_CLUSTER	4
+
+#define POLL_MSEC	10
+#define TIMEOUT_MSEC	1000
+
+struct hip04_secondary_cpu_data {
+	u32	bootwrapper_phys;
+	u32	bootwrapper_size;
+	u32	bootwrapper_magic;
+	u32	relocation_entry;
+	u32	relocation_size;
+};
+
+static void __iomem *relocation, *sysctrl, *fabric;
+static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
+static DEFINE_SPINLOCK(boot_lock);
+static struct hip04_secondary_cpu_data hip04_boot;
+
+static bool hip04_cluster_down(unsigned int cluster)
+{
+	int i;
+
+	for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
+		if (hip04_cpu_table[cluster][i])
+			return false;
+	return true;
+}
+
+static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
+{
+	unsigned long data;
+
+	if (!fabric)
+		return;
+	data = readl_relaxed(fabric + FAB_SF_MODE);
+	if (on)
+		data |= 1 << cluster;
+	else
+		data &= ~(1 << cluster);
+	writel_relaxed(data, fabric + FAB_SF_MODE);
+	while (1) {
+		if (data == readl_relaxed(fabric + FAB_SF_MODE))
+			break;
+	}
+}
+

arch/arm/mach-hisi/platmcpm.c new file +12 -0

+	writel_relaxed(hip04_boot.bootwrapper_phys, relocation);
+	writel_relaxed(hip04_boot.bootwrapper_magic, relocation + 4);
+	writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);
+	writel_relaxed(0, relocation + 12);
+
+	if (hip04_cluster_down(cluster)) {
+		data = CLUSTER_L2_RESET_BIT | CLUSTER_DEBUG_RESET_BIT;
+		writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+		do {
+			mask = CLUSTER_L2_RESET_STATUS | \
+			       CLUSTER_DEBUG_RESET_STATUS;
+			data = readl_relaxed(sysctrl + \

arch/arm/mach-hisi/platmcpm.c new file +11 -0

+	return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	unsigned int v;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+	spin_unlock(&boot_lock);
+
+	asm volatile(
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C)
+	  :);
+

arch/arm/mach-hisi/platmcpm.c new file +11 -0

+	return;
+out:
+	spin_unlock(&boot_lock);
+}
+
+static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int data, tries;
+
+	BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
+	       cpu >= HIP04_MAX_CPUS_PER_CLUSTER);

arch/arm/mach-hisi/platmcpm.c new file +131 -0

+		return 0;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static void hip04_mcpm_powered_up(void)
+{
+	if (!relocation)
+		return;
+	spin_lock(&boot_lock);
+	writel_relaxed(0, relocation);
+	writel_relaxed(0, relocation + 4);
+	writel_relaxed(0, relocation + 8);
+	writel_relaxed(0, relocation + 12);
+	spin_unlock(&boot_lock);
+}
+
+static const struct mcpm_platform_ops hip04_mcpm_ops = {
+	.power_up		= hip04_mcpm_power_up,
+	.power_down		= hip04_mcpm_power_down,
+	.wait_for_powerdown	= hip04_mcpm_wait_for_powerdown,
+	.powered_up		= hip04_mcpm_powered_up,
+};
+
+static bool __init hip04_cpu_table_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	if (cluster >= HIP04_MAX_CLUSTERS ||
+	    cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
+		pr_err("%s: boot CPU is out of bound!\n", __func__);
+		return false;
+	}
+	hip04_set_snoop_filter(cluster, 1);
+	hip04_cpu_table[cluster][cpu] = 1;
+	return true;
+}
+
+static int __init hip04_mcpm_init(void)
+{
+	struct device_node *np, *np_fab;
+	int ret = -ENODEV;
+
+	np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+	if (!np)
+		goto err;
+	np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
+	if (!np_fab)
+		goto err;
+
+	if (of_property_read_u32(np, "bootwrapper-phys",
+				 &hip04_boot.bootwrapper_phys)) {
+		pr_err("failed to get bootwrapper-phys\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "bootwrapper-size",
+				 &hip04_boot.bootwrapper_size)) {
+		pr_err("failed to get bootwrapper-size\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "bootwrapper-magic",
+				 &hip04_boot.bootwrapper_magic)) {
+		pr_err("failed to get bootwrapper-magic\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "relocation-entry",
+				 &hip04_boot.relocation_entry)) {
+		pr_err("failed to get relocation-entry\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "relocation-size",
+				 &hip04_boot.relocation_size)) {
+		pr_err("failed to get relocation-size\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	relocation = ioremap(hip04_boot.relocation_entry,
+			     hip04_boot.relocation_size);
+	if (!relocation) {
+		pr_err("failed to map relocation space\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	sysctrl = of_iomap(np, 0);
+	if (!sysctrl) {
+		pr_err("failed to get sysctrl base\n");
+		ret = -ENOMEM;
+		goto err_sysctrl;
+	}
+	fabric = of_iomap(np_fab, 0);
+	if (!fabric) {
+		pr_err("failed to get fabric base\n");
+		ret = -ENOMEM;
+		goto err_fabric;
+	}
+
+	memblock_reserve(hip04_boot.bootwrapper_phys,
+			 hip04_boot.bootwrapper_size);
+
+	if (!hip04_cpu_table_init())
+		return -EINVAL;
+	ret = mcpm_platform_register(&hip04_mcpm_ops);
+	if (!ret) {
+		mcpm_sync_init(NULL);
+		pr_info("HiP04 MCPM initialized\n");
+	}
+	return ret;
+err_fabric:
+	iounmap(sysctrl);
+err_sysctrl:
+	iounmap(relocation);
+err:
+	return ret;
+}
+early_initcall(hip04_mcpm_init);
+
+bool __init hip04_smp_init_ops(void)
+{
+	mcpm_smp_set_ops();
+	return true;
+}

Signature · 1 line

1.8.3.2

arch/arm/mach-hisi/platmcpm.c line 130

Quoted 4 lines · Haojian Zhuang

arch/arm/mach-hisi/platmcpm.c new file +4 -0

+
+     data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+            CORE_DEBUG_RESET_BIT(cpu);
+     writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));

It might be a good idea to reset and initialize things only if hip04_cpu_table[cluster][cpu] was zero initially. Please see the comment in mcpm_cpu_power_down() discussing concurrent up/down operations, and the way races are handled using dcscb_use_count in dcscb_power_up() / dcscb_power_down() for example.

Review

Quoted 2 lines

(quoted diff) +2 -0

+     spin_unlock(&boot_lock);
+     msleep(POLL_MSEC);

You don't have to wait here. The MCPM up method should set things for the CPU to come up eventually and that CPU to signal itself when it is finally online.

Quoted 11 lines

arch/arm/mach-hisi/platmcpm.c new file +11 -0

+     return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+     unsigned int mpidr, cpu, cluster;
+     unsigned int v;
+
+     mpidr = read_cpuid_mpidr();
+     cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+     cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);

arch/arm/mach-hisi/platmcpm.c line 154

Quoted 10 lines

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+
+     spin_lock(&boot_lock);
+     BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+     __mcpm_cpu_going_down(cpu, cluster);
+
+     hip04_cpu_table[cluster][cpu]--;
+     if (hip04_cpu_table[cluster][cpu]) {
+             pr_err("Cluster %d CPU%d is still running\n", cluster, cpu);
+             goto out;
+     }

This is wrong. Please see dcscb_power_down() or tc2_pm_down() for examples of how to deal with this situation.

Quoted 1 line

+ __mcpm_cpu_down(cpu, cluster);

That call should happen last i.e. after coherency has been disabled and the CPU is about to call WFI. Again, see the TC2 implementation for example. You may also read Documentation/arm/cluster-pm-race-avoidance.txt for more details about those calls and the algorithm behind them.

Quoted 10 lines

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+     spin_unlock(&boot_lock);
+
+     asm volatile(
+     "       mrc     p15, 0, %0, c1, c0, 0\n"
+     "       bic     %0, %0, %1\n"
+     "       mcr     p15, 0, %0, c1, c0, 0\n"
+       : "=&r" (v)
+       : "Ir" (CR_C)
+       :);
+

arch/arm/mach-hisi/platmcpm.c line 176

Quoted 10 lines

arch/arm/mach-hisi/platmcpm.c new file +10 -0

+     flush_cache_louis();
+
+     asm volatile(
+     /* Turn off coherency, disable SMP bit in ACTLR */
+     "       mrc     p15, 0, %0, c1, c0, 1\n"
+     "       bic     %0, %0, %1\n"
+     "       mcr     p15, 0, %0, c1, c0, 1\n"
+     : "=&r" (v)
+     : "Ir" (0x40)
+     :);

The above code is not safe.

You should use v7_exit_coherency_flush() instead.

arch/arm/mach-hisi/platmcpm.c line 182

Quoted 5 lines

arch/arm/mach-hisi/platmcpm.c new file +5 -0

+     isb();
+     dsb();
+
+     while (true)
+             wfi();

This is wrong. By the time execution gets here, it is well possible that another CPU decided that this CPU should not be down anymore, in which case wfi() will return. See what's expected in this case by looking at mcpm_cpu_power_down() and what other backend implementations do.

Quoted 15 lines

arch/arm/mach-hisi/platmcpm.c new file +15 -0

+     return;
+out:
+     spin_unlock(&boot_lock);
+}
+
+static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+     unsigned int data, tries;
+
+     BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
+            cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
+
+     for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; tries++) {
+             data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+             if (!(data & CORE_WFI_STATUS(cpu))) {

arch/arm/mach-hisi/platmcpm.c line 203

Quoted 6 lines

arch/arm/mach-hisi/platmcpm.c new file +6 -0

+                     msleep(POLL_MSEC);
+                     continue;
+             }
+             data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+                    CORE_DEBUG_RESET_BIT(cpu);
+             writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));

Why are you resetting those here?

In HiP04 SoC, the address of GICH_APR & GICH_LR0 registers are different from ARM standard SoC. So add the support of HiP04 SoC in VGIC.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/kvm/interrupts_head.S  | 23 +++++++++++++++++++----
 include/linux/irqchip/arm-gic.h |  3 +++
 virt/kvm/arm/vgic.c             | 10 ++++++++--
 3 files changed, 30 insertions(+), 6 deletions(-)

arch/arm/kvm/interrupts_head.S +8 -3

index 76af9302..13e4144 100644
@@ -419,7 +419,9 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 	ldr	r7, [r2, #GICH_EISR1]
 	ldr	r8, [r2, #GICH_ELRSR0]
 	ldr	r9, [r2, #GICH_ELRSR1]
-	ldr	r10, [r2, #GICH_APR]
+	ldr	r10, =gich_apr
+	ldr	r10, [r10]
+	ldr	r10, [r2, r10]
 
 	str	r3, [r11, #VGIC_CPU_HCR]
 	str	r4, [r11, #VGIC_CPU_VMCR]

@@ -435,7 +437,9 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 	str	r5, [r2, #GICH_HCR]
 
 	/* Save list registers */
-	add	r2, r2, #GICH_LR0
+	ldr	r10, =gich_lr0
+	ldr	r10, [r10]
+	add	r2, r2, r10
 	add	r3, r11, #VGIC_CPU_LR
 	ldr	r4, [r11, #VGIC_CPU_NR_LR]
 1:	ldr	r6, [r2], #4

@@ -469,10 +473,14 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 
 	str	r3, [r2, #GICH_HCR]
 	str	r4, [r2, #GICH_VMCR]
-	str	r8, [r2, #GICH_APR]
+	ldr	r6, =gich_apr
+	ldr	r6, [r6]

arch/arm/kvm/interrupts_head.S +7 -0

@@ -618,3 +626,10 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 .macro load_vcpu
 	mrc	p15, 4, vcpu, c13, c0, 2	@ HTPIDR
 .endm
+
+	.global gich_apr
+gich_apr:
+	.long	GICH_APR
+	.global gich_lr0
+gich_lr0:
+	.long	GICH_LR0

include/linux/irqchip/arm-gic.h +3 -0

index 55933aa..653525b 100644
@@ -49,6 +49,8 @@
 #define GICH_ELRSR1 			0x34
 #define GICH_APR			0xf0
 #define GICH_LR0			0x100
+#define HIP04_GICH_APR			0x70
+#define HIP04_GICH_LR0			0x80
 
 #define GICH_HCR_EN			(1 << 0)
 #define GICH_HCR_UIE			(1 << 1)

@@ -78,6 +80,7 @@
 struct device_node;
 
 extern struct irq_chip gic_arch_extn;
+extern unsigned int gich_apr, gich_lr0;
 
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
 		    u32 offset, struct device_node *);

virt/kvm/arm/vgic.c +0 -0

index 47b2983..010e491 100644
@@ -1478,8 +1478,14 @@ int kvm_vgic_hyp_init(void)
 
 	vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
 	if (!vgic_node) {

Quoted 2 lines · Haojian Zhuang

In HiP04 SoC, the address of GICH_APR & GICH_LR0 registers are different from ARM standard SoC. So add the support of HiP04 SoC in VGIC.

Please explain the differences in the commit message.

Quoted 40 lines

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/kvm/interrupts_head.S  | 23 +++++++++++++++++++----
 include/linux/irqchip/arm-gic.h |  3 +++
 virt/kvm/arm/vgic.c             | 10 ++++++++--
 3 files changed, 30 insertions(+), 6 deletions(-)

arch/arm/kvm/interrupts_head.S +8 -3

index 76af9302..13e4144 100644
@@ -419,7 +419,9 @@ vcpu      .req    r0              @ vcpu pointer always in r0
      ldr     r7, [r2, #GICH_EISR1]
      ldr     r8, [r2, #GICH_ELRSR0]
      ldr     r9, [r2, #GICH_ELRSR1]
-     ldr     r10, [r2, #GICH_APR]
+     ldr     r10, =gich_apr
+     ldr     r10, [r10]
+     ldr     r10, [r2, r10]
 
      str     r3, [r11, #VGIC_CPU_HCR]
      str     r4, [r11, #VGIC_CPU_VMCR]

@@ -435,7 +437,9 @@ vcpu      .req    r0              @ vcpu pointer always in r0
      str     r5, [r2, #GICH_HCR]
 
      /* Save list registers */
-     add     r2, r2, #GICH_LR0
+     ldr     r10, =gich_lr0
+     ldr     r10, [r10]
+     add     r2, r2, r10
      add     r3, r11, #VGIC_CPU_LR
      ldr     r4, [r11, #VGIC_CPU_NR_LR]
 1:   ldr     r6, [r2], #4

@@ -469,10 +473,14 @@ vcpu    .req    r0              @ vcpu pointer always in r0
 
      str     r3, [r2, #GICH_HCR]
      str     r4, [r2, #GICH_VMCR]
-     str     r8, [r2, #GICH_APR]
+     ldr     r6, =gich_apr
+     ldr     r6, [r6]

arch/arm/kvm/interrupts_head.S vcpu .req r0 @ vcpu pointer always in r0 · line 486

Quoted 10 lines

arch/arm/kvm/interrupts_head.S +4 -1

+     str     r8, [r2, r6]
 
      /* Restore list registers */
-     add     r2, r2, #GICH_LR0
+     ldr     r6, =gich_lr0
+     ldr     r6, [r6]
+     add     r2, r2, r6
      add     r3, r11, #VGIC_CPU_LR
      ldr     r4, [r11, #VGIC_CPU_NR_LR]
 1:   ldr     r6, [r3], #4

So we get four extra memory accesses per world switch, just to find out about the new fancy memory map. Let's just say that I'm not exactly pleased.

How about encoding that in the field containing the number of LRs? the distance between GICH_APR and GICH_LR0 is constant (0x10), so we only need to encode the offset of GICH_APR. This way, we only have to read one single word from memory. Not pretty, but I'm not really willing to impact

Quoted 39 lines

arch/arm/kvm/interrupts_head.S +7 -0

@@ -618,3 +626,10 @@ vcpu     .req    r0              @ vcpu pointer always in r0
 .macro load_vcpu
      mrc     p15, 4, vcpu, c13, c0, 2        @ HTPIDR
 .endm
+
+     .global gich_apr
+gich_apr:
+     .long   GICH_APR
+     .global gich_lr0
+gich_lr0:
+     .long   GICH_LR0

include/linux/irqchip/arm-gic.h +3 -0

index 55933aa..653525b 100644
@@ -49,6 +49,8 @@
 #define GICH_ELRSR1                  0x34
 #define GICH_APR                     0xf0
 #define GICH_LR0                     0x100
+#define HIP04_GICH_APR                       0x70
+#define HIP04_GICH_LR0                       0x80
 
 #define GICH_HCR_EN                  (1 << 0)
 #define GICH_HCR_UIE                 (1 << 1)

@@ -78,6 +80,7 @@
 struct device_node;
 
 extern struct irq_chip gic_arch_extn;
+extern unsigned int gich_apr, gich_lr0;
 
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
                  u32 offset, struct device_node *);

virt/kvm/arm/vgic.c +0 -0

index 47b2983..010e491 100644
@@ -1478,8 +1478,14 @@ int kvm_vgic_hyp_init(void)
 

virt/kvm/arm/vgic.c int kvm_vgic_hyp_init(void) · line 1488

Quoted 12 lines

virt/kvm/arm/vgic.c +8 -2

      vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
      if (!vgic_node) {
-             kvm_err("error: no compatible vgic node in DT\n");
-             return -ENODEV;
+             vgic_node = of_find_compatible_node(NULL, NULL,
+                                                 "hisilicon,hip04-gic");
+             if (!vgic_node) {
+                     kvm_err("error: no compatible vgic node in DT\n");
+                     return -ENODEV;
+             }
+             gich_apr = HIP04_GICH_APR;
+             gich_lr0 = HIP04_GICH_LR0;

Consider using of_find_matching_node_and_match instead, with a set of flags for this particular case.