gpio/omap: driver cleanup and fixes
Subsystems (7)
v9 cover gpio/omap: driver cleanup and fixes
This series is continuation of cleanup of OMAP GPIO driver and fixes. The cleanup include getting rid of cpu_is_* checks wherever possible, use of gpio_bank list instead of static array, use of unique platform specific value associated data member to OMAP platforms to avoid cpu_is_* checks. The series also include PM runtime support.
Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Branch: master
Commit: 4962516 (3.2-rc7)
Power Tests
a) OMAP3430SDP
- Modify board-3430sdp.c file to have multiple GPIO modules active with debounce timeout enabled.
- Enable CPU-Idle
- Enable UART timeouts
- Enable offmode
- echo mem > /sys/power/state
- Verify retention and offmode count increment
b) ZOOM3
- Enable CPU-Idle
- Enable UART timeout
- echo mem > /sys/power/state
- Wakeup system using serial keyboard
- Verify retention count increment
Functional Tests
- Done on OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430
Bootup Test
- Done on OMAP1710
v9:
- Summary of Comments/Issues fixed
* GPIO wakeup does not work
* Call debounce clock enable/disable functions from PM runtime callbacks. This will avoid calling the functions from multiple places.
* Modify description of following patch to match latest changes. gpio/omap: save and restore debounce registers.
* Use (bank->regs->set_dataout && bank->regs->clr_dataout) together instead of using only one of them.
* Remove cpu_is_omapxxxx() checks from set_gpio_trigger().
* _gpio_dbck_enable() in runtime callback triggered from omap_gpio_request does not enable dbck because dbck_enable_mask is not set at this point.
* Workaround associated with an errata got missed in v8. This has been included.
v8:
- Remove PM_CONFIG macro around following assignment. pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
- Once pm_runtime is enabled there is no more need for calling the omap_device_disable_idle_on_suspend(od).
- With pm_runtime, handling of clocks in Suspend is taken care of by powerdomain hooks. So remove usage of *_runtime_put/get* from suspend/resume hooks and Idle path.
- Add handling of debounce clocks along the Suspend and Idle paths.
- Remove [PATCH 04/24] gpio/omap: fix pwrdm_post_transition call sequence from this series. This will be merged as part of power cleanup series.
- Remove [PATCH v7 20/26] gpio/omap: skip operations in runtime callbacks The bank->mod_usage check in this patch is not needed any more because they are now already being taken care in suspend/resume and Idle paths.
- Remove [PATCH v7 26/26] gpio/omap: add dbclk aliases for all gpio modules This is already taken care in hwmod.
- Remove redundant blank line in
[PATCH v7 14/26] gpio/omap: remove unnecessary bit-masking for read access
- if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
- isr &= 0x0000ffff;
if (bank->level_mask)
level_mask = bank->level_mask & enabled;v7:
- Use pm_runtime_put() instead of pm_runtime_put_sync_suspend()
- Keep *_runtime_get/put*() outside spinlock
- Remove additional checking of conditions in _restore_context() From:
if (bank->regs->set_dataout && bank->regs->clear_dataout)
...
To:
if (bank->regs->set_dataout)
...
- Use SET_RUNTIME_PM_OPS and SET_SYSTEM_SLEEP_PM_OPS macros
- In [PATCH 19/25] gpio/omap: cleanup prepare_for_idle and resume_after_idle, protect the bank data elements and register access using spinlock in runtime_suspend/resume() callbacks.
This is because these callbacks run with interrupts enabled.
- Add dbclk aliases for all GPIO modules. Without this, GPIO modules were not getting the correct clock handle to enable/disable debounec clock.
- Fix log comments on the following patches:
[PATCH 19/25] gpio/omap: cleanup prepare_for_idle and resume_after_idle [PATCH 20/25] gpio/omap: skip operations in runtime callbacks [PATCH 24/25] gpio/omap: restore OE only after setting the output level
v6:
- Save and restore debounce registers for proper driver operation.
- Restore interrupt enable after all configuration to avoid spurious interrupts.
- Restore dataout register before oe register.
- Restore dataout into dataout_set or dataout based upon the OMAP version.
- Change register name from wkup_status to wkup_en.
- Remove wrapper around omap_pm_get_dev_context_loss_count(). Use it directly. Also, changed the signature of get_context_loss_count in pdata and bank structure from int to u32.
- Use 'context' instead of 'ctx' for clarity wherever it is used.
- Merged two patches into one which are related to bank_is_mpuio() modification.
- Use shift operator instead of following:
+ .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE / 2,
- Remove redundant check from the following
+ if (bank_is_mpuio(bank)) {
+ if (bank->regs->wkup_status) <--- redundant check
+ mpuio_init(bank);
- Change subject of following patch
[PATCH v5 15/22] gpio/omap: use readl in irq_handler for all access into
[PATCH 14/25] gpio/omap: remove unnecessary bit-masking for read access
- Fix multi-line comments in
[PATCH v5 20/22] gpio/omap: cleanup prepare_for_idle and resume_after_idle
v5:
- Reduce runtime callback overhead when *_get/put_sync() called from probe() and *_gpio_request/free().
- Dynamic context save within functions where context is modified instead of saving all context within a common function.
- Removed call to mpuio_init() from omap_gpio_mod_init(). Both the functions are called once during initialization in *_gpio_probe().
Call to omap_gpio_mod_init() has been removed from omap_gpio_request() on the first access to gpio bank. One time initialization looks sufficient.
- In *_gpio_irq_handler() use *_put_sync_suspend() instead of *_put_sync().
- Removed hardcoding of OMAP16xx sysconfig register value and instead defined an associated constant.
- Removed *_get_sync() call from *_gpio_suspend() and *_put_sync() call from *_gpio_resume(). They got wrongly slipped into the code.
- Removed following redundant zero allocated initialization from mach-omap2/gpio.c
+ pdata->regs->irqctrl = 0; + pdata->regs->edgectrl1 = 0; + pdata->regs->edgectrl2 = 0;
- Removed following redundant code in gpio-omap.c -#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
v4:
- since all accesses to registers are 4-byte aligned, removing special checks and handling of 16 and 32-bit wide bank registers and instead use 32-bit read/write access consistently.
- redundant usage of MOD_REG_BIT has been corrected and replaced with _gpio_rmw().
- omap_gpio_mod_init() function has been simplified further using _gpio_rmw().
- sysconfig register offset specific to omap16xx has been removed along with its usage.
- additional logic to skip from suspend/resume:
if (!bank->regs->wkup_status || !bank->suspend_wakeup)
return 0;
if (!bank->regs->wkup_status || !bank->saved_wakeup)
return 0;
- separated mpuio related changes into a different patch from the patch where wakeup status register related changes are done.
- Incorrect replacement of !cpu_class_is_omap2() in gpio_irq_type() corrected:
+ if (!bank->regs->leveldetect0 &&
+ (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
v3:
- Avoid use of wkup_set and wkup_clear registers. Instead use wkup_status register for all platforms. This is because on OMAP4 it is recommended not to use them.
- Remove duplicate code in omap_gpio_mod_init() for handling the same for 32-bit and 16-bit GPIO bank widths. This is accomplished by having two functions to handle each case while assiging a common function pointer during initialization.
- Remove OMAP16xx specific one time initialization from omap_gpio_mod_init(). Move it inside omap16xx_gpio_init().
- Avoid usage of USHRT_MAX to indicate undefined values. Use 0 instead.
- In omap_gpio_suspend()/resume() functions remove code that checks if the feature is supported. Instead, assign these functions to struct platform_driver's suspend & resume function pointers for those OMAP platforms whcih support this feature.
- Remove 'suspend_support' flag because it is redundant. Instead use wkup_* registers to decode the same information.
- Restore context also when we don't know if the context is lost.
- Make omap_gpio_save_context() and omap_gpio_restore_context() static.
v2:
- Do special handling of non-wakeup GPIOs only on OMAP2420. Avoid this handling on OMAP3430.
- Isolate cleanups and fixes into separate set of patches. Keep the cleanup first followed by the fixes.
- Avoid calling omap_gpio_get_context_loss() directly and instead call it through function pointer in pdata initialized during init.
- workaround_enabled flag is not longer needed and is removed.
- Call pwrdm_post_transition() before calling omap_gpio_resume_after_idle().
- In omap2_gpio_resume_after_idle() do context restore before handling workaround.
- Use PM runtime framework.
- Modify register offset names to : wkup_status, wkup_clear, wkup_set. Also use 'base + offset' for readibility in all relevant places.
- Remove unwanted messages from commit section like TODO, etc.
Charulatha V (8):
gpio/omap: remove dependency on gpio_bank_count gpio/omap: use flag to identify wakeup domain gpio/omap: make gpio_context part of gpio_bank structure gpio/omap: make non-wakeup GPIO part of pdata gpio/omap: avoid cpu checks during module ena/disable gpio/omap: use pinctrl offset instead of macro gpio/omap: remove bank->method & METHOD_* macros gpio/omap: fix bankwidth for OMAP7xx MPUIO
Nishanth Menon (4):
gpio/omap: save and restore debounce registers gpio/omap: enable irq at the end of all configuration in restore gpio/omap: restore OE only after setting the output level gpio/omap: handle set_dataout reg capable IP on restore
Tarun Kanti DebBarma (13):
gpio/omap: handle save/restore context in GPIO driver gpio/omap: further cleanup using wkup_en register gpio/omap: use level/edge detect reg offsets gpio/omap: remove hardcoded offsets in context save/restore gpio/omap: cleanup set_gpio_triggering function gpio/omap: cleanup omap_gpio_mod_init function gpio/omap: remove unnecessary bit-masking for read access gpio/omap: use pm-runtime framework
gpio/omap: optimize suspend and resume functions gpio/omap: cleanup prepare_for_idle and resume_after_idle gpio/omap: fix debounce clock handling
gpio/omap: fix incorrect access of debounce module gpio/omap: remove omap_gpio_save_context overhead
arch/arm/mach-omap1/gpio15xx.c | 7 +- arch/arm/mach-omap1/gpio16xx.c | 47 ++- arch/arm/mach-omap1/gpio7xx.c | 14 +- arch/arm/mach-omap2/gpio.c | 36 +- arch/arm/mach-omap2/pm34xx.c | 14 - arch/arm/plat-omap/include/plat/gpio.h | 29 +- drivers/gpio/gpio-omap.c | 1099 +++++++++++++------------------- 7 files changed, 549 insertions(+), 697 deletions(-)
PATCH v9 1/25 gpio/omap: remove dependency on gpio_bank_count
From: Charulatha V <[email protected]>
The gpio_bank_count is the count of number of GPIO devices in a SoC. Remove this dependency from the driver by using list. Also remove the dependency on array of pointers to gpio_bank struct of all GPIO devices.
--- arch/arm/mach-omap1/gpio15xx.c | 1 - arch/arm/mach-omap1/gpio16xx.c | 2 - arch/arm/mach-omap1/gpio7xx.c | 2 - arch/arm/mach-omap2/gpio.c | 1 - arch/arm/plat-omap/include/plat/gpio.h | 3 - drivers/gpio/gpio-omap.c | 163 ++++++++++++++++---------------- 6 files changed, 80 insertions(+), 92 deletions(-)
arch/arm/mach-omap1/gpio15xx.c +0 -1
@@ -115,7 +115,6 @@ static int __init omap15xx_gpio_init(void)platform_device_register (&omap15xx_mpu_gpio);platform_device_register (&omap15xx_gpio); - gpio_bank_count =2 ;return 0 ; }postcore_initcall (omap15xx_gpio_init);
arch/arm/mach-omap1/gpio16xx.c +0 -2
@@ -221,8 +221,6 @@ static int __init omap16xx_gpio_init(void)for (i =0 ; i <ARRAY_SIZE (omap16xx_gpio_dev); i++)platform_device_register (omap16xx_gpio_dev[i]); - gpio_bank_count =ARRAY_SIZE (omap16xx_gpio_dev); -return 0 ; }postcore_initcall (omap16xx_gpio_init);
arch/arm/mach-omap1/gpio7xx.c +0 -2
@@ -282,8 +282,6 @@ static int __init omap7xx_gpio_init(void)for (i =0 ; i <ARRAY_SIZE (omap7xx_gpio_dev); i++)platform_device_register (omap7xx_gpio_dev[i]); - gpio_bank_count =ARRAY_SIZE (omap7xx_gpio_dev); -return 0 ; }postcore_initcall (omap7xx_gpio_init);
arch/arm/mach-omap2/gpio.c +0 -1
@@ -111,7 +111,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)omap_device_disable_idle_on_suspend (pdev); - gpio_bank_count++;return 0 ; }
arch/arm/plat-omap/include/plat/gpio.h +0 -3
@@ -202,9 +202,6 @@ struct omap_gpio_platform_data {struct omap_gpio_reg_offs *regs; }; -/* TODO: Analyze removing gpio_bank_count usage from driver code */ -extern int gpio_bank_count; -extern void omap2_gpio_prepare_for_idle (int off_mode);extern void omap2_gpio_resume_after_idle (void );extern void omap_set_gpio_debounce (int gpio,int enable);
drivers/gpio/gpio-omap.c +80 -83
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1.7.0.4
PATCH v9 2/25 gpio/omap: use flag to identify wakeup domain
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
In omap3, save/restore context is implemented for GPIO banks 2-6 as GPIO bank1 is in wakeup domain. Instead of identifying bank's power domain by bank id, use 'loses_context' flag which is filled by pwrdm_can_ever_lose_context() during dev_init.
For getting the powerdomain pointer, omap_hwmod_get_pwrdm() is used. omap_device_get_pwrdm() could not be used as the pwrdm information needs to be filled in pdata, whereas omap_device_get_pwrdm() could be used only after omap_device_build() call.
--- arch/arm/mach-omap2/gpio.c | 6 ++++++ arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio-omap.c | 13 ++++++------- 3 files changed, 13 insertions(+), 7 deletions(-)
arch/arm/mach-omap2/gpio.c +6 -0
@@ -24,6 +24,8 @@#include <plat/omap_hwmod.h> #include <plat/omap_device.h> +#include "powerdomain.h" +static int omap2_gpio_dev_init (struct omap_hwmod *oh,void *unused) {struct platform_device *pdev;
@@ -31,6 +33,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)struct omap_gpio_dev_attr *dev_attr;char *name ="omap_gpio" ;int id; +struct powerdomain *pwrdm;/* * extract the device id from name field available in the
@@ -99,6 +102,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)return -EINVAL ; } + pwrdm =omap_hwmod_get_pwrdm (oh); + pdata->loses_context =pwrdm_can_ever_lose_context (pwrdm); + pdev =omap_device_build (name, id -1 , oh, pdata,sizeof (*pdata),NULL ,0 , false);kfree (pdata);
arch/arm/plat-omap/include/plat/gpio.h +1 -0
@@ -198,6 +198,7 @@ struct omap_gpio_platform_data {int bank_width;/* GPIO bank width */ int bank_stride;/* Only needed for omap1 MPUIO */ bool dbck_flag;/* dbck required or not - True for OMAP3&4 */ +bool loses_context;/* whether the bank would ever lose context */ struct omap_gpio_reg_offs *regs; };
drivers/gpio/gpio-omap.c +6 -7
@@ -56,6 +56,7 @@ struct gpio_bank {u32 dbck_enable_mask;struct device *dev;bool dbck_flag; +bool loses_context;int stride;u32 width;u16 id;
@@ -1181,7 +1182,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) bank->dbck_flag = pdata->dbck_flag; bank->stride = pdata->bank_stride; bank->width = pdata->bank_width; - + bank->loses_context = pdata->loses_context; bank->regs = pdata->regs;if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1337,8 +1338,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)u32 l1 =0 , l2 =0 ;int j; -/* TODO: Do not use cpu_is_omap34xx */ -if ((cpu_is_omap34xx ()) && (bank->id ==0 )) +if (!bank->loses_context)continue ;for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++)
@@ -1405,8 +1405,7 @@ void omap2_gpio_resume_after_idle(void)u32 l =0 , gen, gen0, gen1;int j; -/* TODO: Do not use cpu_is_omap34xx */ -if ((cpu_is_omap34xx ()) && (bank->id ==0 )) +if (!bank->loses_context)continue ;for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++)
@@ -1505,7 +1504,7 @@ void omap_gpio_save_context(void)list_for_each_entry (bank, &omap_gpio_list, node) { i++; -if (bank->id ==0 ) +if (!bank->loses_context)continue ; gpio_context[i].irqenable1 =
@@ -1539,7 +1538,7 @@ void omap_gpio_restore_context(void)list_for_each_entry (bank, &omap_gpio_list, node) { i++; -if (bank->id ==0 ) +if (!bank->loses_context)continue ; __raw_writel(gpio_context[i].irqenable1,
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1.7.0.4
PATCH v9 3/25 gpio/omap: make gpio_context part of gpio_bank structure
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
Currently gpio_context array used to save gpio bank's context, is used only for OMAP3 architecture. Move gpio_context as part of gpio_bank structure so that it can be specific to each gpio bank and can be used for any OMAP architecture
--- drivers/gpio/gpio-omap.c | 76 ++++++++++++++++++++------------------------- 1 files changed, 34 insertions(+), 42 deletions(-)
drivers/gpio/gpio-omap.c +34 -42
@@ -30,6 +30,19 @@static LIST_HEAD (omap_gpio_list); +struct gpio_regs { +u32 irqenable1; +u32 irqenable2; +u32 wake_en; +u32 ctrl; +u32 oe; +u32 leveldetect0; +u32 leveldetect1; +u32 risingdetect; +u32 fallingdetect; +u32 dataout; +}; +struct gpio_bank {struct list_head node;unsigned long pbase;
@@ -43,7 +56,7 @@ struct gpio_bank {#endif u32 non_wakeup_gpios;u32 enabled_non_wakeup_gpios; - +struct gpio_regs context;u32 saved_datain;u32 saved_fallingdetect;u32 saved_risingdetect;
@@ -66,23 +79,6 @@ struct gpio_bank {struct omap_gpio_reg_offs *regs; }; -#ifdef CONFIG_ARCH_OMAP3 -struct omap3_gpio_regs { -u32 irqenable1; -u32 irqenable2; -u32 wake_en; -u32 ctrl; -u32 oe; -u32 leveldetect0; -u32 leveldetect1; -u32 risingdetect; -u32 fallingdetect; -u32 dataout; -}; - -static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS ]; -#endif -#define GPIO_INDEX (bank, gpio) (gpio % bank->width)#define GPIO_BIT (bank, gpio) (1 << GPIO_INDEX(bank, gpio))
@@ -1499,33 +1495,31 @@ void omap2_gpio_resume_after_idle(void)void omap_gpio_save_context (void ) {struct gpio_bank *bank; -int i =0 ;list_for_each_entry (bank, &omap_gpio_list, node) { - i++;if (!bank->loses_context)continue ; - gpio_context[i].irqenable1 = + bank->context.irqenable1 =__raw_readl (bank->base +OMAP24XX_GPIO_IRQENABLE1 ); - gpio_context[i].irqenable2 = + bank->context.irqenable2 =__raw_readl (bank->base +OMAP24XX_GPIO_IRQENABLE2 ); - gpio_context[i].wake_en = + bank->context.wake_en =__raw_readl (bank->base +OMAP24XX_GPIO_WAKE_EN ); - gpio_context[i].ctrl = + bank->context.ctrl =__raw_readl (bank->base +OMAP24XX_GPIO_CTRL ); - gpio_context[i].oe = + bank->context.oe =__raw_readl (bank->base +OMAP24XX_GPIO_OE ); - gpio_context[i].leveldetect0 = + bank->context.leveldetect0 =__raw_readl (bank->base +OMAP24XX_GPIO_LEVELDETECT0 ); - gpio_context[i].leveldetect1 = + bank->context.leveldetect1 =__raw_readl (bank->base +OMAP24XX_GPIO_LEVELDETECT1 ); - gpio_context[i].risingdetect = + bank->context.risingdetect =__raw_readl (bank->base +OMAP24XX_GPIO_RISINGDETECT ); - gpio_context[i].fallingdetect = + bank->context.fallingdetect =__raw_readl (bank->base +OMAP24XX_GPIO_FALLINGDETECT ); - gpio_context[i].dataout = + bank->context.dataout =__raw_readl (bank->base +OMAP24XX_GPIO_DATAOUT ); } }
@@ -1533,33 +1527,31 @@ void omap_gpio_save_context(void)void omap_gpio_restore_context (void ) {struct gpio_bank *bank; -int i =0 ;list_for_each_entry (bank, &omap_gpio_list, node) { - i++;if (!bank->loses_context)continue ; -__raw_writel (gpio_context[i].irqenable1, +__raw_writel (bank->context.irqenable1, bank->base +OMAP24XX_GPIO_IRQENABLE1 ); -__raw_writel (gpio_context[i].irqenable2, +__raw_writel (bank->context.irqenable2, bank->base +OMAP24XX_GPIO_IRQENABLE2 ); -__raw_writel (gpio_context[i].wake_en, +__raw_writel (bank->context.wake_en, bank->base +OMAP24XX_GPIO_WAKE_EN ); -__raw_writel (gpio_context[i].ctrl, +__raw_writel (bank->context.ctrl, bank->base +OMAP24XX_GPIO_CTRL ); -__raw_writel (gpio_context[i].oe, +__raw_writel (bank->context.oe, bank->base +OMAP24XX_GPIO_OE ); -__raw_writel (gpio_context[i].leveldetect0, +__raw_writel (bank->context.leveldetect0, bank->base +OMAP24XX_GPIO_LEVELDETECT0 ); -__raw_writel (gpio_context[i].leveldetect1, +__raw_writel (bank->context.leveldetect1, bank->base +OMAP24XX_GPIO_LEVELDETECT1 ); -__raw_writel (gpio_context[i].risingdetect, +__raw_writel (bank->context.risingdetect, bank->base +OMAP24XX_GPIO_RISINGDETECT ); -__raw_writel (gpio_context[i].fallingdetect, +__raw_writel (bank->context.fallingdetect, bank->base +OMAP24XX_GPIO_FALLINGDETECT ); -__raw_writel (gpio_context[i].dataout, +__raw_writel (bank->context.dataout, bank->base +OMAP24XX_GPIO_DATAOUT ); } }
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1.7.0.4
PATCH v9 4/25 gpio/omap: handle save/restore context in GPIO driver
In reply to Tarun Kanti DebBarmaModify omap_gpio_prepare_for_idle() & omap_gpio_resume_after_idle() functions to handle save context & restore context respectively in the OMAP GPIO driver itself instead of calling these functions from pm specific files. For this, in gpio_prepare_for_idle(), call *_get_context_loss_count() and in gpio_resume_after_idle() call it again. If the count is different, do restore context.
--- arch/arm/mach-omap2/gpio.c | 3 +- arch/arm/mach-omap2/pm34xx.c | 14 ---- arch/arm/plat-omap/include/plat/gpio.h | 5 +- drivers/gpio/gpio-omap.c | 131 ++++++++++++++------------------ 4 files changed, 63 insertions(+), 90 deletions(-)
arch/arm/mach-omap2/gpio.c +2 -1
@@ -23,6 +23,7 @@#include <plat/omap_hwmod.h> #include <plat/omap_device.h> +#include <plat/omap-pm.h> #include "powerdomain.h"
@@ -55,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->bank_width = dev_attr->bank_width; pdata->dbck_flag = dev_attr->dbck_flag; pdata->virtual_irq_start =IH_GPIO_BASE +32 * (id -1 ); - + pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; pdata->regs =kzalloc (sizeof (struct omap_gpio_reg_offs ),GFP_KERNEL );if (!pdata) {pr_err ("gpio%d: Memory allocation failed\n" , id);
arch/arm/mach-omap2/pm34xx.c +0 -14
@@ -85,16 +85,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;static struct powerdomain *core_pwrdm, *per_pwrdm;static struct powerdomain *cam_pwrdm; -static inline void omap3_per_save_context (void ) -{ -omap_gpio_save_context (); -} - -static inline void omap3_per_restore_context (void ) -{ -omap_gpio_restore_context (); -} -static void omap3_enable_io_chain (void ) {int timeout =0 ;
@@ -390,8 +380,6 @@ void omap_sram_idle(void)omap_uart_prepare_idle (2 );omap_uart_prepare_idle (3 );omap2_gpio_prepare_for_idle (per_going_off); -if (per_next_state ==PWRDM_POWER_OFF ) -omap3_per_save_context (); }/* CORE */
@@ -461,8 +449,6 @@ void omap_sram_idle(void)if (per_next_state <PWRDM_POWER_ON ) { per_prev_state =pwrdm_read_prev_pwrst (per_pwrdm);omap2_gpio_resume_after_idle (); -if (per_prev_state ==PWRDM_POWER_OFF ) -omap3_per_restore_context ();omap_uart_resume_idle (2 );omap_uart_resume_idle (3 ); }
arch/arm/plat-omap/include/plat/gpio.h +3 -2
@@ -201,14 +201,15 @@ struct omap_gpio_platform_data {bool loses_context;/* whether the bank would ever lose context */ struct omap_gpio_reg_offs *regs; + +/* Return context loss count due to PM states changing */ +int (*get_context_loss_count)(struct device *dev); };extern void omap2_gpio_prepare_for_idle (int off_mode);extern void omap2_gpio_resume_after_idle (void );extern void omap_set_gpio_debounce (int gpio,int enable);extern void omap_set_gpio_debounce_time (int gpio,int enable); -extern void omap_gpio_save_context (void ); -extern void omap_gpio_restore_context (void );/*-------------------------------------------------------------------------*/ /* Wrappers for "new style" GPIO calls, using the new infrastructure
drivers/gpio/gpio-omap.c +58 -73
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1.7.0.4
PATCH v9 5/25 gpio/omap: make non-wakeup GPIO part of pdata
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
Non-wakeup GPIOs are available only in OMAP2. Avoid cpu_is checks by making non_wakeup_gpios as part of pdata.
--- arch/arm/mach-omap2/gpio.c | 8 ++++++++ arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio-omap.c | 8 +------- 3 files changed, 10 insertions(+), 7 deletions(-)
arch/arm/mach-omap2/gpio.c +8 -0
@@ -65,6 +65,14 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)switch (oh->class->rev) {case 0 : +if (id ==1 ) +/* non-wakeup GPIO pins for OMAP2 Bank1 */ + pdata->non_wakeup_gpios =0xe203ffc0 ; +else if (id ==2 ) +/* non-wakeup GPIO pins for OMAP2 Bank2 */ + pdata->non_wakeup_gpios =0x08700040 ; +/* fall through */ +case 1 : pdata->bank_type =METHOD_GPIO_24XX ; pdata->regs->revision =OMAP24XX_GPIO_REVISION ;
arch/arm/plat-omap/include/plat/gpio.h +1 -0
@@ -199,6 +199,7 @@ struct omap_gpio_platform_data {int bank_stride;/* Only needed for omap1 MPUIO */ bool dbck_flag;/* dbck required or not - True for OMAP3&4 */ bool loses_context;/* whether the bank would ever lose context */ +u32 non_wakeup_gpios;struct omap_gpio_reg_offs *regs;
drivers/gpio/gpio-omap.c +1 -7
@@ -1021,13 +1021,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)/* Initialize interface clk ungated, module enabled */ __raw_writel (0 , bank->base +OMAP24XX_GPIO_CTRL ); - }else if (cpu_is_omap24xx ()) { -static const u32 non_wakeup_gpios[] = { -0xe203ffc0 ,0x08700040 - }; -if (bank->id <ARRAY_SIZE (non_wakeup_gpios)) - bank->non_wakeup_gpios = - non_wakeup_gpios[bank->id]; } }else if (cpu_class_is_omap1 ()) {if (bank_is_mpuio (bank)) {
@@ -1180,6 +1173,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) bank->dbck_flag = pdata->dbck_flag; bank->stride = pdata->bank_stride; bank->width = pdata->bank_width; + bank->non_wakeup_gpios = pdata->non_wakeup_gpios; bank->loses_context = pdata->loses_context; bank->get_context_loss_count = pdata->get_context_loss_count; bank->regs = pdata->regs;
Signature · 1 line
1.7.0.4
PATCH v9 6/25 gpio/omap: avoid cpu checks during module ena/disable
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio request/free.
--- arch/arm/mach-omap2/gpio.c | 2 + arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio-omap.c | 53 ++++++++++++++------------------ 3 files changed, 26 insertions(+), 30 deletions(-)
arch/arm/mach-omap2/gpio.c +2 -0
@@ -88,6 +88,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->clr_irqenable =OMAP24XX_GPIO_CLEARIRQENABLE1 ; pdata->regs->debounce =OMAP24XX_GPIO_DEBOUNCE_VAL ; pdata->regs->debounce_en =OMAP24XX_GPIO_DEBOUNCE_EN ; + pdata->regs->ctrl =OMAP24XX_GPIO_CTRL ;break ;case 2 : pdata->bank_type =METHOD_GPIO_44XX ;
@@ -104,6 +105,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->clr_irqenable =OMAP4_GPIO_IRQSTATUSCLR0 ; pdata->regs->debounce =OMAP4_GPIO_DEBOUNCINGTIME ; pdata->regs->debounce_en =OMAP4_GPIO_DEBOUNCENABLE ; + pdata->regs->ctrl =OMAP4_GPIO_CTRL ;break ;default :WARN (1 ,"Invalid gpio bank_type\n" );
arch/arm/plat-omap/include/plat/gpio.h +1 -0
@@ -188,6 +188,7 @@ struct omap_gpio_reg_offs {u16 clr_irqenable;u16 debounce;u16 debounce_en; +u16 ctrl;bool irqenable_inv; };
drivers/gpio/gpio-omap.c +23 -30
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1.7.0.4
PATCH v9 7/25 gpio/omap: further cleanup using wkup_en register
In reply to Tarun Kanti DebBarmaWakeup enable register offset initialized according to OMAP versions during device registration. Use this to avoid version checks. Starting with OMAP4, legacy registers should not be used in combination with the updated regsiters. Use wkup_en register consistently for all SoCs wherever applicable.
--- arch/arm/mach-omap1/gpio16xx.c | 1 + arch/arm/mach-omap2/gpio.c | 2 + arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio-omap.c | 110 ++++++-------------------------- 4 files changed, 25 insertions(+), 89 deletions(-)
arch/arm/mach-omap1/gpio16xx.c +1 -0
@@ -89,6 +89,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = { .irqenable = OMAP1610_GPIO_IRQENABLE1, .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, + .wkup_en = OMAP1610_GPIO_WAKEUPENABLE, };static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
arch/arm/mach-omap2/gpio.c +2 -0
@@ -89,6 +89,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->debounce =OMAP24XX_GPIO_DEBOUNCE_VAL ; pdata->regs->debounce_en =OMAP24XX_GPIO_DEBOUNCE_EN ; pdata->regs->ctrl =OMAP24XX_GPIO_CTRL ; + pdata->regs->wkup_en =OMAP24XX_GPIO_WAKE_EN ;break ;case 2 : pdata->bank_type =METHOD_GPIO_44XX ;
@@ -106,6 +107,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->debounce =OMAP4_GPIO_DEBOUNCINGTIME ; pdata->regs->debounce_en =OMAP4_GPIO_DEBOUNCENABLE ; pdata->regs->ctrl =OMAP4_GPIO_CTRL ; + pdata->regs->wkup_en =OMAP4_GPIO_IRQWAKEN0 ;break ;default :WARN (1 ,"Invalid gpio bank_type\n" );
arch/arm/plat-omap/include/plat/gpio.h +1 -0
@@ -189,6 +189,7 @@ struct omap_gpio_reg_offs {u16 debounce;u16 debounce_en;u16 ctrl; +u16 wkup_en;bool irqenable_inv; };
drivers/gpio/gpio-omap.c +21 -89
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1.7.0.4
PATCH v9 8/25 gpio/omap: use level/edge detect reg offsets
In reply to Tarun Kanti DebBarmaBy adding level and edge detection register offsets and then initializing them correctly according to OMAP versions during device registrations we can now remove lot of revision checks in these functions.
--- arch/arm/mach-omap2/gpio.c | 8 ++ arch/arm/plat-omap/include/plat/gpio.h | 4 + drivers/gpio/gpio-omap.c | 114 +++++++++----------------------- 3 files changed, 44 insertions(+), 82 deletions(-)
arch/arm/mach-omap2/gpio.c +8 -0
@@ -90,6 +90,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->debounce_en =OMAP24XX_GPIO_DEBOUNCE_EN ; pdata->regs->ctrl =OMAP24XX_GPIO_CTRL ; pdata->regs->wkup_en =OMAP24XX_GPIO_WAKE_EN ; + pdata->regs->leveldetect0 =OMAP24XX_GPIO_LEVELDETECT0 ; + pdata->regs->leveldetect1 =OMAP24XX_GPIO_LEVELDETECT1 ; + pdata->regs->risingdetect =OMAP24XX_GPIO_RISINGDETECT ; + pdata->regs->fallingdetect =OMAP24XX_GPIO_FALLINGDETECT ;break ;case 2 : pdata->bank_type =METHOD_GPIO_44XX ;
@@ -108,6 +112,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->debounce_en =OMAP4_GPIO_DEBOUNCENABLE ; pdata->regs->ctrl =OMAP4_GPIO_CTRL ; pdata->regs->wkup_en =OMAP4_GPIO_IRQWAKEN0 ; + pdata->regs->leveldetect0 =OMAP4_GPIO_LEVELDETECT0 ; + pdata->regs->leveldetect1 =OMAP4_GPIO_LEVELDETECT1 ; + pdata->regs->risingdetect =OMAP4_GPIO_RISINGDETECT ; + pdata->regs->fallingdetect =OMAP4_GPIO_FALLINGDETECT ;break ;default :WARN (1 ,"Invalid gpio bank_type\n" );
arch/arm/plat-omap/include/plat/gpio.h +4 -0
@@ -190,6 +190,10 @@ struct omap_gpio_reg_offs {u16 debounce_en;u16 ctrl;u16 wkup_en; +u16 leveldetect0; +u16 leveldetect1; +u16 risingdetect; +u16 fallingdetect;bool irqenable_inv; };
drivers/gpio/gpio-omap.c +32 -82
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1.7.0.4
PATCH v9 9/25 gpio/omap: remove hardcoded offsets in context save/restore
In reply to Tarun Kanti DebBarmaIt is not required to use hard-coded offsets any more in context save and restore functions and instead use the generic offsets which have been correctly initialized during device registration.
--- arch/arm/mach-omap2/gpio.c | 2 + arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio-omap.c | 42 +++++++++++++++---------------- 3 files changed, 23 insertions(+), 22 deletions(-)
arch/arm/mach-omap2/gpio.c +2 -0
@@ -84,6 +84,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->irqstatus =OMAP24XX_GPIO_IRQSTATUS1 ; pdata->regs->irqstatus2 =OMAP24XX_GPIO_IRQSTATUS2 ; pdata->regs->irqenable =OMAP24XX_GPIO_IRQENABLE1 ; + pdata->regs->irqenable2 =OMAP24XX_GPIO_IRQENABLE2 ; pdata->regs->set_irqenable =OMAP24XX_GPIO_SETIRQENABLE1 ; pdata->regs->clr_irqenable =OMAP24XX_GPIO_CLEARIRQENABLE1 ; pdata->regs->debounce =OMAP24XX_GPIO_DEBOUNCE_VAL ;
@@ -106,6 +107,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->irqstatus =OMAP4_GPIO_IRQSTATUS0 ; pdata->regs->irqstatus2 =OMAP4_GPIO_IRQSTATUS1 ; pdata->regs->irqenable =OMAP4_GPIO_IRQSTATUSSET0 ; + pdata->regs->irqenable2 =OMAP4_GPIO_IRQSTATUSSET1 ; pdata->regs->set_irqenable =OMAP4_GPIO_IRQSTATUSSET0 ; pdata->regs->clr_irqenable =OMAP4_GPIO_IRQSTATUSCLR0 ; pdata->regs->debounce =OMAP4_GPIO_DEBOUNCINGTIME ;
arch/arm/plat-omap/include/plat/gpio.h +1 -0
@@ -184,6 +184,7 @@ struct omap_gpio_reg_offs {u16 irqstatus;u16 irqstatus2;u16 irqenable; +u16 irqenable2;u16 set_irqenable;u16 clr_irqenable;u16 debounce;
drivers/gpio/gpio-omap.c +20 -22
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1.7.0.4
PATCH v9 10/25 gpio/omap: cleanup set_gpio_triggering function
In reply to Tarun Kanti DebBarmaGetting rid of ifdefs within the function by adding register offset intctrl and associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific files. Also, use wkup_status register consistently instead of referring to wakeup clear and wakeup set register offsets. Get rid of cpu_is_xxxx checks in set_gpio_trigger() using irqctrl.
--- arch/arm/mach-omap1/gpio15xx.c | 2 + arch/arm/mach-omap1/gpio16xx.c | 3 + arch/arm/mach-omap1/gpio7xx.c | 2 + arch/arm/plat-omap/include/plat/gpio.h | 3 + drivers/gpio/gpio-omap.c | 157 +++++++++----------------------- 5 files changed, 53 insertions(+), 114 deletions(-)
arch/arm/mach-omap1/gpio15xx.c +2 -0
@@ -42,6 +42,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = { .irqstatus = OMAP_MPUIO_GPIO_INT, .irqenable = OMAP_MPUIO_GPIO_MASKIT, .irqenable_inv = true, + .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE, };static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
@@ -83,6 +84,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = { .irqstatus = OMAP1510_GPIO_INT_STATUS, .irqenable = OMAP1510_GPIO_INT_MASK, .irqenable_inv = true, + .irqctrl = OMAP1510_GPIO_INT_CONTROL, };static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
arch/arm/mach-omap1/gpio16xx.c +3 -0
@@ -45,6 +45,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = { .irqstatus = OMAP_MPUIO_GPIO_INT, .irqenable = OMAP_MPUIO_GPIO_MASKIT, .irqenable_inv = true, + .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE, };static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
@@ -90,6 +91,8 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = { .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, .wkup_en = OMAP1610_GPIO_WAKEUPENABLE, + .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1, + .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2, };static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
arch/arm/mach-omap1/gpio7xx.c +2 -0
@@ -47,6 +47,7 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = { .irqstatus = OMAP_MPUIO_GPIO_INT / 2, .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, .irqenable_inv = true, + .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1, };static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
@@ -88,6 +89,7 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = { .irqstatus = OMAP7XX_GPIO_INT_STATUS, .irqenable = OMAP7XX_GPIO_INT_MASK, .irqenable_inv = true, + .irqctrl = OMAP7XX_GPIO_INT_CONTROL, };static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
arch/arm/plat-omap/include/plat/gpio.h +3 -0
@@ -195,6 +195,9 @@ struct omap_gpio_reg_offs {u16 leveldetect1;u16 risingdetect;u16 fallingdetect; +u16 irqctrl; +u16 edgectrl1; +u16 edgectrl2;bool irqenable_inv; };
drivers/gpio/gpio-omap.c +43 -114
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1.7.0.4
PATCH v9 11/25 gpio/omap: cleanup omap_gpio_mod_init function
In reply to Tarun Kanti DebBarmaWith register offsets now defined for respective OMAP versions we can get rid of cpu_class_* checks. This function now has common initialization code for all OMAP versions. Initialization specific to OMAP16xx has been moved within omap16xx_gpio_init().
--- arch/arm/mach-omap1/gpio16xx.c | 35 +++++++++++++++++- drivers/gpio/gpio-omap.c | 77 ++++++++++++---------------------------- 2 files changed, 57 insertions(+), 55 deletions(-)
arch/arm/mach-omap1/gpio16xx.c +34 -1
@@ -24,6 +24,9 @@#define OMAP1610_GPIO4_BASE 0xfffbbc00#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE +/* smart idle, enable wakeup */ +#define SYSCONFIG_WORD 0x14 +/* mpu gpio */ static struct __initdata resource omap16xx_mpu_gpio_resources[] = { {
@@ -218,12 +221,42 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {static int __init omap16xx_gpio_init (void ) {int i; +void __iomem *base; +struct resource *res; +struct platform_device *pdev; +struct omap_gpio_platform_data *pdata;if (!cpu_is_omap16xx ())return -EINVAL ; -for (i =0 ; i <ARRAY_SIZE (omap16xx_gpio_dev); i++) +for (i =0 ; i <ARRAY_SIZE (omap16xx_gpio_dev); i++) { + pdev = omap16xx_gpio_dev[i]; + pdata = pdev->dev.platform_data; + + res =platform_get_resource (pdev,IORESOURCE_MEM ,0 ); +if (unlikely (!res)) { +dev_err (&pdev->dev,"Invalid mem resource.\n" ); +return -ENODEV ; + } + + base =ioremap (res->start,resource_size (res)); +if (unlikely (!base)) { +dev_err (&pdev->dev,"ioremap failed.\n" ); +return -ENOMEM ; + } + +__raw_writel (SYSCONFIG_WORD , base +OMAP1610_GPIO_SYSCONFIG ); +iounmap (base); + +/* +* Enable system clock for GPIO module. +* The CAM_CLK_CTRL *is* really the right place. +*/ +omap_writel (omap_readl (ULPD_CAM_CLK_CTRL ) |0x04 , +ULPD_CAM_CLK_CTRL ); +platform_device_register (omap16xx_gpio_dev[i]); + }return 0 ; }
drivers/gpio/gpio-omap.c +23 -54
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1.7.0.4
PATCH v9 12/25 gpio/omap: use pinctrl offset instead of macro
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL
--- arch/arm/mach-omap1/gpio15xx.c | 1 + arch/arm/plat-omap/include/plat/gpio.h | 1 + drivers/gpio/gpio-omap.c | 8 +++----- 3 files changed, 5 insertions(+), 5 deletions(-)
arch/arm/mach-omap1/gpio15xx.c +1 -0
@@ -85,6 +85,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = { .irqenable = OMAP1510_GPIO_INT_MASK, .irqenable_inv = true, .irqctrl = OMAP1510_GPIO_INT_CONTROL, + .pinctrl = OMAP1510_GPIO_PIN_CONTROL, };static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
arch/arm/plat-omap/include/plat/gpio.h +1 -0
@@ -198,6 +198,7 @@ struct omap_gpio_reg_offs {u16 irqctrl;u16 edgectrl1;u16 edgectrl2; +u16 pinctrl;bool irqenable_inv; };
drivers/gpio/gpio-omap.c +3 -5
@@ -490,15 +490,13 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)*/ _set_gpio_triggering (bank, offset,IRQ_TYPE_NONE ); -#ifdef CONFIG_ARCH_OMAP15XX -if (bank->method ==METHOD_GPIO_1510 ) { -void __iomem *reg; +if (bank->regs->pinctrl) { +void __iomem *reg = bank->base + bank->regs->pinctrl;/* Claim the pin for MPU */ - reg = bank->base +OMAP1510_GPIO_PIN_CONTROL ;__raw_writel (__raw_readl (reg) | (1 << offset), reg); } -#endif +if (bank->regs->ctrl && !bank->mod_usage) {void __iomem *reg = bank->base + bank->regs->ctrl;u32 ctrl;
Signature · 1 line
1.7.0.4
PATCH v9 13/25 gpio/omap: remove unnecessary bit-masking for read access
In reply to Tarun Kanti DebBarmaRemove un-necessary bit masking. Since the register are 4 byte aligned and readl would work as is. The 'enabled' mask is already taking care to mask for bank width.
--- drivers/gpio/gpio-omap.c | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-)
drivers/gpio/gpio-omap.c +0 -3
@@ -576,9 +576,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) enabled =_get_gpio_irqbank_mask (bank); isr_saved = isr =__raw_readl (isr_reg) & enabled; -if (cpu_is_omap15xx () && (bank->method ==METHOD_MPUIO )) - isr &=0x0000ffff ; -if (bank->level_mask) level_mask = bank->level_mask & enabled;
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1.7.0.4
PATCH v9 14/25 gpio/omap: remove bank->method & METHOD_* macros
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
The only bank->type (method) used in the OMAP GPIO driver is MPUIO type as they need to be handled separately. Identify the same using a flag and remove all METHOD_* macros.
mpuio_init() function is defined under #ifdefs. It is required only in case of MPUIO bank type and only when PM operations are supported by it. This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type. For all the other cases it is a dummy function. Hence clean up the same and remove all the OMAP SoC specific #ifdefs.
--- arch/arm/mach-omap1/gpio15xx.c | 3 +- arch/arm/mach-omap1/gpio16xx.c | 6 +---- arch/arm/mach-omap1/gpio7xx.c | 8 +------ arch/arm/mach-omap2/gpio.c | 2 - arch/arm/plat-omap/include/plat/gpio.h | 8 +------ drivers/gpio/gpio-omap.c | 38 +++++-------------------------- 6 files changed, 10 insertions(+), 55 deletions(-)
arch/arm/mach-omap1/gpio15xx.c +1 -2
@@ -47,7 +47,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { .virtual_irq_start =IH_MPUIO_BASE , - .bank_type =METHOD_MPUIO , + .is_mpuio = true, .bank_width =16 , .bank_stride =1 , .regs = &omap15xx_mpuio_regs,
@@ -90,7 +90,6 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { .virtual_irq_start =IH_GPIO_BASE , - .bank_type =METHOD_GPIO_1510 , .bank_width =16 , .regs = &omap15xx_gpio_regs, };
arch/arm/mach-omap1/gpio16xx.c +1 -5
@@ -53,7 +53,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { .virtual_irq_start =IH_MPUIO_BASE , - .bank_type =METHOD_MPUIO , + .is_mpuio = true, .bank_width =16 , .bank_stride =1 , .regs = &omap16xx_mpuio_regs,
@@ -100,7 +100,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { .virtual_irq_start =IH_GPIO_BASE , - .bank_type =METHOD_GPIO_1610 , .bank_width =16 , .regs = &omap16xx_gpio_regs, };
@@ -130,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { .virtual_irq_start =IH_GPIO_BASE +16 , - .bank_type =METHOD_GPIO_1610 , .bank_width =16 , .regs = &omap16xx_gpio_regs, };
@@ -160,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { .virtual_irq_start =IH_GPIO_BASE +32 , - .bank_type =METHOD_GPIO_1610 , .bank_width =16 , .regs = &omap16xx_gpio_regs, };
@@ -190,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { .virtual_irq_start =IH_GPIO_BASE +48 , - .bank_type =METHOD_GPIO_1610 , .bank_width =16 , .regs = &omap16xx_gpio_regs, };
arch/arm/mach-omap1/gpio7xx.c +1 -7
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { .virtual_irq_start =IH_MPUIO_BASE , - .bank_type =METHOD_MPUIO , .bank_width =32 , + .is_mpuio = true, .bank_stride =2 , .regs = &omap7xx_mpuio_regs, };
@@ -94,7 +94,6 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { .virtual_irq_start =IH_GPIO_BASE , - .bank_type =METHOD_GPIO_7XX , .bank_width =32 , .regs = &omap7xx_gpio_regs, };
@@ -124,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { .virtual_irq_start =IH_GPIO_BASE +32 , - .bank_type =METHOD_GPIO_7XX , .bank_width =32 , .regs = &omap7xx_gpio_regs, };
@@ -154,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { .virtual_irq_start =IH_GPIO_BASE +64 , - .bank_type =METHOD_GPIO_7XX , .bank_width =32 , .regs = &omap7xx_gpio_regs, };
@@ -184,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { .virtual_irq_start =IH_GPIO_BASE +96 , - .bank_type =METHOD_GPIO_7XX , .bank_width =32 , .regs = &omap7xx_gpio_regs, };
@@ -214,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { .virtual_irq_start =IH_GPIO_BASE +128 , - .bank_type =METHOD_GPIO_7XX , .bank_width =32 , .regs = &omap7xx_gpio_regs, };
@@ -244,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { .virtual_irq_start =IH_GPIO_BASE +160 , - .bank_type =METHOD_GPIO_7XX , .bank_width =32 , .regs = &omap7xx_gpio_regs, };
arch/arm/mach-omap2/gpio.c +0 -2
@@ -74,7 +74,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)/* fall through */ case 1 : - pdata->bank_type =METHOD_GPIO_24XX ; pdata->regs->revision =OMAP24XX_GPIO_REVISION ; pdata->regs->direction =OMAP24XX_GPIO_OE ; pdata->regs->datain =OMAP24XX_GPIO_DATAIN ;
@@ -97,7 +96,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs->fallingdetect =OMAP24XX_GPIO_FALLINGDETECT ;break ;case 2 : - pdata->bank_type =METHOD_GPIO_44XX ; pdata->regs->revision =OMAP4_GPIO_REVISION ; pdata->regs->direction =OMAP4_GPIO_OE ; pdata->regs->datain =OMAP4_GPIO_DATAIN ;
arch/arm/plat-omap/include/plat/gpio.h +1 -7
@@ -162,13 +162,6 @@ IH_MPUIO_BASE + ((nr) & 0x0f) : \ IH_GPIO_BASE + (nr)) -#define METHOD_MPUIO 0 -#define METHOD_GPIO_1510 1 -#define METHOD_GPIO_1610 2 -#define METHOD_GPIO_7XX 3 -#define METHOD_GPIO_24XX 5 -#define METHOD_GPIO_44XX 6 - struct omap_gpio_dev_attr { int bank_width; /* GPIO bank width */ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
@@ -210,6 +203,7 @@ struct omap_gpio_platform_data {int bank_stride;/* Only needed for omap1 MPUIO */ bool dbck_flag;/* dbck required or not - True for OMAP3&4 */ bool loses_context;/* whether the bank would ever lose context */ +bool is_mpuio;/* whether the bank is of type MPUIO */ u32 non_wakeup_gpios;struct omap_gpio_reg_offs *regs;
drivers/gpio/gpio-omap.c +6 -32
@@ -49,7 +49,6 @@ struct gpio_bank {void __iomem *base;u16 irq;u16 virtual_irq_start; -int method;u32 suspend_wakeup;u32 saved_wakeup;u32 non_wakeup_gpios;
@@ -66,6 +65,7 @@ struct gpio_bank {u32 mod_usage;u32 dbck_enable_mask;struct device *dev; +bool is_mpuio;bool dbck_flag;bool loses_context;int stride;
@@ -693,14 +693,6 @@ static struct irq_chip gpio_irq_chip = {/*---------------------------------------------------------------------*/ -#ifdef CONFIG_ARCH_OMAP1 - -#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) - -#ifdef CONFIG_ARCH_OMAP16XX - -#include <linux/platform_device.h> -static int omap_mpuio_suspend_noirq (struct device *dev) {struct platform_device *pdev =to_platform_device (dev);
@@ -762,23 +754,8 @@ static inline void mpuio_init(struct gpio_bank *bank) (void )platform_device_register (&omap_mpuio_device); } -#else -static inline void mpuio_init (struct gpio_bank *bank) {} -#endif /* 16xx */ - -#else - -#define bank_is_mpuio (bank) 0 -static inline void mpuio_init (struct gpio_bank *bank) {} - -#endif -/*---------------------------------------------------------------------*/ -/* REVISIT these are stupid implementations! replace by ones that -* don't switch on METHOD_* and which mostly avoid spinlocks -*/ -static int gpio_input (struct gpio_chip *chip,unsigned offset) {struct gpio_bank *bank;
@@ -899,7 +876,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)if (bank->width ==16 ) l =0xffff ; -if (bank_is_mpuio (bank)) { +if (bank->is_mpuio) {__raw_writel (l, bank->base + bank->regs->irqenable);return ; }
@@ -951,7 +928,6 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)int j;static int gpio; - bank->mod_usage =0 ;/* * REVISIT eventually switch from OMAP-specific gpio structs * over to the generic ones
@@ -964,12 +940,10 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) bank->chip.set_debounce = gpio_debounce; bank->chip.set = gpio_set; bank->chip.to_irq = gpio_2irq; -if (bank_is_mpuio (bank)) { +if (bank->is_mpuio) { bank->chip.label ="mpuio" ; -#ifdef CONFIG_ARCH_OMAP16XX if (bank->regs->wkup_en) bank->chip.dev = &omap_mpuio_device.dev; -#endif bank->chip.base =OMAP_MPUIO (0 ); }else { bank->chip.label ="gpio" ;
@@ -984,7 +958,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) j < bank->virtual_irq_start + bank->width; j++) {irq_set_lockdep_class (j, &gpio_lock_class);irq_set_chip_data (j, bank); -if (bank_is_mpuio (bank)) { +if (bank->is_mpuio) {omap_mpuio_alloc_gc (bank, j, bank->width); }else {irq_set_chip (j, &gpio_irq_chip);
@@ -1028,11 +1002,11 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) pdata = pdev->dev.platform_data; bank->virtual_irq_start = pdata->virtual_irq_start; - bank->method = pdata->bank_type; bank->dev = &pdev->dev; bank->dbck_flag = pdata->dbck_flag; bank->stride = pdata->bank_stride; bank->width = pdata->bank_width; + bank->is_mpuio = pdata->is_mpuio; bank->non_wakeup_gpios = pdata->non_wakeup_gpios; bank->loses_context = pdata->loses_context; bank->get_context_loss_count = pdata->get_context_loss_count;
@@ -1065,7 +1039,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)pm_runtime_enable (bank->dev);pm_runtime_get_sync (bank->dev); -if (bank_is_mpuio (bank)) +if (bank->is_mpuio)mpuio_init (bank);omap_gpio_mod_init (bank);
Signature · 1 line
1.7.0.4
PATCH v9 15/25 gpio/omap: fix bankwidth for OMAP7xx MPUIO
In reply to Tarun Kanti DebBarmaFrom: Charulatha V <[email protected]>
In all OMAP1 SoCs, the MPUIO bank width is 16 bits. But, in OMAP7xx, it is wrongly initialised to 32. Fix this.
--- arch/arm/mach-omap1/gpio7xx.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-omap1/gpio7xx.c +1 -1
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { .virtual_irq_start =IH_MPUIO_BASE , - .bank_width =32 , .is_mpuio = true, + .bank_width =16 , .bank_stride =2 , .regs = &omap7xx_mpuio_regs, };
Signature · 1 line
1.7.0.4
PATCH v9 16/25 gpio/omap: use pm-runtime framework
In reply to Tarun Kanti DebBarmaCall runtime pm APIs pm_runtime_get_sync() and pm_runtime_put() for enabling/disabling clocks appropriately. Remove syscore_ops and instead use SET_RUNTIME_PM_OPS macro.
There is no more need to call omap_device_disable_idle_on_suspend since driver is PM runtime adapted now.
--- arch/arm/mach-omap2/gpio.c | 2 - drivers/gpio/gpio-omap.c | 65 ++++++++++++++++++++++++++++--------------- 2 files changed, 42 insertions(+), 25 deletions(-)
arch/arm/mach-omap2/gpio.c +0 -2
@@ -136,8 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)return PTR_ERR (pdev); } -omap_device_disable_idle_on_suspend (pdev); -return 0 ; }
drivers/gpio/gpio-omap.c +42 -23
166 lines not on this page · raw message
Signature · 1 line
1.7.0.4
PATCH v9 17/25 gpio/omap: optimize suspend and resume functions
In reply to Tarun Kanti DebBarmaThere is no need to operate on all the banks every time the function is called. Just operate on the current bank passed by the framework.
--- drivers/gpio/gpio-omap.c | 54 ++++++++++++++++++++++++--------------------- 1 files changed, 29 insertions(+), 25 deletions(-)
drivers/gpio/gpio-omap.c +29 -25
@@ -1052,6 +1052,8 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) goto err_free; } +platform_set_drvdata (pdev, bank); +pm_runtime_enable (bank->dev);pm_runtime_irq_safe (bank->dev);pm_runtime_get_sync (bank->dev);
@@ -1079,44 +1081,46 @@ err_exit:static int omap_gpio_suspend (struct device *dev) { -struct gpio_bank *bank; +struct platform_device *pdev =to_platform_device (dev); +struct gpio_bank *bank =platform_get_drvdata (pdev); +void __iomem *base = bank->base; +void __iomem *wakeup_enable; +unsigned long flags; -list_for_each_entry (bank, &omap_gpio_list, node) { -void __iomem *base = bank->base; -void __iomem *wake_status; -unsigned long flags; +if (!bank->mod_usage || !bank->loses_context) +return 0 ; -if (!bank->regs->wkup_en) -return 0 ; +if (!bank->regs->wkup_en || !bank->suspend_wakeup) +return 0 ; - wake_status = bank->base + bank->regs->wkup_en; + wakeup_enable = bank->base + bank->regs->wkup_en; -spin_lock_irqsave (&bank->lock, flags); - bank->saved_wakeup =__raw_readl (wake_status); -_gpio_rmw (base, bank->regs->wkup_en,0xffffffff ,0 ); -_gpio_rmw (base, bank->regs->wkup_en, bank->suspend_wakeup,1 ); -spin_unlock_irqrestore (&bank->lock, flags); - } +spin_lock_irqsave (&bank->lock, flags); + bank->saved_wakeup =__raw_readl (wakeup_enable); +_gpio_rmw (base, bank->regs->wkup_en,0xffffffff ,0 ); +_gpio_rmw (base, bank->regs->wkup_en, bank->suspend_wakeup,1 ); +spin_unlock_irqrestore (&bank->lock, flags);return 0 ; }static int omap_gpio_resume (struct device *dev) { -struct gpio_bank *bank; +struct platform_device *pdev =to_platform_device (dev); +struct gpio_bank *bank =platform_get_drvdata (pdev); +void __iomem *base = bank->base; +unsigned long flags; -list_for_each_entry (bank, &omap_gpio_list, node) { -void __iomem *base = bank->base; -unsigned long flags; +if (!bank->mod_usage || !bank->loses_context) +return 0 ; -if (!bank->regs->wkup_en) -return 0 ; +if (!bank->regs->wkup_en || !bank->saved_wakeup) +return 0 ; -spin_lock_irqsave (&bank->lock, flags); -_gpio_rmw (base, bank->regs->wkup_en,0xffffffff ,0 ); -_gpio_rmw (base, bank->regs->wkup_en, bank->saved_wakeup,1 ); -spin_unlock_irqrestore (&bank->lock, flags); - } +spin_lock_irqsave (&bank->lock, flags); +_gpio_rmw (base, bank->regs->wkup_en,0xffffffff ,0 ); +_gpio_rmw (base, bank->regs->wkup_en, bank->saved_wakeup,1 ); +spin_unlock_irqrestore (&bank->lock, flags);return 0 ; }
Signature · 1 line
1.7.0.4
PATCH v9 18/25 gpio/omap: cleanup prepare_for_idle and resume_after_idle
In reply to Tarun Kanti DebBarmaSince *_prepare_for_idle() and *_resume_after_idle() are called with interrupts disabled they should be kept as simple as possible. So, moving most of the stuff to *_runtime_suspend/resume() callbacks.
To avoid invalid context restore happening in *_runtime_resume() callback as a result of *_get_sync() call in *_gpio_probe(), update bank->context_loss_count. This would make context restore condition check false in the callback and skip restore until further initialization take place. The workaround_enabled static variable is now a member of struct gpio_bank.
Unlike most GPIO registers the OE has 0xffffffff as the default value. To make sure invalid context is not restored, updating the OE context with default value.
--- drivers/gpio/gpio-omap.c | 241 +++++++++++++++++++++++++++------------------- 1 files changed, 143 insertions(+), 98 deletions(-)
drivers/gpio/gpio-omap.c +143 -98
@@ -29,6 +29,8 @@#include <asm/gpio.h> #include <asm/mach/irq.h> +#define OFF_MODE 1 +static LIST_HEAD (omap_gpio_list);struct gpio_regs {
@@ -73,6 +75,8 @@ struct gpio_bank {u32 width;int context_loss_count;u16 id; +int power_mode; +bool workaround_enabled;void (*set_dataout)(struct gpio_bank *bank,int gpio,int enable);int (*get_context_loss_count)(struct device *dev);
@@ -905,6 +909,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)if (bank->regs->debounce_en)_gpio_rmw (base, bank->regs->debounce_en,0 ,1 ); +/* Save OE default value (0xffffffff) in the context */ + bank->context.oe =__raw_readl (bank->base + bank->regs->direction);/* Initialize interface clk ungated, module enabled */ if (bank->regs->ctrl)_gpio_rmw (base, bank->regs->ctrl,0 ,1 );
@@ -1129,135 +1135,170 @@ static int omap_gpio_resume(struct device *dev)static void omap_gpio_save_context (struct gpio_bank *bank);static void omap_gpio_restore_context (struct gpio_bank *bank); -void omap2_gpio_prepare_for_idle (int off_mode) +static int omap_gpio_runtime_suspend (struct device *dev) { -struct gpio_bank *bank; - -list_for_each_entry (bank, &omap_gpio_list, node) { -u32 l1 =0 , l2 =0 ; -int j; - -if (!bank->loses_context) -continue ; - -for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++) -clk_disable (bank->dbck); +struct platform_device *pdev =to_platform_device (dev); +struct gpio_bank *bank =platform_get_drvdata (pdev); +u32 l1 =0 , l2 =0 ; +unsigned long flags; -if (!off_mode) -continue ; +spin_lock_irqsave (&bank->lock, flags); +if (bank->power_mode !=OFF_MODE ) { + bank->power_mode =0 ; + goto save_gpio_context; + } +/* +* If going to OFF, remove triggering for all +* non-wakeup GPIOs. Otherwise spurious IRQs will be +* generated. See OMAP2420 Errata item 1.101. +*/ +if (!(bank->enabled_non_wakeup_gpios)) + goto save_gpio_context; -/* If going to OFF, remove triggering for all -* non-wakeup GPIOs. Otherwise spurious IRQs will be -* generated. See OMAP2420 Errata item 1.101. */ -if (!(bank->enabled_non_wakeup_gpios)) - goto save_gpio_context; + bank->saved_datain =__raw_readl (bank->base + + bank->regs->datain); + l1 =__raw_readl (bank->base + bank->regs->fallingdetect); + l2 =__raw_readl (bank->base + bank->regs->risingdetect); - bank->saved_datain =__raw_readl (bank->base + - bank->regs->datain); - l1 =__raw_readl (bank->base + bank->regs->fallingdetect); - l2 =__raw_readl (bank->base + bank->regs->risingdetect); + bank->saved_fallingdetect = l1; + bank->saved_risingdetect = l2; + l1 &= ~bank->enabled_non_wakeup_gpios; + l2 &= ~bank->enabled_non_wakeup_gpios; - bank->saved_fallingdetect = l1; - bank->saved_risingdetect = l2; - l1 &= ~bank->enabled_non_wakeup_gpios; - l2 &= ~bank->enabled_non_wakeup_gpios; +__raw_writel (l1, bank->base + bank->regs->fallingdetect); +__raw_writel (l2, bank->base + bank->regs->risingdetect); -__raw_writel (l1, bank->base + bank->regs->fallingdetect); -__raw_writel (l2, bank->base + bank->regs->risingdetect); + bank->workaround_enabled = true; save_gpio_context: - -if (bank->get_context_loss_count) - bank->context_loss_count = +if (bank->get_context_loss_count) + bank->context_loss_count = bank->get_context_loss_count (bank->dev); -omap_gpio_save_context (bank); +omap_gpio_save_context (bank); +spin_unlock_irqrestore (&bank->lock, flags); -if (!pm_runtime_suspended (bank->dev)) -pm_runtime_put (bank->dev); - } +return 0 ; } -void omap2_gpio_resume_after_idle (void ) +static int omap_gpio_runtime_resume (struct device *dev) { -struct gpio_bank *bank; - -list_for_each_entry (bank, &omap_gpio_list, node) { -int context_lost_cnt_after; -u32 l =0 , gen, gen0, gen1; -int j; - -if (!bank->loses_context) -continue ; - -for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++) -clk_enable (bank->dbck); +struct platform_device *pdev =to_platform_device (dev); +struct gpio_bank *bank =platform_get_drvdata (pdev); +int context_lost_cnt_after; +u32 l =0 , gen, gen0, gen1; +unsigned long flags; -if (pm_runtime_suspended (bank->dev)) -pm_runtime_get_sync (bank->dev); +spin_lock_irqsave (&bank->lock, flags); +if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { +spin_unlock_irqrestore (&bank->lock, flags); +return 0 ; + } -if (bank->get_context_loss_count) { - context_lost_cnt_after = - bank->get_context_loss_count (bank->dev); -if (context_lost_cnt_after != bank->context_loss_count - || !context_lost_cnt_after) -omap_gpio_restore_context (bank); +if (bank->get_context_loss_count) { + context_lost_cnt_after = + bank->get_context_loss_count (bank->dev); +if (context_lost_cnt_after != bank->context_loss_count || + !context_lost_cnt_after) { +omap_gpio_restore_context (bank); + }else { +spin_unlock_irqrestore (&bank->lock, flags); +return 0 ; } + } -if (!(bank->enabled_non_wakeup_gpios)) -continue ; +__raw_writel (bank->saved_fallingdetect, + bank->base + bank->regs->fallingdetect); +__raw_writel (bank->saved_risingdetect, + bank->base + bank->regs->risingdetect); + l =__raw_readl (bank->base + bank->regs->datain); -__raw_writel (bank->saved_fallingdetect, - bank->base + bank->regs->fallingdetect); -__raw_writel (bank->saved_risingdetect, - bank->base + bank->regs->risingdetect); - l =__raw_readl (bank->base + bank->regs->datain); +/* +* Check if any of the non-wakeup interrupt GPIOs have changed +* state. If so, generate an IRQ by software. This is +* horribly racy, but it's the best we can do to work around +* this silicon bug. +*/ + l ^= bank->saved_datain; + l &= bank->enabled_non_wakeup_gpios; -/* Check if any of the non-wakeup interrupt GPIOs have changed -* state. If so, generate an IRQ by software. This is -* horribly racy, but it's the best we can do to work around -* this silicon bug. */ - l ^= bank->saved_datain; - l &= bank->enabled_non_wakeup_gpios; +/* +* No need to generate IRQs for the rising edge for gpio IRQs +* configured with falling edge only; and vice versa. +*/ + gen0 = l & bank->saved_fallingdetect; + gen0 &= bank->saved_datain; -/* -* No need to generate IRQs for the rising edge for gpio IRQs -* configured with falling edge only; and vice versa. -*/ - gen0 = l & bank->saved_fallingdetect; - gen0 &= bank->saved_datain; + gen1 = l & bank->saved_risingdetect; + gen1 &= ~(bank->saved_datain); - gen1 = l & bank->saved_risingdetect; - gen1 &= ~(bank->saved_datain); +/* FIXME: Consider GPIO IRQs with level detections properly! */ + gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect)); +/* Consider all GPIO IRQs needed to be updated */ + gen |= gen0 | gen1; -/* FIXME: Consider GPIO IRQs with level detections properly! */ - gen = l & (~(bank->saved_fallingdetect) & - ~(bank->saved_risingdetect)); -/* Consider all GPIO IRQs needed to be updated */ - gen |= gen0 | gen1; +if (gen) { +u32 old0, old1; -if (gen) { -u32 old0, old1; + old0 =__raw_readl (bank->base + bank->regs->leveldetect0); + old1 =__raw_readl (bank->base + bank->regs->leveldetect1); - old0 =__raw_readl (bank->base + +if (cpu_is_omap24xx () ||cpu_is_omap34xx ()) { +__raw_writel (old0 | gen, bank->base + bank->regs->leveldetect0); - old1 =__raw_readl (bank->base + +__raw_writel (old1 | gen, bank->base + bank->regs->leveldetect1); + } -if (cpu_is_omap24xx () ||cpu_is_omap34xx ()) { - old0 |= gen; - old1 |= gen; - } - -if (cpu_is_omap44xx ()) { - old0 |= l; - old1 |= l; - } -__raw_writel (old0, bank->base + +if (cpu_is_omap44xx ()) { +__raw_writel (old0 | l, bank->base + bank->regs->leveldetect0); -__raw_writel (old1, bank->base + +__raw_writel (old1 | l, bank->base + bank->regs->leveldetect1); } +__raw_writel (old0, bank->base + bank->regs->leveldetect0); +__raw_writel (old1, bank->base + bank->regs->leveldetect1); + } + + bank->workaround_enabled = false; +spin_unlock_irqrestore (&bank->lock, flags); + +return 0 ; +} + +void omap2_gpio_prepare_for_idle (int pwr_mode) +{ +struct gpio_bank *bank; + +list_for_each_entry (bank, &omap_gpio_list, node) { +int j; + +if (!bank->mod_usage || !bank->loses_context) +continue ; + + bank->power_mode = pwr_mode; + +for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++) +clk_disable (bank->dbck); + +pm_runtime_put_sync_suspend (bank->dev); + } +} + +void omap2_gpio_resume_after_idle (void ) +{ +struct gpio_bank *bank; + +list_for_each_entry (bank, &omap_gpio_list, node) { +int j; + +if (!bank->mod_usage || !bank->loses_context) +continue ; + +for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++) +clk_enable (bank->dbck); + +pm_runtime_get_sync (bank->dev); } }
@@ -1305,10 +1346,14 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)#else #define omap_gpio_suspend NULL#define omap_gpio_resume NULL +#define omap_gpio_runtime_suspend NULL +#define omap_gpio_runtime_resume NULL#endif static const struct dev_pm_ops gpio_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) +SET_RUNTIME_PM_OPS (omap_gpio_runtime_suspend, omap_gpio_runtime_resume, +NULL ) };static struct platform_driver omap_gpio_driver = {
Signature · 1 line
1.7.0.4
PATCH v9 19/25 gpio/omap: fix debounce clock handling
In reply to Tarun Kanti DebBarmaThe dbck_enable_mask indicates which all GPIOs within a bank have debounce enabled and dbck is enabled/disabled based upon this. But there is no mechanism to track the dbck state. In order to manage the dbck state we need additional flag and logic so that turning off/on dbck is synchronized with pm_runtime_put/get_sync calls.
--- drivers/gpio/gpio-omap.c | 29 +++++++++++++++++++---------- 1 files changed, 19 insertions(+), 10 deletions(-)
drivers/gpio/gpio-omap.c +19 -10
@@ -67,6 +67,7 @@ struct gpio_bank {struct clk *dbck;u32 mod_usage;u32 dbck_enable_mask; +bool dbck_enabled;struct device *dev;bool is_mpuio;bool dbck_flag;
@@ -158,6 +159,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)__raw_writel (l, base + reg); } +static inline void _gpio_dbck_enable (struct gpio_bank *bank) +{ +if (bank->dbck_enable_mask && !bank->dbck_enabled) { +clk_enable (bank->dbck); + bank->dbck_enabled = true; + } +} + +static inline void _gpio_dbck_disable (struct gpio_bank *bank) +{ +if (bank->dbck_enable_mask && bank->dbck_enabled) { +clk_disable (bank->dbck); + bank->dbck_enabled = false; + } +} +/** * _set_gpio_debounce - low level gpio debounce time * @bank: the gpio bank we're acting upon
@@ -1176,6 +1193,7 @@ save_gpio_context: bank->get_context_loss_count (bank->dev);omap_gpio_save_context (bank); +_gpio_dbck_disable (bank);spin_unlock_irqrestore (&bank->lock, flags);return 0 ;
@@ -1190,6 +1208,7 @@ static int omap_gpio_runtime_resume(struct device *dev)unsigned long flags;spin_lock_irqsave (&bank->lock, flags); +_gpio_dbck_enable (bank);if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {spin_unlock_irqrestore (&bank->lock, flags);return 0 ;
@@ -1271,16 +1290,11 @@ void omap2_gpio_prepare_for_idle(int pwr_mode)struct gpio_bank *bank;list_for_each_entry (bank, &omap_gpio_list, node) { -int j; -if (!bank->mod_usage || !bank->loses_context)continue ; bank->power_mode = pwr_mode; -for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++) -clk_disable (bank->dbck); -pm_runtime_put_sync_suspend (bank->dev); } }
@@ -1290,14 +1304,9 @@ void omap2_gpio_resume_after_idle(void)struct gpio_bank *bank;list_for_each_entry (bank, &omap_gpio_list, node) { -int j; -if (!bank->mod_usage || !bank->loses_context)continue ; -for (j =0 ; j <hweight_long (bank->dbck_enable_mask); j++) -clk_enable (bank->dbck); -pm_runtime_get_sync (bank->dev); } }
Signature · 1 line
1.7.0.4
PATCH v9 20/25 gpio/omap: fix incorrect access of debounce module
In reply to Tarun Kanti DebBarmaEnable debounce clock before writing/reading debounce registers. Disable the clock at the end so that it is synchronized with the pm_runtime_get/put_sync calls.
Enable debounce clock per module. This call is mandatory because in omap_gpio_request() when *_runtime_get_sync() is called, _gpio_dbck_enable() within runtime callbck fails to turn on dbck
because dbck_enable_mask used within _gpio_dbck_enable() is still
not initialized at that point. Therefore we have to enable dbck here.
--- drivers/gpio/gpio-omap.c | 18 +++++++++++++----- 1 files changed, 13 insertions(+), 5 deletions(-)
drivers/gpio/gpio-omap.c +13 -5
@@ -203,22 +203,30 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, l =GPIO_BIT (bank, gpio); +clk_enable (bank->dbck); reg = bank->base + bank->regs->debounce;__raw_writel (debounce, reg); reg = bank->base + bank->regs->debounce_en; val =__raw_readl (reg); -if (debounce) { +if (debounce) val |= l; -clk_enable (bank->dbck); - }else { +else val &= ~l; -clk_disable (bank->dbck); - } bank->dbck_enable_mask = val;__raw_writel (val, reg); +clk_disable (bank->dbck); +/* +* Enable debounce clock per module. +* This call is mandatory because in omap_gpio_request() when +* *_runtime_get_sync() is called, _gpio_dbck_enable() within +* runtime callbck fails to turn on dbck because dbck_enable_mask +* used within _gpio_dbck_enable() is still not initialized at +* that point. Therefore we have to enable dbck here. +*/ +_gpio_dbck_enable (bank); } static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
Signature · 1 line
1.7.0.4
PATCH v9 21/25 gpio/omap: remove omap_gpio_save_context overhead
In reply to Tarun Kanti DebBarmaContext is now saved dynamically in respective functions whenever and whichever registers are modified. This avoid overhead of saving all registers context in the runtime suspend callback.
--- drivers/gpio/gpio-omap.c | 56 +++++++++++++++++++++++----------------------- 1 files changed, 28 insertions(+), 28 deletions(-)
drivers/gpio/gpio-omap.c +28 -28
@@ -101,6 +101,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)else l &= ~(1 << gpio);__raw_writel (l, reg); + bank->context.oe = l; }
@@ -131,6 +132,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)else l &= ~gpio_bit;__raw_writel (l, reg); + bank->context.dataout = l; }static int _get_gpio_datain (struct gpio_bank *bank,int gpio)
@@ -244,8 +246,20 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,_gpio_rmw (base, bank->regs->fallingdetect, gpio_bit, trigger &IRQ_TYPE_EDGE_FALLING ); -if (likely (!(bank->non_wakeup_gpios & gpio_bit))) + bank->context.leveldetect0 = +__raw_readl (bank->base + bank->regs->leveldetect0); + bank->context.leveldetect1 = +__raw_readl (bank->base + bank->regs->leveldetect1); + bank->context.risingdetect = +__raw_readl (bank->base + bank->regs->risingdetect); + bank->context.fallingdetect = +__raw_readl (bank->base + bank->regs->fallingdetect); + +if (likely (!(bank->non_wakeup_gpios & gpio_bit))) {_gpio_rmw (base, bank->regs->wkup_en, gpio_bit, trigger !=0 ); + bank->context.wake_en = +__raw_readl (bank->base + bank->regs->wkup_en); + }/* This part needs to be executed always for OMAP{34xx, 44xx} */ if (!bank->regs->irqctrl) {
@@ -338,6 +352,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)/* Enable wake-up during idle for dynamic tick */ _gpio_rmw (base, bank->regs->wkup_en,1 << gpio, trigger); + bank->context.wake_en = +__raw_readl (bank->base + bank->regs->wkup_en);__raw_writel (l, reg); }return 0 ;
@@ -430,6 +446,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) }__raw_writel (l, reg); + bank->context.irqenable1 = l; }static void _disable_gpio_irqbank (struct gpio_bank *bank,int gpio_mask)
@@ -450,6 +467,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) }__raw_writel (l, reg); + bank->context.irqenable1 = l; }static inline void _set_gpio_irqenable (struct gpio_bank *bank,int gpio,int enable)
@@ -541,6 +559,7 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)/* Module is enabled, clocks are not gated */ ctrl &= ~GPIO_MOD_CTRL_BIT ;__raw_writel (ctrl, reg); + bank->context.ctrl = ctrl; } bank->mod_usage |=1 << offset;
@@ -558,9 +577,12 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)spin_lock_irqsave (&bank->lock, flags); -if (bank->regs->wkup_en) +if (bank->regs->wkup_en) {/* Disable wake-up during idle for dynamic tick */ _gpio_rmw (base, bank->regs->wkup_en,1 << offset,0 ); + bank->context.wake_en = +__raw_readl (bank->base + bank->regs->wkup_en); + } bank->mod_usage &= ~(1 << offset);
@@ -572,6 +594,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)/* Module is disabled, clocks are gated */ ctrl |=GPIO_MOD_CTRL_BIT ;__raw_writel (ctrl, reg); + bank->context.ctrl = ctrl; }_reset_gpio (bank, bank->chip.base + offset);
@@ -1157,7 +1180,6 @@ static int omap_gpio_resume(struct device *dev) } -static void omap_gpio_save_context (struct gpio_bank *bank);static void omap_gpio_restore_context (struct gpio_bank *bank);static int omap_gpio_runtime_suspend (struct device *dev)
@@ -1170,7 +1192,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)spin_lock_irqsave (&bank->lock, flags);if (bank->power_mode !=OFF_MODE ) { bank->power_mode =0 ; - goto save_gpio_context; + goto update_gpio_context_count; }/* * If going to OFF, remove triggering for all
@@ -1178,7 +1200,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)* generated. See OMAP2420 Errata item 1.101. */ if (!(bank->enabled_non_wakeup_gpios)) - goto save_gpio_context; + goto update_gpio_context_count; bank->saved_datain =__raw_readl (bank->base + bank->regs->datain);
@@ -1195,12 +1217,11 @@ static int omap_gpio_runtime_suspend(struct device *dev) bank->workaround_enabled = true; -save_gpio_context: +update_gpio_context_count:if (bank->get_context_loss_count) bank->context_loss_count = bank->get_context_loss_count (bank->dev); -omap_gpio_save_context (bank);_gpio_dbck_disable (bank);spin_unlock_irqrestore (&bank->lock, flags);
@@ -1319,27 +1340,6 @@ void omap2_gpio_resume_after_idle(void) } } -static void omap_gpio_save_context (struct gpio_bank *bank) -{ - bank->context.irqenable1 = -__raw_readl (bank->base + bank->regs->irqenable); - bank->context.irqenable2 = -__raw_readl (bank->base + bank->regs->irqenable2); - bank->context.wake_en = -__raw_readl (bank->base + bank->regs->wkup_en); - bank->context.ctrl =__raw_readl (bank->base + bank->regs->ctrl); - bank->context.oe =__raw_readl (bank->base + bank->regs->direction); - bank->context.leveldetect0 = -__raw_readl (bank->base + bank->regs->leveldetect0); - bank->context.leveldetect1 = -__raw_readl (bank->base + bank->regs->leveldetect1); - bank->context.risingdetect = -__raw_readl (bank->base + bank->regs->risingdetect); - bank->context.fallingdetect = -__raw_readl (bank->base + bank->regs->fallingdetect); - bank->context.dataout =__raw_readl (bank->base + bank->regs->dataout); -} -static void omap_gpio_restore_context (struct gpio_bank *bank) { __raw_writel(bank->context.irqenable1,
Signature · 1 line
1.7.0.4
PATCH v9 22/25 gpio/omap: save and restore debounce registers
In reply to Tarun Kanti DebBarmaFrom: Nishanth Menon <[email protected]>
GPIO debounce registers need to be saved and restored for proper functioning of driver.
tarun.kanti at ti.com: Debounce context save is moved to _set_gpio_debounce() as part of dynamic context save to remove overhead.
--- drivers/gpio/gpio-omap.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)
drivers/gpio/gpio-omap.c +12 -0
@@ -44,6 +44,8 @@ struct gpio_regs {u32 risingdetect;u32 fallingdetect;u32 dataout; +u32 debounce; +u32 debounce_en; };struct gpio_bank {
@@ -229,6 +231,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,* that point. Therefore we have to enable dbck here. */ _gpio_dbck_enable (bank); +if (bank->dbck_enable_mask) { + bank->context.debounce = debounce; + bank->context.debounce_en = val; + } } static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
@@ -1359,6 +1365,12 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)__raw_writel (bank->context.fallingdetect, bank->base + bank->regs->fallingdetect);__raw_writel (bank->context.dataout, bank->base + bank->regs->dataout); +if (bank->dbck_enable_mask) { +__raw_writel (bank->context.debounce, bank->base + + bank->regs->debounce); +__raw_writel (bank->context.debounce_en, + bank->base + bank->regs->debounce_en); + } }#else #define omap_gpio_suspend NULL
Signature · 1 line
1.7.0.4
PATCH v9 23/25 gpio/omap: enable irq at the end of all configuration in restore
In reply to Tarun Kanti DebBarmaFrom: Nishanth Menon <[email protected]>
Setup the interrupt enable registers only after we have configured the required edge and required configurations, not before, to prevent spurious events as part of restore routine.
--- drivers/gpio/gpio-omap.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-)
drivers/gpio/gpio-omap.c +5 -4
@@ -1348,10 +1348,6 @@ void omap2_gpio_resume_after_idle(void)static void omap_gpio_restore_context (struct gpio_bank *bank) { -__raw_writel (bank->context.irqenable1, - bank->base + bank->regs->irqenable); -__raw_writel (bank->context.irqenable2, - bank->base + bank->regs->irqenable2);__raw_writel (bank->context.wake_en, bank->base + bank->regs->wkup_en);__raw_writel (bank->context.ctrl, bank->base + bank->regs->ctrl);
@@ -1371,6 +1367,11 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)__raw_writel (bank->context.debounce_en, bank->base + bank->regs->debounce_en); } + +__raw_writel (bank->context.irqenable1, + bank->base + bank->regs->irqenable); +__raw_writel (bank->context.irqenable2, + bank->base + bank->regs->irqenable2); }#else #define omap_gpio_suspend NULL
Signature · 1 line
1.7.0.4
PATCH v9 24/25 gpio/omap: restore OE only after setting the output level
In reply to Tarun Kanti DebBarmaFrom: Nishanth Menon <[email protected]>
Setup the dataout register before restoring OE. This is to make sure that we have valid data in dataout register which would be made available in output pins as soon as OE is enabled. Else, there is risk of unknown data getting out into gpio pins.
--- drivers/gpio/gpio-omap.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
drivers/gpio/gpio-omap.c +2 -1
@@ -1351,7 +1351,6 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)__raw_writel (bank->context.wake_en, bank->base + bank->regs->wkup_en);__raw_writel (bank->context.ctrl, bank->base + bank->regs->ctrl); -__raw_writel (bank->context.oe, bank->base + bank->regs->direction);__raw_writel (bank->context.leveldetect0, bank->base + bank->regs->leveldetect0); __raw_writel(bank->context.leveldetect1,
@@ -1361,6 +1360,8 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)__raw_writel (bank->context.fallingdetect, bank->base + bank->regs->fallingdetect);__raw_writel (bank->context.dataout, bank->base + bank->regs->dataout); +__raw_writel (bank->context.oe, bank->base + bank->regs->direction); +if (bank->dbck_enable_mask) {__raw_writel (bank->context.debounce, bank->base + bank->regs->debounce);
Signature · 1 line
1.7.0.4
PATCH v9 25/25 gpio/omap: handle set_dataout reg capable IP on restore
In reply to Tarun Kanti DebBarmaFrom: Nishanth Menon <[email protected]>
GPIO IP revisions such as those used in OMAP4 have a set_dataout while the previous revisions used a single dataout register. Depending on what is available restore the dataout settings to the right register.
--- drivers/gpio/gpio-omap.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
drivers/gpio/gpio-omap.c +6 -1
@@ -1359,7 +1359,12 @@ static void omap_gpio_restore_context(struct gpio_bank *bank) bank->base + bank->regs->risingdetect);__raw_writel (bank->context.fallingdetect, bank->base + bank->regs->fallingdetect); -__raw_writel (bank->context.dataout, bank->base + bank->regs->dataout); +if (bank->regs->set_dataout && bank->regs->clr_dataout) +__raw_writel (bank->context.dataout, + bank->base + bank->regs->set_dataout); +else +__raw_writel (bank->context.dataout, + bank->base + bank->regs->dataout);__raw_writel (bank->context.oe, bank->base + bank->regs->direction);if (bank->dbck_enable_mask) {
Signature · 1 line
1.7.0.4
v9 cover gpio/omap: driver cleanup and fixes
In reply to Tarun Kanti DebBarmaHi Tarun,
Quoted 5 lines · Tarun Kanti DebBarma
This series is continuation of cleanup of OMAP GPIO driver and fixes. The cleanup include getting rid of cpu_is_* checks wherever possible, use of
gpio_banklist instead of static array, use of unique platform specific value associated data member to OMAP platforms to avoid cpu_is_* checks. The series also include PM runtime support.
Since this is now a "real" driver under drivers, please repost this including the GPIO maintainer (Grant Likely <[email protected]>) and LKML.
Also, for ease of testing with all the other OMAP features that are already queued for upstream, please rebase on top of Tony's 'uart' branch.
After the above, I will do some final testing and queue a branch for Grant, but it's too late for the v3.3 merge window, but we'll get this into v3.4. We'll also get it into Tony's "testing" branch so it can see some broader testing as well.
Thanks,
Kevin