Add XOR engine support to Armada 3700 SoC (ARM64)

Hi,

This series adds the support of the Marvell XOR engine to the Armada 3700 SoC. As this SoC is an ARM64 one, then the code has been fixed to support the 64 bits platform.

The initialization for the Armada 3700 is different from the other SoCs, so in order to support it, a new way of handling the different family have been added.

Once the dmaengine part will be approved, I will apply the dts part in the mvebu/dt64 tree.

In this fourth series I took into account the remarks from Vinoud, I also updated the dts patch that I will apply on my tree.

Thanks,

Gregory

Changelog:
v3 -> v4:
- Fix more typo in commit log of patch 3
- Add the warning fixed by patch 1
- Rebased the dt patch onto mvebu/dt64

v2 -> v3:
- Add COMPILE_TEST dependency

v1 ->v2:
- Fix typo in commit log of patch 3
- Reformatting to 1 compatible string per line in Documentation/devicetree/bindings/dma/mv-xor.txt
- Added Acked-by from Rob in patch 3

Gregory CLEMENT (4):
dmaengine: mv_xor: make the code 64 bits compliant
dmaengine: mv_xor: use SoC type instead of directly the operation mode
dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible
SoC
arm64: dts: marvell: add XOR node for Armada 3700 SoC

Marcin Wojtas (1):
dmaengine: mv_xor: add support for Armada 3700 SoC

 Documentation/devicetree/bindings/dma/mv-xor.txt |  5 +-
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi     | 13 ++++
 drivers/dma/Kconfig                              |  2 +-
 drivers/dma/mv_xor.c                             | 98 +++++++++++++++++++-----
 drivers/dma/mv_xor.h                             |  1 +
 5 files changed, 97 insertions(+), 22 deletions(-)

2.5.0

Fix two warnings which appear when building for 64 bits target:

drivers/dma/mv_xor.c: In function ?mv_xor_prep_dma_xor?:
drivers/dma/mv_xor.c:480:3: warning: format ?%u? expects argument of type ?unsigned int?, but argument 6 has type ?size_t {aka long unsigned int}? [-Wformat=]
"%s src_cnt: %d len: %u dest %pad flags: %ld\n",
^
drivers/dma/mv_xor.c: In function ?mv_xor_probe?:
drivers/dma/mv_xor.c:1223:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

    op_in_desc = (int)of_id->data;
                 ^

---
 drivers/dma/mv_xor.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 3922a5d56806..a6ec82776cbc 100644
@@ -477,7 +477,7 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 	BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
 
 	dev_dbg(mv_chan_to_devp(mv_chan),
-		"%s src_cnt: %d len: %u dest %pad flags: %ld\n",
+		"%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
 		__func__, src_cnt, len, &dest, flags);
 
 	sw_desc = mv_chan_alloc_slot(mv_chan);

@@ -1220,7 +1220,7 @@ static int mv_xor_probe(struct platform_device *pdev)
 			struct mv_xor_chan *chan;
 			dma_cap_mask_t cap_mask;
 			int irq;
-			op_in_desc = (int)of_id->data;
+			op_in_desc = (uintptr_t)of_id->data;
 
 			if (i >= max_channels)
 				continue;

2.5.0

Currently the main difference between legacy XOR engine and newer one, is the way the engine modes are setup (either in the descriptor or through the controller registers). In order to be able to take into account new generation of the XOR engine for the ARM64 SoC, we need to identify them by type, and then depending to the type the engine setup will be selected.

---
 drivers/dma/mv_xor.c | 40 ++++++++++++++++++++++++++++------------
 drivers/dma/mv_xor.h |  1 +
 2 files changed, 29 insertions(+), 12 deletions(-)

index a6ec82776cbc..6d012a56b97b 100644
@@ -31,6 +31,11 @@
 #include "dmaengine.h"
 #include "mv_xor.h"
 
+enum mv_xor_type {
+	XOR_ORION,
+	XOR_ARMADA_38X,
+};
+
 enum mv_xor_mode {
 	XOR_MODE_IN_REG,
 	XOR_MODE_IN_DESC,

@@ -933,7 +938,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
 static struct mv_xor_chan *
 mv_xor_channel_add(struct mv_xor_device *xordev,
 		   struct platform_device *pdev,
-		   int idx, dma_cap_mask_t cap_mask, int irq, int op_in_desc)
+		   int idx, dma_cap_mask_t cap_mask, int irq)
 {
 	int ret = 0;
 	struct mv_xor_chan *mv_chan;

@@ -945,7 +950,10 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
 
 	mv_chan->idx = idx;
 	mv_chan->irq = irq;
-	mv_chan->op_in_desc = op_in_desc;
+	if (xordev->xor_type == XOR_ORION)
+		mv_chan->op_in_desc = XOR_MODE_IN_REG;
+	else
+		mv_chan->op_in_desc = XOR_MODE_IN_DESC;
 
 	dma_dev = &mv_chan->dmadev;
 

@@ -1137,8 +1145,8 @@ static int mv_xor_resume(struct platform_device *dev)
 }
 
 static const struct of_device_id mv_xor_dt_ids[] = {
-	{ .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG },
-	{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC },
+	{ .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
+	{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
 	{},
 };
 

@@ -1152,7 +1160,6 @@ static int mv_xor_probe(struct platform_device *pdev)
 	struct resource *res;
 	unsigned int max_engines, max_channels;
 	int i, ret;
-	int op_in_desc;
 
 	dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
 

@@ -1180,6 +1187,20 @@ static int mv_xor_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, xordev);
 
+
+	/*
+	 * We need to know which type of XOR device we use before
+	 * setting up. In non-dt case it can only be the legacy one.
+	 */
+	xordev->xor_type = XOR_ORION;
+	if (pdev->dev.of_node) {
+		const struct of_device_id *of_id =
+			of_match_device(mv_xor_dt_ids,
+					&pdev->dev);
+
+		xordev->xor_type = (uintptr_t)of_id->data;
+	}
+
 	/*
 	 * (Re-)program MBUS remapping windows if we are asked to.
 	 */

@@ -1212,15 +1233,11 @@ static int mv_xor_probe(struct platform_device *pdev)
 	if (pdev->dev.of_node) {
 		struct device_node *np;
 		int i = 0;
-		const struct of_device_id *of_id =
-			of_match_device(mv_xor_dt_ids,
-					&pdev->dev);
 
 		for_each_child_of_node(pdev->dev.of_node, np) {
 			struct mv_xor_chan *chan;
 			dma_cap_mask_t cap_mask;
 			int irq;
-			op_in_desc = (uintptr_t)of_id->data;
 
 			if (i >= max_channels)
 				continue;

@@ -1237,7 +1254,7 @@ static int mv_xor_probe(struct platform_device *pdev)
 			}
 
 			chan = mv_xor_channel_add(xordev, pdev, i,
-						  cap_mask, irq, op_in_desc);
+						  cap_mask, irq);
 			if (IS_ERR(chan)) {
 				ret = PTR_ERR(chan);
 				irq_dispose_mapping(irq);

@@ -1266,8 +1283,7 @@ static int mv_xor_probe(struct platform_device *pdev)
 			}
 
 			chan = mv_xor_channel_add(xordev, pdev, i,
-						  cd->cap_mask, irq,
-						  XOR_MODE_IN_REG);
+						  cd->cap_mask, irq);
 			if (IS_ERR(chan)) {
 				ret = PTR_ERR(chan);
 				goto err_channel_add;

index c19fe30e5ae9..bf56e082e7cd 100644
@@ -85,6 +85,7 @@ struct mv_xor_device {
 	void __iomem	     *xor_high_base;
 	struct clk	     *clk;
 	struct mv_xor_chan   *channels[MV_XOR_MAX_CHANNELS];
+	int		     xor_type;
 };
 
 /**

2.5.0

From: Marcin Wojtas <[email protected]>

Armada 3700 SoC comprise a single XOR engine compliant with the ones used in older Marvell SoC's like Armada XP or 38x. The only thing that needs modification is the Mbus configuration, which has to be done on two
levels: global and in device. The first one is inherited from the bootloader. The latter can be opened in a default way, leaving arbitration to the bus controller. Hence filled mbus_dram_target_info structure is not needed.

Patch "dmaengine: mv_xor: optimize performance by using a subset of the XOR channels" introduced limitation for using XOR engines and channels vs number of available CPU's. Those constraints do not however fit Armada 3700 architecture with two possible CPU's and single, dual-channel engine. Hence in this commit an adjustment for setting maximum available channels is added.

This patch enables XOR access to DRAM by opening default window to 4GB space with specific attribute.

---
 Documentation/devicetree/bindings/dma/mv-xor.txt |  5 ++-
 drivers/dma/mv_xor.c                             | 56 +++++++++++++++++++++---
 2 files changed, 53 insertions(+), 8 deletions(-)

index 276ef815ef32..c075f5988135 100644
@@ -1,7 +1,10 @@
 * Marvell XOR engines
 
 Required properties:
-- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"
+- compatible: Should be one of the following:
+  - "marvell,orion-xor"
+  - "marvell,armada-380-xor"
+  - "marvell,armada-3700-xor".
 - reg: Should contain registers location and length (two sets)
     the first set is the low registers, the second set the high
     registers for the XOR engine.

2.5.0

Armada 3700 SoC uses the mv_xor driver but don't select anymore the PLAT_ORION symbol. This commit extends the dependency of the mv_xor driver to the more modern SoCs only compatible with ARCH_MVEBU, which allows using it with the Armada 3700 SoC.

In the same time it also add the COMPILE_TEST dependency allowing a wider test coverage.

---
 drivers/dma/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index d96d87c56f2e..67b37ce94143 100644
@@ -332,7 +332,7 @@ config MPC512X_DMA
 
 config MV_XOR
 	bool "Marvell XOR engine support"
-	depends on PLAT_ORION
+	depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
 	select DMA_ENGINE
 	select DMA_ENGINE_RAID
 	select ASYNC_TX_ENABLE_CHANNEL_SWITCH

2.5.0

Armada 3700 SoC comprise one dual-channel XOR engine and this patch adds its according representation.

---
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

index 1d4fb4d27787..9e2efb882983 100644
@@ -113,6 +113,19 @@
 				status = "disabled";
 			};
 
+			xor at 60900 {
+				compatible = "marvell,armada-3700-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+
+				xor10 {
+					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				};
+				xor11 {
+					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
 			sata: sata at e0000 {
 				compatible = "marvell,armada-3700-ahci";
 				reg = <0xe0000 0x2000>;

2.5.0

Hi,

I applied this patch on mvebu/dt64 (the new binding was appouved since the v3).

Gregory

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Applied, 1 thru 4.

~Vinod