mips: Fix BC1ANY[24]F instructions
PATCH 1/1 mips: Fix BC1ANY[24]F instructions
There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests.
--- target-mips/translate.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
target-mips/translate.c +4 -4
@@ -6017,7 +6017,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,TCGv_i32 t1 =tcg_temp_new_i32 ();tcg_gen_shri_i32 (t0, fpu_fcr31,get_fp_bit (cc));tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+1 )); -tcg_gen_nor_i32 (t0, t0, t1); +tcg_gen_nand_i32 (t0, t0, t1);tcg_temp_free_i32 (t1);tcg_gen_andi_i32 (t0, t0,1 );tcg_gen_extu_i32_tl (bcond, t0);
@@ -6041,11 +6041,11 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,TCGv_i32 t1 =tcg_temp_new_i32 ();tcg_gen_shri_i32 (t0, fpu_fcr31,get_fp_bit (cc));tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+1 )); -tcg_gen_or_i32 (t0, t0, t1); +tcg_gen_and_i32 (t0, t0, t1);tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+2 )); -tcg_gen_or_i32 (t0, t0, t1); +tcg_gen_and_i32 (t0, t0, t1);tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+3 )); -tcg_gen_nor_i32 (t0, t0, t1); +tcg_gen_nand_i32 (t0, t0, t1);tcg_temp_free_i32 (t1);tcg_gen_andi_i32 (t0, t0,1 );tcg_gen_extu_i32_tl (bcond, t0);
Signature · 1 line
1.7.2.5
Am 26.11.2011 14:37, schrieb Richard Sandiford:
Quoted 10 lines
There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests.
Signed-off-by Richard Sandiford <[email protected]>--- target-mips/translate.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
Ping! Patch has a Reviewed-by. Anthony or Blue, can you apply for 1.1?
http://patchwork.ozlabs.org/patch/127798/
/-F
Quoted 28 lines
target-mips/translate.c +4
-4@@ -6017,7 +6017,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,TCGv_i32 t1 =tcg_temp_new_i32 ();tcg_gen_shri_i32 (t0, fpu_fcr31,get_fp_bit (cc));tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+1 )); -tcg_gen_nor_i32 (t0, t0, t1); +tcg_gen_nand_i32 (t0, t0, t1);tcg_temp_free_i32 (t1);tcg_gen_andi_i32 (t0, t0,1 );tcg_gen_extu_i32_tl (bcond, t0);@@ -6041,11 +6041,11 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,TCGv_i32 t1 =tcg_temp_new_i32 ();tcg_gen_shri_i32 (t0, fpu_fcr31,get_fp_bit (cc));tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+1 )); -tcg_gen_or_i32 (t0, t0, t1); +tcg_gen_and_i32 (t0, t0, t1);tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+2 )); -tcg_gen_or_i32 (t0, t0, t1); +tcg_gen_and_i32 (t0, t0, t1);tcg_gen_shri_i32 (t1, fpu_fcr31,get_fp_bit (cc+3 )); -tcg_gen_nor_i32 (t0, t0, t1); +tcg_gen_nand_i32 (t0, t0, t1);tcg_temp_free_i32 (t1);tcg_gen_andi_i32 (t0, t0,1 );tcg_gen_extu_i32_tl (bcond, t0);
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Blue Swirl
AppliedThanks, applied.
Quoted 50 lines · Andreas Färber
Am 26.11.2011 14:37, schrieb Richard Sandiford:
Quoted 10 lines
There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests.
Signed-off-by Richard Sandiford <[email protected]>---
target-mips/translate.c | 8 ++++----1 files changed, 4 insertions(+), 4 deletions(-)Ping! Patch has a Reviewed-by. Anthony or Blue, can you apply for 1.1?
http://patchwork.ozlabs.org/patch/127798/
/-F
Quoted 18 lines
target-mips/translate.c +1
-2@@ -6017,7 +6017,7 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_nor_i32(t0, t0, t1); + tcg_gen_nand_i32(t0, t0, t1); tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0);@@ -6041,11 +6041,11 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_or_i32(t0, t0, t1);target-mips/translate.c static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, · line 6051
Quoted 10 lines
target-mips/translate.c +3
-2+ tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); - tcg_gen_nor_i32(t0, t0, t1); + tcg_gen_nand_i32(t0, t0, t1); tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0);--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg