mpc83xx: set gpio level before direction

Set gpio level register before direction register to inhibit glitches on high level output pins.

Dir and data gets cleared at powerup, so high level output lines see a short low pulse between setting the direction and level registers.

Issue was seen on a new board with the nReset line of the NOR flash connected to a GPIO. Setting the direction register puts the NOR flash in reset so the next instruction to set the level cannot get executed.

---
 cpu/mpc83xx/cpu_init.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

index 67c9e57..4514dbb 100644
@@ -283,12 +283,12 @@ void cpu_init_f (volatile immap_t * im)
 	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
 #endif
 #ifdef CFG_GPIO1_PRELIM
-	im->gpio[0].dir = CFG_GPIO1_DIR;
 	im->gpio[0].dat = CFG_GPIO1_DAT;
+	im->gpio[0].dir = CFG_GPIO1_DIR;
 #endif
 #ifdef CFG_GPIO2_PRELIM
-	im->gpio[1].dir = CFG_GPIO2_DIR;
 	im->gpio[1].dat = CFG_GPIO2_DAT;
+	im->gpio[1].dir = CFG_GPIO2_DIR;
 #endif
 }
 

1.5.6.3

Hi Peter,

this is a duplicate of:

http://www.nabble.com/-U-Boot---PATCH--MPC83XX%3A-Fix-GPIO-configuration-to19119329.html#a19119329

so I'll merge your better description and s-o-b to that one if you don't mind.

Kim

Kim> this is a duplicate of:

Ahh sorry, I must have missed that one.

Kim> so I'll merge your better description and s-o-b to that one if you Kim> don't mind.

Yeah, that's fine.

Bye, Peter Korsgaard