enable HiP04 SoC

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               | 10 +++++++++-
 arch/arm/mach-berlin/Kconfig   |  2 +-
 arch/arm/mach-highbank/Kconfig |  2 +-
 arch/arm/mach-mvebu/Kconfig    |  4 ++--
 arch/arm/mach-omap2/Kconfig    |  4 ++--
 arch/arm/mach-qcom/Kconfig     |  2 +-
 arch/arm/mach-shmobile/Kconfig |  2 +-
 arch/arm/mach-tegra/Kconfig    |  2 +-
 arch/arm/mach-vexpress/Kconfig |  2 +-
 9 files changed, 19 insertions(+), 11 deletions(-)

arch/arm/Kconfig +0 -0

index ab438cb..5ef96ea 100644

arch/arm/Kconfig +1 -0

+
 config ARCH_MULTI_V6_V7
        bool
        select MIGHT_HAVE_CACHE_L2X0

arch/arm/mach-berlin/Kconfig +1 -1

index b0cb072..be0512d 100644
@@ -1,5 +1,5 @@
 config ARCH_BERLIN
-       bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
+       bool "Marvell Berlin SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V7_LPAE)
        select ARM_GIC
        select GENERIC_IRQ_CHIP
        select DW_APB_ICTL

arch/arm/mach-highbank/Kconfig +0 -0

index 830b76e..9b6b3f8 100644

arch/arm/mach-highbank/Kconfig +0 -0

        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL

arch/arm/mach-mvebu/Kconfig +2 -2

index 3f73eec..0d54d1a 100644
@@ -1,5 +1,5 @@
 config ARCH_MVEBU
-       bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5)
+       bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V7_LPAE || ARCH_MULTI_V5)
        select ARCH_SUPPORTS_BIG_ENDIAN
        select CLKSRC_MMIO
        select GENERIC_IRQ_CHIP

@@ -59,7 +59,7 @@ config MACH_ARMADA_38X
          on the Marvell Armada 380/385 SoC with device tree.
 
 config MACH_ARMADA_XP
-       bool "Marvell Armada XP boards" if ARCH_MULTI_V7
+       bool "Marvell Armada XP boards" if ARCH_MULTI_V7_LPAE
        select ARMADA_XP_CLK
        select CPU_PJ4B
        select MACH_MVEBU_V7

arch/arm/mach-omap2/Kconfig +0 -0

index cb31d43..1958791 100644

Bit[9:0] is interrupt ID field in GICC_IAR. Bit[12:10] is CPU ID field, and others are reserved.

So we should use GICC_IAR_INTID to get interrupt ID. It's not a good way to use ~0x1c00 (CPU ID field) to get interrupt ID.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/irq-gic.c       | 2 +-
 include/linux/irqchip/arm-gic.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

drivers/irqchip/irq-gic.c +1 -1

index 4300b66..8fd27bf 100644
@@ -287,7 +287,7 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 
 	do {
 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
-		irqnr = irqstat & ~0x1c00;
+		irqnr = irqstat & GICC_IAR_INTID;
 
 		if (likely(irqnr > 15 && irqnr < 1021)) {
 			irqnr = irq_find_mapping(gic->domain, irqnr);

include/linux/irqchip/arm-gic.h +0 -0

index 7ed92d0..55933aa 100644

There's a little difference between ARM GIC and HiP04 GIC.

* HiP04 GIC could support 16 cores at most, and ARM GIC could support 8 cores at most. So the difination on GIC_DIST_SGIR, GIC_DIST_SGI_PENDING_SET, GIC_DIST_SGI_PENDING_CLEAR
& GIC_DIST_TARGET registers are different since CPU interfaces are increased from 8-bit to 16-bit.

* HiP04 GIC could support 510 interrupts at most, and ARM GIC could support 1020 interrupts at most.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/irq-gic.c | 155 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 122 insertions(+), 33 deletions(-)

drivers/irqchip/irq-gic.c +5 -2

index 8fd27bf..793b4fe 100644
@@ -68,6 +68,7 @@ struct gic_chip_data {
 #ifdef CONFIG_GIC_NON_BANKED
        void __iomem *(*get_base)(union gic_base *);
 #endif
+       u32 nr_cpu_if;
 };
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);

@@ -76,9 +77,11 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  * The GIC mapping of CPU interfaces does not necessarily match
  * the logical CPU numbering.  Let's use a mapping as returned
  * by the GIC itself.
+ *
+ * Hisilicon HiP04 extends the number of CPU interface from 8 to 16.
  */
-#define NR_GIC_CPU_IF 8
-static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+#define NR_GIC_CPU_IF  16
+static u16 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 
 /*
  * Supported arch specific GIC irq extension.

drivers/irqchip/irq-gic.c +25 -2

+}
+
+static inline u32 irq_to_core_shift(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       unsigned int i = gic_irq(d);
+
+       /* ARM GIC */
+       if (gic_data->nr_cpu_if == 8)
+               return ((i % 4) << 3);
+       /* HiP04 GIC (nr_cpu_if == 16) */
+       return ((i % 2) << 4);
+}
+
+static inline u32 irq_to_core_mask(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       u32 mask;
+       /* ARM GIC, nr_cpu_if == 8; HiP04 GIC, nr_cpu_if == 16 */
+       mask = (1 << gic_data->nr_cpu_if) - 1;
+       return (mask << irq_to_core_shift(d));
+}
+
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-       unsigned int shift = (gic_irq(d) % 4) * 8;
+       void __iomem *reg;
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic.c +5 -6

        raw_spin_lock(&irq_controller_lock);
-       mask = 0xff << shift;
+       mask = irq_to_core_mask(d);
        bit = gic_cpu_map[cpu] << shift;
        val = readl_relaxed(reg) & ~mask;
        writel_relaxed(val | bit, reg);

@@ -354,15 +393,24 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
-static u8 gic_get_cpumask(struct gic_chip_data *gic)
+static u16 gic_get_cpumask(struct gic_chip_data *gic)
 {
        void __iomem *base = gic_data_dist_base(gic);
        u32 mask, i;
 
-       for (i = mask = 0; i < 32; i += 4) {
-               mask = readl_relaxed(base + GIC_DIST_TARGET + i);
-               mask |= mask >> 16;
-               mask |= mask >> 8;
+       /*
+        * ARM GIC uses 8 registers for interrupt 0-31,
+        * HiP04 GIC uses 16 registers for interrupt 0-31.

drivers/irqchip/irq-gic.c +4 -0

                if (mask)
                        break;
        }

@@ -370,6 +418,10 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
        if (!mask)
                pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 
+       /* ARM GIC needs 8-bit cpu mask, HiP04 GIC needs 16-bit cpu mask. */
+       if (gic->nr_cpu_if == 8)
+               mask &= 0xff;
+
        return mask;
 }
 

@@ -392,10 +444,20 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         * Set all global interrupts to this CPU only.
         */
        cpumask = gic_get_cpumask(gic);

drivers/irqchip/irq-gic.c +3 -2

+       }
 
        /*
         * Set priority on all global interrupts.

@@ -423,7 +485,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Get what the GIC says our CPU mask is.
         */
-       BUG_ON(cpu >= NR_GIC_CPU_IF);
+       BUG_ON(cpu >= gic->nr_cpu_if);
        cpu_mask = gic_get_cpumask(gic);
        gic_cpu_map[cpu] = cpu_mask;
 

@@ -431,7 +493,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
         * Clear our mask from the other map entries in case they're
         * still undefined.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
+       for (i = 0; i < gic->nr_cpu_if; i++)
                if (i != cpu)
                        gic_cpu_map[i] &= ~cpu_mask;
 

drivers/irqchip/irq-gic.c +1 -1

        void __iomem *dist_base;
        int i;
 

@@ -484,7 +546,7 @@ static void gic_dist_save(unsigned int gic_nr)
                gic_data[gic_nr].saved_spi_conf[i] =
                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                gic_data[gic_nr].saved_spi_target[i] =
                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 

drivers/irqchip/irq-gic.c +39 -13

        unsigned int i;
        void __iomem *dist_base;
 

@@ -525,7 +587,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                writel_relaxed(0xa0a0a0a0,
                        dist_base + GIC_DIST_PRI + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
                        dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -665,9 +727,19 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
         */
        dmb(ishst);
 
-       /* this always happens on GIC0 */
-       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
-
+       /*
+        * CPUTargetList -- bit[23:16] in GIC_DIST_SOFTINT in ARM GIC.
+        *                  bit[23:8] in GIC_DIST_SOFTINT in HiP04 GIC.
+        * NSATT -- bit[15] in GIC_DIST_SOFTINT in ARM GIC.
+        *          bit[7] in GIC_DIST_SOFTINT in HiP04 GIC.
+        * this always happens on GIC0
+        */
+       if (gic_data[0].nr_cpu_if == 8)
+               map = map << 16;
+       else
+               map = map << 8;
+       writel_relaxed(map | irq,
+                      gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
        raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 #endif

@@ -681,10 +753,15 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
  */
 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 {
-       BUG_ON(cpu_id >= NR_GIC_CPU_IF);
+       BUG_ON(cpu_id >= gic_data[0].nr_cpu_if);
        cpu_id = 1 << cpu_id;
        /* this always happens on GIC0 */
-       writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+       if (gic_data[0].nr_cpu_if == 8)
+               cpu_id = cpu_id << 16;
+       else
+               cpu_id = cpu_id << 8;
+       writel_relaxed(cpu_id | irq,
+                      gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 }
 
 /*

@@ -700,7 +777,7 @@ int gic_get_cpu_id(unsigned int cpu)
 {
        unsigned int cpu_bit;
 
-       if (cpu >= NR_GIC_CPU_IF)
+       if (cpu >= gic_data[0].nr_cpu_if)
                return -1;
        cpu_bit = gic_cpu_map[cpu];
        if (cpu_bit & (cpu_bit - 1))

@@ -931,7 +1008,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
        irq_hw_number_t hwirq_base;
        struct gic_chip_data *gic;
        int gic_irqs, irq_base, i;
-       int nr_routable_irqs;
+       int nr_routable_irqs, max_nr_irq;
 
        BUG_ON(gic_nr >= MAX_GIC_NR);
 

@@ -967,12 +1044,22 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                gic_set_base_accessor(gic, gic_get_common_base);
        }
 
+       if (of_device_is_compatible(node, "hisilicon,hip04-gic")) {
+               /* HiP04 GIC supports 16 CPUs at most */
+               gic->nr_cpu_if = 16;
+               max_nr_irq = 510;
+       } else {
+               /* ARM/Qualcomm GIC supports 8 CPUs at most */
+               gic->nr_cpu_if = 8;
+               max_nr_irq = 1020;
+       }
+
        /*
         * Initialize the CPU interface map to all CPUs.
         * It will be refined as each CPU probes its ID.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               gic_cpu_map[i] = 0xff;
+       for (i = 0; i < gic->nr_cpu_if; i++)
+               gic_cpu_map[i] = (1 << gic->nr_cpu_if) - 1;
 
        /*
         * For primary GICs, skip over SGIs.

@@ -988,12 +1075,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 
        /*
         * Find out how many interrupts are supported.
-        * The GIC only supports up to 1020 interrupt sources.
+        * The ARM/Qualcomm GIC only supports up to 1020 interrupt sources.
+        * The HiP04 GIC only supports up to 510 interrupt sources.
         */
        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
-       if (gic_irqs > 1020)
-               gic_irqs = 1020;
+       if (gic_irqs > max_nr_irq)
+               gic_irqs = max_nr_irq;
        gic->gic_irqs = gic_irqs;
 
        gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */

There's a little difference between ARM GIC and HiP04 GIC.

* HiP04 GIC could support 16 cores at most, and ARM GIC could support 8 cores at most. So the difination on GIC_DIST_SGIR, GIC_DIST_SGI_PENDING_SET, GIC_DIST_SGI_PENDING_CLEAR
& GIC_DIST_TARGET registers are different since CPU interfaces are increased from 8-bit to 16-bit.

* HiP04 GIC could support 510 interrupts at most, and ARM GIC could support 1020 interrupts at most.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/irq-gic.c | 155 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 122 insertions(+), 33 deletions(-)

drivers/irqchip/irq-gic.c +122 -34

index 8fd27bf..793b4fe 100644
@@ -68,6 +68,7 @@ struct gic_chip_data {
 #ifdef CONFIG_GIC_NON_BANKED
        void __iomem *(*get_base)(union gic_base *);
 #endif
+       u32 nr_cpu_if;
 };
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);

@@ -76,9 +77,11 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  * The GIC mapping of CPU interfaces does not necessarily match
  * the logical CPU numbering.  Let's use a mapping as returned
  * by the GIC itself.
+ *
+ * Hisilicon HiP04 extends the number of CPU interface from 8 to 16.
  */
-#define NR_GIC_CPU_IF 8
-static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+#define NR_GIC_CPU_IF  16
+static u16 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 
 /*
  * Supported arch specific GIC irq extension.

@@ -242,19 +245,55 @@ static int gic_retrigger(struct irq_data *d)
 }
 
 #ifdef CONFIG_SMP
+static inline u32 irq_to_core_offset(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       unsigned int i = gic_irq(d);
+
+       /* ARM GIC */
+       if (gic_data->nr_cpu_if == 8)
+               return ((i >> 2) << 2);
+       /* HiP04 GIC (nr_cpu_if == 16) */
+       return ((i >> 1) << 2);
+}
+
+static inline u32 irq_to_core_shift(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       unsigned int i = gic_irq(d);
+
+       /* ARM GIC */
+       if (gic_data->nr_cpu_if == 8)
+               return ((i % 4) << 3);
+       /* HiP04 GIC (nr_cpu_if == 16) */
+       return ((i % 2) << 4);
+}
+
+static inline u32 irq_to_core_mask(struct irq_data *d)
+{
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       u32 mask;
+       /* ARM GIC, nr_cpu_if == 8; HiP04 GIC, nr_cpu_if == 16 */
+       mask = (1 << gic_data->nr_cpu_if) - 1;
+       return (mask << irq_to_core_shift(d));
+}
+
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-       unsigned int shift = (gic_irq(d) % 4) * 8;
+       void __iomem *reg;
+       struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+       unsigned int shift = irq_to_core_shift(d);
        unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
        u32 val, mask, bit;
 
-       if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
+       if (cpu >= gic_data->nr_cpu_if || cpu >= nr_cpu_ids)
                return -EINVAL;
 
+       reg = gic_dist_base(d) + GIC_DIST_TARGET + irq_to_core_offset(d);
+
        raw_spin_lock(&irq_controller_lock);
-       mask = 0xff << shift;
+       mask = irq_to_core_mask(d);
        bit = gic_cpu_map[cpu] << shift;
        val = readl_relaxed(reg) & ~mask;
        writel_relaxed(val | bit, reg);

@@ -354,15 +393,24 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
-static u8 gic_get_cpumask(struct gic_chip_data *gic)
+static u16 gic_get_cpumask(struct gic_chip_data *gic)
 {
        void __iomem *base = gic_data_dist_base(gic);
        u32 mask, i;
 
-       for (i = mask = 0; i < 32; i += 4) {
-               mask = readl_relaxed(base + GIC_DIST_TARGET + i);
-               mask |= mask >> 16;
-               mask |= mask >> 8;
+       /*
+        * ARM GIC uses 8 registers for interrupt 0-31,
+        * HiP04 GIC uses 16 registers for interrupt 0-31.
+        */
+       for (i = mask = 0; i < 32; i += 32 / gic->nr_cpu_if) {
+               if (gic->nr_cpu_if == 8) {      /* ARM GIC */
+                       mask = readl_relaxed(base + GIC_DIST_TARGET + i);
+                       mask |= mask >> 16;
+                       mask |= mask >> 8;
+               } else {                        /* HiP04 GIC */
+                       mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2);
+                       mask |= mask >> 16;
+               }
                if (mask)
                        break;
        }

@@ -370,6 +418,10 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
        if (!mask)
                pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
 
+       /* ARM GIC needs 8-bit cpu mask, HiP04 GIC needs 16-bit cpu mask. */
+       if (gic->nr_cpu_if == 8)
+               mask &= 0xff;
+
        return mask;
 }
 

@@ -392,10 +444,20 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         * Set all global interrupts to this CPU only.
         */
        cpumask = gic_get_cpumask(gic);
-       cpumask |= cpumask << 8;
-       cpumask |= cpumask << 16;
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+       if (gic->nr_cpu_if == 8) {      /* ARM GIC */
+               cpumask |= cpumask << 8;
+               cpumask |= cpumask << 16;
+       } else {                        /* HiP04 GIC */
+               cpumask |= cpumask << 16;
+       }
+       for (i = 32; i < gic_irqs; i += 32 / gic->nr_cpu_if) {
+               if (gic->nr_cpu_if == 8)
+                       writel_relaxed(cpumask,
+                                      base + GIC_DIST_TARGET + i / 4 * 4);
+               else
+                       writel_relaxed(cpumask,
+                                      base + GIC_DIST_TARGET + i / 2 * 4);
+       }
 
        /*
         * Set priority on all global interrupts.

@@ -423,7 +485,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Get what the GIC says our CPU mask is.
         */
-       BUG_ON(cpu >= NR_GIC_CPU_IF);
+       BUG_ON(cpu >= gic->nr_cpu_if);
        cpu_mask = gic_get_cpumask(gic);
        gic_cpu_map[cpu] = cpu_mask;
 

@@ -431,7 +493,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
         * Clear our mask from the other map entries in case they're
         * still undefined.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
+       for (i = 0; i < gic->nr_cpu_if; i++)
                if (i != cpu)
                        gic_cpu_map[i] &= ~cpu_mask;
 

@@ -467,7 +529,7 @@ void gic_cpu_if_down(void)
  */
 static void gic_dist_save(unsigned int gic_nr)
 {
-       unsigned int gic_irqs;
+       unsigned int gic_irqs, nr_if =  32 / gic_data[gic_nr].nr_cpu_if;
        void __iomem *dist_base;
        int i;
 

@@ -484,7 +546,7 @@ static void gic_dist_save(unsigned int gic_nr)
                gic_data[gic_nr].saved_spi_conf[i] =
                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                gic_data[gic_nr].saved_spi_target[i] =
                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -502,7 +564,7 @@ static void gic_dist_save(unsigned int gic_nr)
  */
 static void gic_dist_restore(unsigned int gic_nr)
 {
-       unsigned int gic_irqs;
+       unsigned int gic_irqs, nr_if = 32 / gic_data[gic_nr].nr_cpu_if;
        unsigned int i;
        void __iomem *dist_base;
 

@@ -525,7 +587,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                writel_relaxed(0xa0a0a0a0,
                        dist_base + GIC_DIST_PRI + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, nr_if); i++)
                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
                        dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -665,9 +727,19 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
         */
        dmb(ishst);
 
-       /* this always happens on GIC0 */
-       writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
-
+       /*
+        * CPUTargetList -- bit[23:16] in GIC_DIST_SOFTINT in ARM GIC.
+        *                  bit[23:8] in GIC_DIST_SOFTINT in HiP04 GIC.
+        * NSATT -- bit[15] in GIC_DIST_SOFTINT in ARM GIC.
+        *          bit[7] in GIC_DIST_SOFTINT in HiP04 GIC.
+        * this always happens on GIC0
+        */
+       if (gic_data[0].nr_cpu_if == 8)
+               map = map << 16;
+       else
+               map = map << 8;
+       writel_relaxed(map | irq,
+                      gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
        raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 #endif

@@ -681,10 +753,15 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
  */
 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 {
-       BUG_ON(cpu_id >= NR_GIC_CPU_IF);
+       BUG_ON(cpu_id >= gic_data[0].nr_cpu_if);
        cpu_id = 1 << cpu_id;
        /* this always happens on GIC0 */
-       writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+       if (gic_data[0].nr_cpu_if == 8)
+               cpu_id = cpu_id << 16;
+       else
+               cpu_id = cpu_id << 8;
+       writel_relaxed(cpu_id | irq,
+                      gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 }
 
 /*

@@ -700,7 +777,7 @@ int gic_get_cpu_id(unsigned int cpu)
 {
        unsigned int cpu_bit;
 
-       if (cpu >= NR_GIC_CPU_IF)
+       if (cpu >= gic_data[0].nr_cpu_if)
                return -1;
        cpu_bit = gic_cpu_map[cpu];
        if (cpu_bit & (cpu_bit - 1))

@@ -931,7 +1008,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
        irq_hw_number_t hwirq_base;
        struct gic_chip_data *gic;
        int gic_irqs, irq_base, i;
-       int nr_routable_irqs;
+       int nr_routable_irqs, max_nr_irq;
 
        BUG_ON(gic_nr >= MAX_GIC_NR);
 

@@ -967,12 +1044,22 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
                gic_set_base_accessor(gic, gic_get_common_base);
        }
 
+       if (of_device_is_compatible(node, "hisilicon,hip04-gic")) {
+               /* HiP04 GIC supports 16 CPUs at most */
+               gic->nr_cpu_if = 16;
+               max_nr_irq = 510;
+       } else {
+               /* ARM/Qualcomm GIC supports 8 CPUs at most */
+               gic->nr_cpu_if = 8;
+               max_nr_irq = 1020;
+       }
+
        /*
         * Initialize the CPU interface map to all CPUs.
         * It will be refined as each CPU probes its ID.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               gic_cpu_map[i] = 0xff;
+       for (i = 0; i < gic->nr_cpu_if; i++)
+               gic_cpu_map[i] = (1 << gic->nr_cpu_if) - 1;
 
        /*
         * For primary GICs, skip over SGIs.

@@ -988,12 +1075,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 
        /*
         * Find out how many interrupts are supported.
-        * The GIC only supports up to 1020 interrupt sources.
+        * The ARM/Qualcomm GIC only supports up to 1020 interrupt sources.
+        * The HiP04 GIC only supports up to 510 interrupt sources.
         */
        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
-       if (gic_irqs > 1020)
-               gic_irqs = 1020;
+       if (gic_irqs > max_nr_irq)
+               gic_irqs = max_nr_irq;
        gic->gic_irqs = gic_irqs;
 
        gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */

@@ -1069,6 +1157,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 }
 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+IRQCHIP_DECLARE(hip04_gic, "hisilicon,hip04-gic", gic_of_init);
 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
 
--

1.9.1

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Add the CONFIG_MCPM_QUAD_CLUSTER configuration to enlarge cluster number from 2 to 4.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig            | 6 ++++++
 arch/arm/include/asm/mcpm.h | 5 +++++
 2 files changed, 11 insertions(+)

arch/arm/Kconfig +0 -0

index 5ef96ea..58e995d 100644

Hisilicon Hi3xxx is based on Cortex A9 Core. Now HiP04 SoC is based on Cortex A15 Core. Since multiple clusters is used in HiP04 SoC, it could be based on MCPM.

And HiP04 supports LPAE to support large memory.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               |   2 +-
 arch/arm/mach-hisi/Kconfig     |  10 +-
 arch/arm/mach-hisi/Makefile    |   1 +
 arch/arm/mach-hisi/core.h      |   2 +
 arch/arm/mach-hisi/hisilicon.c |  12 ++
 arch/arm/mach-hisi/platmcpm.c  | 318 +++++++++++++++++++++++++++++++++++++++++
 6 files changed, 343 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-hisi/platmcpm.c

arch/arm/mach-hisi/hisilicon.c +0 -0

index 741faf3..6489e57 100644

arch/arm/mach-hisi/hisilicon.c +0 -0

@@ -0,0 +1,318 @@

arch/arm/mach-hisi/hisilicon.c +6 -0

+static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned long data, mask;
+
+	if (!relocation || !sysctrl)
+		return -ENODEV;

arch/arm/mach-hisi/hisilicon.c +202 -0

+		do {
+			mask = CLUSTER_L2_RESET_STATUS | \
+			       CLUSTER_DEBUG_RESET_STATUS;
+			data = readl_relaxed(sysctrl + \
+					     SC_CPU_RESET_STATUS(cluster));
+		} while (data & mask);
+		hip04_set_snoop_filter(cluster, 1);
+	}
+
+	hip04_cpu_table[cluster][cpu]++;
+
+	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+	       CORE_DEBUG_RESET_BIT(cpu);
+	writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+	spin_unlock_irq(&boot_lock);
+	msleep(POLL_MSEC);
+
+	return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool skip_wfi = false;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	spin_lock(&boot_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	hip04_cpu_table[cluster][cpu]--;
+	if (hip04_cpu_table[cluster][cpu] == 1) {
+		/* A power_up request went ahead of us. */
+		skip_wfi = true;
+	} else if (hip04_cpu_table[cluster][cpu] > 1) {
+		pr_err("Cluster %d CPU%d is still running\n", cluster, cpu);
+		BUG();
+	}
+
+	spin_unlock(&boot_lock);
+
+	v7_exit_coherency_flush(louis);
+
+	__mcpm_cpu_down(cpu, cluster);
+
+	isb();
+	dsb();
+
+	if (!skip_wfi)
+		wfi();
+}
+
+static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int data, tries;
+
+	BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
+	       cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
+
+	for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; tries++) {
+		data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+		if (!(data & CORE_WFI_STATUS(cpu))) {
+			msleep(POLL_MSEC);
+			continue;
+		}
+		data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+		       CORE_DEBUG_RESET_BIT(cpu);
+		writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
+		return 0;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static void hip04_mcpm_powered_up(void)
+{
+	if (!relocation)
+		return;
+	spin_lock(&boot_lock);
+	writel_relaxed(0, relocation);
+	writel_relaxed(0, relocation + 4);
+	writel_relaxed(0, relocation + 8);
+	writel_relaxed(0, relocation + 12);
+	spin_unlock(&boot_lock);
+}
+
+static const struct mcpm_platform_ops hip04_mcpm_ops = {
+	.power_up		= hip04_mcpm_power_up,
+	.power_down		= hip04_mcpm_power_down,
+	.wait_for_powerdown	= hip04_mcpm_wait_for_powerdown,
+	.powered_up		= hip04_mcpm_powered_up,
+};
+
+static bool __init hip04_cpu_table_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	if (cluster >= HIP04_MAX_CLUSTERS ||
+	    cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
+		pr_err("%s: boot CPU is out of bound!\n", __func__);
+		return false;
+	}
+	hip04_set_snoop_filter(cluster, 1);
+	hip04_cpu_table[cluster][cpu] = 1;
+	return true;
+}
+
+static int __init hip04_mcpm_init(void)
+{
+	struct device_node *np, *np_fab;
+	int ret = -ENODEV;
+
+	np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+	if (!np)
+		goto err;
+	np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
+	if (!np_fab)
+		goto err;
+
+	if (of_property_read_u32(np, "bootwrapper-phys",
+				 &hip04_boot.bootwrapper_phys)) {
+		pr_err("failed to get bootwrapper-phys\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "bootwrapper-size",
+				 &hip04_boot.bootwrapper_size)) {
+		pr_err("failed to get bootwrapper-size\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "bootwrapper-magic",
+				 &hip04_boot.bootwrapper_magic)) {
+		pr_err("failed to get bootwrapper-magic\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "relocation-entry",
+				 &hip04_boot.relocation_entry)) {
+		pr_err("failed to get relocation-entry\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	if (of_property_read_u32(np, "relocation-size",
+				 &hip04_boot.relocation_size)) {
+		pr_err("failed to get relocation-size\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	relocation = ioremap(hip04_boot.relocation_entry,
+			     hip04_boot.relocation_size);
+	if (!relocation) {
+		pr_err("failed to map relocation space\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	sysctrl = of_iomap(np, 0);
+	if (!sysctrl) {
+		pr_err("failed to get sysctrl base\n");
+		ret = -ENOMEM;
+		goto err_sysctrl;
+	}
+	fabric = of_iomap(np_fab, 0);
+	if (!fabric) {
+		pr_err("failed to get fabric base\n");
+		ret = -ENOMEM;
+		goto err_fabric;
+	}
+
+	memblock_reserve(hip04_boot.bootwrapper_phys,
+			 hip04_boot.bootwrapper_size);
+
+	if (!hip04_cpu_table_init())
+		return -EINVAL;
+	ret = mcpm_platform_register(&hip04_mcpm_ops);
+	if (!ret) {
+		mcpm_sync_init(NULL);
+		pr_info("HiP04 MCPM initialized\n");
+	}
+	return ret;
+err_fabric:
+	iounmap(sysctrl);
+err_sysctrl:
+	iounmap(relocation);
+err:
+	return ret;
+}
+early_initcall(hip04_mcpm_init);
+
+bool __init hip04_smp_init_ops(void)
+{
+	mcpm_smp_set_ops();
+	return true;
+}

Signature · 7 lines

1.9.1


_______________________________________________
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linux-arm-kernel at lists.infradead.org
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Add hip04.dtsi & hip04-d01.dts file to support HiP04 SoC platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 Documentation/devicetree/bindings/arm/gic.txt      |   1 +
 .../bindings/arm/hisilicon/hisilicon.txt           |  10 +
 .../devicetree/bindings/clock/hip04-clock.txt      |  20 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/hip04-d01.dts                    |  74 +++++++
 arch/arm/boot/dts/hip04.dtsi                       | 239 +++++++++++++++++++++
 6 files changed, 345 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hip04-clock.txt
 create mode 100644 arch/arm/boot/dts/hip04-d01.dts
 create mode 100644 arch/arm/boot/dts/hip04.dtsi

arch/arm/boot/dts/hip04-d01.dts new file +11 -0

new file mode 100644
index 0000000..a10dcf3
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013-2014 Linaro Ltd.
+ *  Author: Haojian Zhuang <[email protected]>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+

arch/arm/boot/dts/hip04-d01.dts new file +23 -0

+               device_type = "memory";
+               reg = <0x00000004 0xc0000000 0x40000000>;
+       };
+
+       memory at 0000000500000000 {
+               device_type = "memory";
+               reg = <0x00000005 0x00000000 0x80000000>;
+       };
+
+       memory at 0000000580000000 {
+               device_type = "memory";
+               reg = <0x00000005 0x80000000 0x80000000>;
+       };
+
+       memory at 0000000600000000 {
+               device_type = "memory";
+               reg = <0x00000006 0x00000000 0x80000000>;
+       };
+
+       memory at 0000000680000000 {
+               device_type = "memory";
+               reg = <0x00000006 0x80000000 0x80000000>;
+       };

arch/arm/boot/dts/hip04-d01.dts new file +3 -0

+                       reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
+                             <0xc04000 0x2000>, <0xc06000 0x2000>;
+               };

Add hip04.dtsi & hip04-d01.dts file to support HiP04 SoC platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 Documentation/devicetree/bindings/arm/gic.txt      |   1 +
 .../bindings/arm/hisilicon/hisilicon.txt           |  10 +
 .../devicetree/bindings/clock/hip04-clock.txt      |  20 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/hip04-d01.dts                    |  74 +++++++
 arch/arm/boot/dts/hip04.dtsi                       | 239 +++++++++++++++++++++
 6 files changed, 345 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hip04-clock.txt
 create mode 100644 arch/arm/boot/dts/hip04-d01.dts
 create mode 100644 arch/arm/boot/dts/hip04.dtsi

Documentation/devicetree/bindings/arm/gic.txt +1 -0

index 5573c08..150f7d6 100644
@@ -16,6 +16,7 @@ Main node required properties:
 	"arm,cortex-a9-gic"
 	"arm,cortex-a7-gic"
 	"arm,arm11mp-gic"
+	"hisilicon,hip04-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +10 -0

index df0a452..4681f15 100644
@@ -4,6 +4,10 @@ Hisilicon Platforms Device Tree Bindings
 Hi4511 Board
 Required root node properties:
 	- compatible = "hisilicon,hi3620-hi4511";
+HiP04 D01 Board
+Required root node properties:
+	- compatible = "hisilicon,hip04-d01";
+
 
 Hisilicon system controller
 

@@ -19,6 +23,11 @@ Optional properties:
 		If reg value is not zero, cpun exit wfi and go
 - resume-offset : offset in sysctrl for notifying cpu0 when resume
 - reboot-offset : offset in sysctrl for system reboot
+- relocation-entry : relocation address of secondary cpu boot code
+- relocation-size : relocation size of secondary cpu boot code
+- bootwrapper-phys : physical address of boot wrapper
+- bootwrapper-size : size of boot wrapper
+- bootwrapper-magic : magic number for secondary cpu in boot wrapper
 
 Example:
 

@@ -31,6 +40,7 @@ Example:
 		reboot-offset = <0x4>;
 	};
 
+
 PCTRL: Peripheral misc control register
 
 Required Properties:

Documentation/devicetree/bindings/clock/hip04-clock.txt new file +20 -0

new file mode 100644
index 0000000..4d31ae3
@@ -0,0 +1,20 @@
+* Hisilicon HiP04 Clock Controller
+
+The HiP04 clock controller generates and supplies clock to various
+controllers within the HiP04 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hip04-clock" - controller compatible with HiP04 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hip04-clock.h>.

arch/arm/boot/dts/Makefile +1 -0

index 35c146f..7119bca 100644
@@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
 	ecx-2000.dtb
+dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
 	integratorcp.dtb
 dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \

arch/arm/boot/dts/hip04-d01.dts new file +21 -0

new file mode 100644
index 0000000..a10dcf3
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013-2014 Linaro Ltd.
+ *  Author: Haojian Zhuang <[email protected]>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "hip04.dtsi"
+
+/ {
+	/* memory bus is 64-bit */
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "Hisilicon D01 Development Board";
+	compatible = "hisilicon,hip04-d01";
+
+	memory at 0 {

From the "soc" node's ranges, I'm guessing I/O starts at

arch/arm/boot/dts/hip04-d01.dts new file +43 -0

+	};
+
+	memory at 00000004c0000000 {
+		device_type = "memory";
+		reg = <0x00000004 0xc0000000 0x40000000>;
+	};
+
+	memory at 0000000500000000 {
+		device_type = "memory";
+		reg = <0x00000005 0x00000000 0x80000000>;
+	};
+
+	memory at 0000000580000000 {
+		device_type = "memory";
+		reg = <0x00000005 0x80000000 0x80000000>;
+	};
+
+	memory at 0000000600000000 {
+		device_type = "memory";
+		reg = <0x00000006 0x00000000 0x80000000>;
+	};
+
+	memory at 0000000680000000 {
+		device_type = "memory";
+		reg = <0x00000006 0x80000000 0x80000000>;
+	};
+
+	memory at 0000000700000000 {
+		device_type = "memory";
+		reg = <0x00000007 0x00000000 0x80000000>;
+	};
+
+	memory at 0000000780000000 {
+		device_type = "memory";
+		reg = <0x00000007 0x80000000 0x80000000>;
+	};
+
+	soc {
+		uart0: uart at 4007000 {
+			status = "ok";
+		};
+	};
+};

arch/arm/boot/dts/hip04.dtsi new file +183 -0

new file mode 100644
index 0000000..7e909ee
@@ -0,0 +1,239 @@
+/*
+ * Hisilicon Ltd. HiP01 SoC
+ *
+ * Copyright (C) 2013-2014 Hisilicon Ltd.
+ * Copyright (C) 2013-2014 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/hip04-clock.h>
+
+/ {
+	/* memory bus is 64-bit */
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+				core1 {
+					cpu = <&CPU1>;
+				};
+				core2 {
+					cpu = <&CPU2>;
+				};
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+				core1 {
+					cpu = <&CPU5>;
+				};
+				core2 {
+					cpu = <&CPU6>;
+				};
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+			cluster2 {
+				core0 {
+					cpu = <&CPU8>;
+				};
+				core1 {
+					cpu = <&CPU9>;
+				};
+				core2 {
+					cpu = <&CPU10>;
+				};
+				core3 {
+					cpu = <&CPU11>;
+				};
+			};
+			cluster3 {
+				core0 {
+					cpu = <&CPU12>;
+				};
+				core1 {
+					cpu = <&CPU13>;
+				};
+				core2 {
+					cpu = <&CPU14>;
+				};
+				core3 {
+					cpu = <&CPU15>;
+				};
+			};
+		};
+		CPU0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+		};
+		CPU1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+		};
+		CPU2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+		};
+		CPU3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+		};
+		CPU4: cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x100>;
+		};
+		CPU5: cpu at 101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x101>;
+		};
+		CPU6: cpu at 102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x102>;
+		};
+		CPU7: cpu at 103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x103>;
+		};
+		CPU8: cpu at 200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x200>;
+		};
+		CPU9: cpu at 201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x201>;
+		};
+		CPU10: cpu at 202 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x202>;
+		};
+		CPU11: cpu at 203 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x203>;
+		};
+		CPU12: cpu at 300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x300>;
+		};
+		CPU13: cpu at 301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x301>;
+		};
+		CPU14: cpu at 302 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x302>;
+		};
+		CPU15: cpu at 303 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x303>;
+		};
+	};
+
+	soc {
+		/* It's a 32-bit SoC. */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		device_type = "soc";
+		interrupt-parent = <&gic>;
+		ranges = <0 0 0xe0000000 0x10000000>;
+
+		gic: interrupt-controller at c01000 {
+			compatible = "hisilicon,hip04-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <1 9 0xf04>;

arch/arm/boot/dts/hip04.dtsi new file +14 -0

+		};
+
+		fabric: fabric {
+			compatible = "hisilicon,hip04-fabric";
+			reg = <0x302a000 0x1000>;
+		};
+
+		clock: clock {
+			compatible = "hisilicon,hip04-clock";
+			/* dummy register */
+			reg = <0 0x1000>;
+			#clock-cells = <1>;
+		};
+

arch/arm/boot/dts/hip04.dtsi new file +5 -0

+			compatible = "arm,armv7-timer";
+			interrupts = <1 13 0xf08>,
+				     <1 14 0xf08>,
+				     <1 11 0xf08>,
+				     <1 10 0xf08>;

Add hip04.dtsi & hip04-d01.dts file to support HiP04 SoC platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 Documentation/devicetree/bindings/arm/gic.txt      |   1 +
 .../bindings/arm/hisilicon/hisilicon.txt           |  10 +
 .../devicetree/bindings/clock/hip04-clock.txt      |  20 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/hip04-d01.dts                    |  74 +++++++
 arch/arm/boot/dts/hip04.dtsi                       | 239 +++++++++++++++++++++
 6 files changed, 345 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hip04-clock.txt
 create mode 100644 arch/arm/boot/dts/hip04-d01.dts
 create mode 100644 arch/arm/boot/dts/hip04.dtsi

Documentation/devicetree/bindings/arm/gic.txt +1 -0

index 5573c08..150f7d6 100644
@@ -16,6 +16,7 @@ Main node required properties:
        "arm,cortex-a9-gic"
        "arm,cortex-a7-gic"
        "arm,arm11mp-gic"
+       "hisilicon,hip04-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +4 -0

index df0a452..4681f15 100644
@@ -4,6 +4,10 @@ Hisilicon Platforms Device Tree Bindings
 Hi4511 Board
 Required root node properties:
        - compatible = "hisilicon,hi3620-hi4511";
+HiP04 D01 Board
+Required root node properties:
+       - compatible = "hisilicon,hip04-d01";
+
 
 Hisilicon system controller
 

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +1 -0

 Example:
 

@@ -31,6 +40,7 @@ Example:
                reboot-offset = <0x4>;
        };
 
+
 PCTRL: Peripheral misc control register
 
 Required Properties:

Documentation/devicetree/bindings/clock/hip04-clock.txt new file +20 -0

new file mode 100644
index 0000000..4d31ae3
@@ -0,0 +1,20 @@
+* Hisilicon HiP04 Clock Controller
+
+The HiP04 clock controller generates and supplies clock to various
+controllers within the HiP04 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hip04-clock" - controller compatible with HiP04 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hip04-clock.h>.

arch/arm/boot/dts/Makefile +1 -0

index 35c146f..7119bca 100644
@@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
        ecx-2000.dtb
+dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
        integratorcp.dtb
 dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \

arch/arm/boot/dts/hip04-d01.dts new file +57 -0

new file mode 100644
index 0000000..a10dcf3
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013-2014 Linaro Ltd.
+ *  Author: Haojian Zhuang <[email protected]>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "hip04.dtsi"
+
+/ {
+       /* memory bus is 64-bit */
+       #address-cells = <2>;
+       #size-cells = <1>;
+       model = "Hisilicon D01 Development Board";
+       compatible = "hisilicon,hip04-d01";
+
+       memory at 0 {
+               device_type = "memory";
+               /*
+                * Bootloader loads kernel image into 0x1000_0000 region,
+                * so disables the region between [0000_0000 - 1000_0000]
+                * temporarily.
+                * Because the PHYS_TO_VIRT_OFFSET is calculated based on
+                * the original region that kenrel is loaded.
+                * This workaround will be removed only after UEFI updated.
+                */
+               reg = <0x00000000 0x10000000 0xc0000000>;
+       };
+
+       memory at 00000004c0000000 {
+               device_type = "memory";
+               reg = <0x00000004 0xc0000000 0x40000000>;
+       };
+
+       memory at 0000000500000000 {
+               device_type = "memory";
+               reg = <0x00000005 0x00000000 0x80000000>;
+       };
+
+       memory at 0000000580000000 {
+               device_type = "memory";
+               reg = <0x00000005 0x80000000 0x80000000>;
+       };
+
+       memory at 0000000600000000 {
+               device_type = "memory";
+               reg = <0x00000006 0x00000000 0x80000000>;
+       };
+
+       memory at 0000000680000000 {
+               device_type = "memory";
+               reg = <0x00000006 0x80000000 0x80000000>;
+       };

arch/arm/boot/dts/hip04-d01.dts new file +17 -0

+               interrupt-parent = <&gic>;
+               ranges = <0 0 0xe0000000 0x10000000>;
+
+               gic: interrupt-controller at c01000 {
+                       compatible = "hisilicon,hip04-gic";
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       interrupts = <1 9 0xf04>;
+
+                       /* gic dist base, gic cpu base */
+                       reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
+                             <0xc04000 0x2000>, <0xc06000 0x2000>;
+               };
+
+               sysctrl: sysctrl {
+                       compatible = "hisilicon,sysctrl";

arch/arm/boot/dts/hip04-d01.dts new file +21 -1

+               };
+
+               timer {
+                       compatible = "arm,armv7-timer";
+                       interrupts = <1 13 0xf08>,
+                                    <1 14 0xf08>,
+                                    <1 11 0xf08>,
+                                    <1 10 0xf08>;
+               };
+
+               uart0: uart at 4007000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x4007000 0x1000>;
+                       interrupts = <0 381 4>;
+                       clocks = <&clock HIP04_CLK_168M>;
+                       clock-names = "uartclk";
+                       reg-shift = <2>;
+                       status = "disabled";
+               };
+       };
+};
--

1.9.1

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

In ARM standard GIC, GICH_APR offset is 0xf0 & GICH_LR0 offset is 0x100. In HiP04 GIC, GICH_APR offset is 0x70 & GICH_LR0 offset is 0x80. So add the support of HiP04 SoC in VGIC.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/kvm/interrupts_head.S  | 24 ++++++++++++++++++++----
 include/linux/irqchip/arm-gic.h |  3 +++
 virt/kvm/arm/vgic.c             | 15 ++++++++++++++-
 3 files changed, 37 insertions(+), 5 deletions(-)

arch/arm/kvm/interrupts_head.S +0 -0

index 76af9302..b27e43f 100644

arch/arm/kvm/interrupts_head.S +17 -3

 	str	r3, [r11, #VGIC_CPU_HCR]
 	str	r4, [r11, #VGIC_CPU_VMCR]

@@ -435,7 +437,11 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 	str	r5, [r2, #GICH_HCR]
 
 	/* Save list registers */
-	add	r2, r2, #GICH_LR0
+	ldr	r10, =gich_apr
+	ldr	r10, [r10]
+	/* the offset between GICH_APR & GICH_LR0 is 0x10 */
+	add	r10, r10, #0x10
+	add	r2, r2, r10
 	add	r3, r11, #VGIC_CPU_LR
 	ldr	r4, [r11, #VGIC_CPU_NR_LR]
 1:	ldr	r6, [r2], #4

@@ -469,10 +475,16 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 
 	str	r3, [r2, #GICH_HCR]
 	str	r4, [r2, #GICH_VMCR]
-	str	r8, [r2, #GICH_APR]
+	ldr	r6, =gich_apr
+	ldr	r6, [r6]
+	str	r8, [r2, r6]
 
 	/* Restore list registers */
-	add	r2, r2, #GICH_LR0
+	ldr	r6, =gich_apr
+	ldr	r6, [r6]
+	/* the offset between GICH_APR & GICH_LR0 is 0x10 */
+	add	r6, r6, #0x10
+	add	r2, r2, r6
 	add	r3, r11, #VGIC_CPU_LR
 	ldr	r4, [r11, #VGIC_CPU_NR_LR]
 1:	ldr	r6, [r3], #4

@@ -618,3 +630,7 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 .macro load_vcpu
 	mrc	p15, 4, vcpu, c13, c0, 2	@ HTPIDR
 .endm
+
+	.global gich_apr
+gich_apr:
+	.long	GICH_APR

include/linux/irqchip/arm-gic.h +3 -0

index 55933aa..dd0785a 100644
@@ -49,6 +49,8 @@
 #define GICH_ELRSR1 			0x34
 #define GICH_APR			0xf0
 #define GICH_LR0			0x100
+#define HIP04_GICH_APR			0x70
+/* GICH_LR0 offset in HiP04 is 0x80 */
 
 #define GICH_HCR_EN			(1 << 0)
 #define GICH_HCR_UIE			(1 << 1)

@@ -78,6 +80,7 @@
 struct device_node;
 
 extern struct irq_chip gic_arch_extn;
+extern unsigned int gich_apr;
 
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
 		    u32 offset, struct device_node *);

virt/kvm/arm/vgic.c +11 -0

index 47b2983..6bf31db 100644
@@ -1470,17 +1470,30 @@ static struct notifier_block vgic_cpu_nb = {
 	.notifier_call = vgic_cpu_notify,
 };
 
+static const struct of_device_id of_vgic_ids[] = {
+	{
+		.compatible = "arm,cortex-a15-gic",
+		.data = (void *)GICH_APR,
+	}, {
+		.compatible = "hisilicon,hip04-gic",
+		.data = (void *)HIP04_GICH_APR,
+	}, {
+	},
+};
+
 int kvm_vgic_hyp_init(void)
 {
 	int ret;