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Add coresight support for QCOM SC7180 SoC

PATCH Superseded Sai Prakash Ranjan 3 participants 12 messages Mar 20, 2020 – Apr 9, 2020

Subsystems (6)
Device tree bindings Arm Qualcomm mailing list Arm Qualcomm support Arm/CoreSight framework and drivers +2 more subsystems

v1 of 2 Superseded Latest is v2 →

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Sai Prakash Ranjan

author
#0 lore raw

cover Add coresight support for QCOM SC7180 SoC

Patch 1 adds the ETM PIDs for Kryo 4XX CPU cores and Patch 2 adds the DT nodes for coresight components on SC7180.

Sai Prakash Ranjan (2):
coresight: etm4x: Add support for Qualcomm SC7180 SoC
arm64: dts: qcom: sc7180: Add Coresight support

 arch/arm64/boot/dts/qcom/sc7180.dtsi          | 507 ++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etm4x.c |   2 +
 2 files changed, 509 insertions(+)
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#1 lore raw

PATCH 1/2 coresight: etm4x: Add support for Qualcomm SC7180 SoC

Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU cores based on Cortex-A55.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/hwtracing/coresight/coresight-etm4x.c +2 -0
index a90d757f7043..a153a65c4c5b 100644
@@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
 	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
 	CS_AMBA_ID(0x000bb802),			/* Qualcomm Kryo 385 Cortex-A55 */
 	CS_AMBA_ID(0x000bb803),			/* Qualcomm Kryo 385 Cortex-A75 */
+	CS_AMBA_ID(0x000bb805),			/* Qualcomm Kryo 4XX Cortex-A55 */
+	CS_AMBA_ID(0x000bb804),			/* Qualcomm Kryo 4XX Cortex-A76 */
 	CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
 	{},
 };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
maintainer
#3 lore raw

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

In reply to Sai Prakash Ranjan
Quoted 14 lines · Sai Prakash Ranjan

Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU cores based on Cortex-A55.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
  drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
  1 file changed, 2 insertions(+)
drivers/hwtracing/coresight/coresight-etm4x.c +0 -0
index a90d757f7043..a153a65c4c5b 100644

drivers/hwtracing/coresight/coresight-etm4x.c static const struct amba_id etm4_ids[] = { · line 1560

Quoted 5 lines
drivers/hwtracing/coresight/coresight-etm4x.c +2 -0
@@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
  	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
  	CS_AMBA_ID(0x000bb802),			/* Qualcomm Kryo 385 Cortex-A55 */
  	CS_AMBA_ID(0x000bb803),			/* Qualcomm Kryo 385 Cortex-A75 */
+	CS_AMBA_ID(0x000bb805),			/* Qualcomm Kryo 4XX Cortex-A55 */
+	CS_AMBA_ID(0x000bb804),			/* Qualcomm Kryo 4XX Cortex-A76 */

Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please could we enforce the UCI_ID check for these components ? The moment you add CTI components to your board this could conflict with them unless we check the UCI_ID for ETMv4.

Suzuki

author
#4 lore raw

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

Hi Suzuki,

Quoted 10 lines · Suzuki K Poulose
Quoted 9 lines · Sai Prakash Ranjan

Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU cores based on Cortex-A55.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
  drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
  1 file changed, 2 insertions(+)
Quoted 16 lines

drivers/hwtracing/coresight/coresight-etm4x.c static const struct amba_id etm4_ids[] = { · line 1560

Quoted 10 lines
drivers/hwtracing/coresight/coresight-etm4x.c +2 -0
index a90d757f7043..a153a65c4c5b 100644
@@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
  	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
  	CS_AMBA_ID(0x000bb802),			/* Qualcomm Kryo 385 Cortex-A55 */
  	CS_AMBA_ID(0x000bb803),			/* Qualcomm Kryo 385 Cortex-A75 */
+	CS_AMBA_ID(0x000bb805),			/* Qualcomm Kryo 4XX Cortex-A55 */
+	CS_AMBA_ID(0x000bb804),			/* Qualcomm Kryo 4XX Cortex-A76 */

Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please could we enforce the UCI_ID check for these components ? The moment you add CTI components to your board this could conflict with them unless we check the UCI_ID for ETMv4.

Yes I got these IDs through devarch and it does indicate that it is ETMv4.2.

devname=7040000.etm dev->type=0x13 devarch=0x47724a13 devname=7140000.etm dev->type=0x13 devarch=0x47724a13 devname=7240000.etm dev->type=0x13 devarch=0x47724a13 devname=7340000.etm dev->type=0x13 devarch=0x47724a13 devname=7440000.etm dev->type=0x13 devarch=0x47724a13 devname=7540000.etm dev->type=0x13 devarch=0x47724a13 devname=7640000.etm dev->type=0x13 devarch=0x47724a13 devname=7740000.etm dev->type=0x13 devarch=0x47724a13

I will add the UCI_ID as you suggested in next version.

Thanks,
Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
maintainer
#5 lore raw

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

Quoted 43 lines · Sai Prakash Ranjan

Hi Suzuki,

Quoted 19 lines · Suzuki K Poulose
Quoted 18 lines · Sai Prakash Ranjan

Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU cores based on Cortex-A55.

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
  drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++

  1 file changed, 2 insertions(+)
drivers/hwtracing/coresight/coresight-etm4x.c +0 -0
index a90d757f7043..a153a65c4c5b 100644
@@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {

      CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_ID(0x000bb802),            /* Qualcomm Kryo 385 Cortex-A55 */ CS_AMBA_ID(0x000bb803),            /* Qualcomm Kryo 385 Cortex-A75 */ +    CS_AMBA_ID(0x000bb805),            /* Qualcomm Kryo 4XX

Quoted 9 lines
Quoted 3 lines

Cortex-A55 */
+    CS_AMBA_ID(0x000bb804),            /* Qualcomm Kryo 4XX Cortex-A76 */

Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please could we enforce the UCI_ID check for these components ? The moment you add CTI components to your board this could conflict with them unless we check the UCI_ID for ETMv4.

Yes I got these IDs through devarch and it does indicate that it is ETMv4.2.

devname=7040000.etm dev->type=0x13 devarch=0x47724a13 devname=7140000.etm dev->type=0x13 devarch=0x47724a13 devname=7240000.etm dev->type=0x13 devarch=0x47724a13 devname=7340000.etm dev->type=0x13 devarch=0x47724a13 devname=7440000.etm dev->type=0x13 devarch=0x47724a13 devname=7540000.etm dev->type=0x13 devarch=0x47724a13 devname=7640000.etm dev->type=0x13 devarch=0x47724a13 devname=7740000.etm dev->type=0x13 devarch=0x47724a13

Quoted 1 line

I will add the UCI_ID as you suggested in next version.

If you do have access to the Kryo 385 variants, please fix them as well.

Cheers
Suzuki

author
#6 lore raw

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

Quoted 44 lines · Suzuki K Poulose
Quoted 43 lines · Sai Prakash Ranjan

Hi Suzuki,

Quoted 19 lines · Suzuki K Poulose
Quoted 18 lines · Sai Prakash Ranjan

Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU cores based on Cortex-A55.

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
  drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++

  1 file changed, 2 insertions(+)
drivers/hwtracing/coresight/coresight-etm4x.c +0 -0
index a90d757f7043..a153a65c4c5b 100644
@@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {

      CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_ID(0x000bb802),            /* Qualcomm Kryo 385 Cortex-A55 */ CS_AMBA_ID(0x000bb803),            /* Qualcomm Kryo 385 Cortex-A75 */ +    CS_AMBA_ID(0x000bb805),            /* Qualcomm Kryo 4XX

Quoted 9 lines
Quoted 3 lines

Cortex-A55 */
+    CS_AMBA_ID(0x000bb804),            /* Qualcomm Kryo 4XX Cortex-A76 */

Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please could we enforce the UCI_ID check for these components ? The moment you add CTI components to your board this could conflict with them unless we check the UCI_ID for ETMv4.

Yes I got these IDs through devarch and it does indicate that it is ETMv4.2.

devname=7040000.etm dev->type=0x13 devarch=0x47724a13 devname=7140000.etm dev->type=0x13 devarch=0x47724a13 devname=7240000.etm dev->type=0x13 devarch=0x47724a13 devname=7340000.etm dev->type=0x13 devarch=0x47724a13 devname=7440000.etm dev->type=0x13 devarch=0x47724a13 devname=7540000.etm dev->type=0x13 devarch=0x47724a13 devname=7640000.etm dev->type=0x13 devarch=0x47724a13 devname=7740000.etm dev->type=0x13 devarch=0x47724a13

Quoted 5 lines
Quoted 1 line

I will add the UCI_ID as you suggested in next version.

If you do have access to the Kryo 385 variants, please fix them as well.

Sure, will do.

Thanks,
Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#7 lore raw

PATCH 2/2 arm64: dts: qcom: sc7180: Add Coresight support

In reply to Sai Prakash Ranjan

Add coresight components found on Qualcomm SC7180 SoC.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 +++++++++++++++++++++++++++
 1 file changed, 507 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +507 -0
index 998f101ad623..d8fe960d6ace 100644
@@ -1294,6 +1294,513 @@
 			};
 		};
 
+		stm@6002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0 0x06002000 0 0x1000>,
+			      <0 0x16280000 0 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint =
+						  <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@6041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06041000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in0>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					funnel0_in7: endpoint {
+						remote-endpoint =
+						  <&stm_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06042000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in1>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+					funnel1_in4: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06045000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&swao_funnel_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					merge_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					merge_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&funnel1_out>;
+					};
+				};
+			};
+		};
+
+		replicator@6046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0 0x06046000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					replicator_out: endpoint {
+						remote-endpoint =
+						  <&etr_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					replicator_in: endpoint {
+						remote-endpoint =
+						  <&swao_replicator_out>;
+					};
+				};
+			};
+		};
+
+		etr@6048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0 0x06048000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr_in: endpoint {
+						remote-endpoint =
+						  <&replicator_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06b04000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					swao_funnel_out: endpoint {
+						remote-endpoint =
+						  <&etf_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					swao_funnel_in: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_out>;
+					};
+				};
+			};
+		};
+
+		etf@6b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0 0x06b05000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etf_out: endpoint {
+						remote-endpoint =
+						  <&swao_replicator_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					etf_in: endpoint {
+						remote-endpoint =
+						  <&swao_funnel_out>;
+					};
+				};
+			};
+		};
+
+		replicator@6b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0 0x06b06000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					swao_replicator_out: endpoint {
+						remote-endpoint =
+						  <&replicator_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					swao_replicator_in: endpoint {
+						remote-endpoint =
+						  <&etf_out>;
+					};
+				};
+			};
+		};
+
+		etm@7040000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07040000 0 0x1000>;
+
+			cpu = <&CPU0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		etm@7140000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07140000 0 0x1000>;
+
+			cpu = <&CPU1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		etm@7240000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07240000 0 0x1000>;
+
+			cpu = <&CPU2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in2>;
+					};
+				};
+			};
+		};
+
+		etm@7340000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07340000 0 0x1000>;
+
+			cpu = <&CPU3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in3>;
+					};
+				};
+			};
+		};
+
+		etm@7440000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07440000 0 0x1000>;
+
+			cpu = <&CPU4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		etm@7540000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07540000 0 0x1000>;
+
+			cpu = <&CPU5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in5>;
+					};
+				};
+			};
+		};
+
+		etm@7640000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07640000 0 0x1000>;
+
+			cpu = <&CPU6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		etm@7740000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07740000 0 0x1000>;
+
+			cpu = <&CPU7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@7800000 { /* APSS Funnel */
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x07800000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					apss_funnel_out: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					apss_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					apss_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					apss_funnel_in2: endpoint {
+						remote-endpoint =
+						  <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+					apss_funnel_in3: endpoint {
+						remote-endpoint =
+						  <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+					apss_funnel_in4: endpoint {
+						remote-endpoint =
+						  <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+					apss_funnel_in5: endpoint {
+						remote-endpoint =
+						  <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+					apss_funnel_in6: endpoint {
+						remote-endpoint =
+						  <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+					apss_funnel_in7: endpoint {
+						remote-endpoint =
+						  <&etm7_out>;
+					};
+				};
+			};
+		};
+
+		funnel@7810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x07810000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					apss_merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&funnel1_in4>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					apss_merge_funnel_in: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_out>;
+					};
+				};
+			};
+		};
+
 		sdhc_2: sdhci@8804000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Reviewed-by Tested-by on v1 2/2
#8 lore raw

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)

Quoted 4 lines

Add coresight components found on Qualcomm SC7180 SoC.

Signed-off-by Sai Prakash Ranjan <[email protected]>

---

Reviewed-by Stephen Boyd <[email protected]>
Tested-by Stephen Boyd <[email protected]>

One nit below.

Quoted 15 lines
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 +++++++++++++++++++++++++++
 1 file changed, 507 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +4 -0
index 998f101ad623..d8fe960d6ace 100644
@@ -1294,6 +1294,513 @@
                        };
                };
 
+               stm@6002000 {
+                       compatible = "arm,coresight-stm", "arm,primecell";
+                       reg = <0 0x06002000 0 0x1000>,
+                             <0 0x16280000 0 0x180000>;

arch/arm64/boot/dts/qcom/sc7180.dtsi line 1310

Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +10 -0
+                       reg-names = "stm-base", "stm-stimulus-base";
+
+                       clocks = <&aoss_qmp>;
+                       clock-names = "apb_pclk";
+
+                       out-ports {
+                               port {
+                                       stm_out: endpoint {
+                                               remote-endpoint =
+                                                 <&funnel0_in7>;

Given that this is DT I'd say we just put this remote-endpoint all on one line. Makes it more readable and I don't think we really care about the line length in these cases. We're nested pretty deep because it's a graph binding.

Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5 -0
+                                       };
+                               };
+                       };
+               };
+
author
#9 lore raw

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

Quoted 35 lines · Stephen Boyd

Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)

Quoted 4 lines

Add coresight components found on Qualcomm SC7180 SoC.

Signed-off-by Sai Prakash Ranjan <[email protected]>

---

Reviewed-by Stephen Boyd <[email protected]>
Tested-by Stephen Boyd <[email protected]>

One nit below.

Quoted 24 lines
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 
+++++++++++++++++++++++++++
 1 file changed, 507 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +11 -0
index 998f101ad623..d8fe960d6ace 100644
@@ -1294,6 +1294,513 @@
                        };
                };
 
+               stm@6002000 {
+                       compatible = "arm,coresight-stm", 
 "arm,primecell";
+                       reg = <0 0x06002000 0 0x1000>,
+                             <0 0x16280000 0 0x180000>;
+                       reg-names = "stm-base", "stm-stimulus-base";
+
+                       clocks = <&aoss_qmp>;
+                       clock-names = "apb_pclk";
+
+                       out-ports {
+                               port {
Quoted 9 lines

arch/arm64/boot/dts/qcom/sc7180.dtsi line 1310

Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +3 -0
+                                       stm_out: endpoint {
+                                               remote-endpoint =
+                                                 <&funnel0_in7>;

Given that this is DT I'd say we just put this remote-endpoint all on one line. Makes it more readable and I don't think we really care about the line length in these cases. We're nested pretty deep because it's a graph binding.

Thanks for the review and test, I will make this change.

-Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#10 lore raw

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

In reply to Sai Prakash Ranjan

Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)

Quoted 12 lines

Add coresight components found on Qualcomm SC7180 SoC.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 +++++++++++++++++++++++++++
 1 file changed, 507 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +0 -0
index 998f101ad623..d8fe960d6ace 100644

arch/arm64/boot/dts/qcom/sc7180.dtsi line 1298

Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +2 -0
@@ -1294,6 +1294,513 @@
                        };
                };
 
+               stm@6002000 {
+                       compatible = "arm,coresight-stm", "arm,primecell";

Does this SoC have a cpu-debug coresight component? Specifically wondering if there's an 'arm,coresight-cpu-debug' compatible node that can be added to this dtsi file.

author
#11 lore raw

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

Quoted 17 lines · Stephen Boyd

Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)

Quoted 16 lines

Add coresight components found on Qualcomm SC7180 SoC.

Signed-off-by Sai Prakash Ranjan <[email protected]>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 
+++++++++++++++++++++++++++
 1 file changed, 507 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +0 -0
index 998f101ad623..d8fe960d6ace 100644
@@ -1294,6 +1294,513 @@
                        };
                };
Quoted 7 lines

arch/arm64/boot/dts/qcom/sc7180.dtsi line 1299

Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +2 -0
+               stm@6002000 {
+                       compatible = "arm,coresight-stm", 
 "arm,primecell";

Does this SoC have a cpu-debug coresight component? Specifically wondering if there's an 'arm,coresight-cpu-debug' compatible node that can be added to this dtsi file.

There is no coresight cpu-debug component on SC7180 and SDM845.

-Sai

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation