Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC

Using ARCH_FOO symbol is preferred than SOC_FOO. Set obj-y for starfive/ in Makefile, so the StarFive drivers can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n.

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
 drivers/clk/Makefile         | 2 +-
 drivers/clk/starfive/Kconfig | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

drivers/clk/Makefile +1 -1

index e3ca0d058a25..3bed88d67a3a 100644
@@ -117,7 +117,7 @@ obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-y					+= sprd/
 obj-$(CONFIG_ARCH_STI)			+= st/
 obj-$(CONFIG_ARCH_STM32)		+= stm32/
-obj-$(CONFIG_SOC_STARFIVE)		+= starfive/
+obj-y					+= starfive/
 obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/
 obj-y					+= sunxi-ng/
 obj-$(CONFIG_ARCH_TEGRA)		+= tegra/

drivers/clk/starfive/Kconfig +2 -2

index 003bd2d56ce7..ef3517f4a276 100644
@@ -2,8 +2,8 @@
 
 config CLK_STARFIVE_JH7100
 	bool "StarFive JH7100 clock support"
-	depends on SOC_STARFIVE || COMPILE_TEST
-	default SOC_STARFIVE
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	default ARCH_STARFIVE
 	help
 	  Say yes here to support the clock controller on the StarFive JH7100
 	  SoC.

From: Emil Renner Berthing <[email protected]>

Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd.

Tested-by Tommaso Merciai <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Signed-off-by Emil Renner Berthing <[email protected]>

Co-developed-by Jianlong Huang <[email protected]>

Signed-off-by Jianlong Huang <[email protected]>

Co-developed-by Hal Feng <[email protected]>

Signed-off-by Hal Feng <[email protected]>

---
  arch/riscv/boot/dts/starfive/jh7110.dtsi | 509 +++++++++++++++++++++++
  1 file changed, 509 insertions(+)

create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +240 -0

new file mode 100644
index 000000000000..d484ecdf93f7
@@ -0,0 +1,509 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+	compatible = "starfive,jh7110";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		S7_0: cpu@0 {
+			compatible = "sifive,s7", "riscv";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <8192>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <16384>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imac_zba_zbb";
+			tlb-split;
+			status = "disabled";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		U74_1: cpu@1 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <1>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc_zba_zbb";
+			tlb-split;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		U74_2: cpu@2 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <2>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc_zba_zbb";
+			tlb-split;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		U74_3: cpu@3 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <3>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc_zba_zbb";
+			tlb-split;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		U74_4: cpu@4 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <4>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			riscv,isa = "rv64imafdc_zba_zbb";
+			tlb-split;
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&S7_0>;
+				};
+
+				core1 {
+					cpu = <&U74_1>;
+				};
+
+				core2 {
+					cpu = <&U74_2>;
+				};
+
+				core3 {
+					cpu = <&U74_3>;
+				};
+
+				core4 {
+					cpu = <&U74_4>;
+				};
+			};
+		};
+	};
+
+	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "gmac0_rgmii_rxin";
+		#clock-cells = <0>;
+	};
+
+	gmac0_rmii_refin: gmac0-rmii-refin-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "gmac0_rmii_refin";
+		#clock-cells = <0>;
+	};
+
+	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "gmac1_rgmii_rxin";
+		#clock-cells = <0>;
+	};
+
+	gmac1_rmii_refin: gmac1-rmii-refin-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "gmac1_rmii_refin";
+		#clock-cells = <0>;
+	};
+
+	i2srx_bclk_ext: i2srx-bclk-ext-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "i2srx_bclk_ext";
+		#clock-cells = <0>;
+	};
+
+	i2srx_lrck_ext: i2srx-lrck-ext-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "i2srx_lrck_ext";
+		#clock-cells = <0>;
+	};
+
+	i2stx_bclk_ext: i2stx-bclk-ext-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "i2stx_bclk_ext";
+		#clock-cells = <0>;
+	};
+
+	i2stx_lrck_ext: i2stx-lrck-ext-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "i2stx_lrck_ext";
+		#clock-cells = <0>;
+	};
+
+	mclk_ext: mclk-ext-clock {
+		compatible = "fixed-clock";
+		clock-output-names = "mclk_ext";
+		#clock-cells = <0>;
+	};
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "osc";
+		#clock-cells = <0>;
+	};
+
+	rtc_osc: rtc-oscillator {
+		compatible = "fixed-clock";
+		clock-output-names = "rtc_osc";
+		#clock-cells = <0>;
+	};

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +259 -0

+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clint: timer@2000000 {
+			compatible = "starfive,jh7110-clint", "sifive,clint0";
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>;
+		};
+
+		ccache: cache-controller@2010000 {
+			compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+			reg = <0x0 0x2010000 0x0 0x4000>;
+			interrupts = <1>, <3>, <4>, <2>;
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+		};
+
+		plic: interrupt-controller@c000000 {
+			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			riscv,ndev = <136>;
+		};
+
+		uart0: serial@10000000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+				 <&syscrg JH7110_SYSCLK_UART0_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+			interrupts = <32>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart1: serial@10010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10010000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+				 <&syscrg JH7110_SYSCLK_UART1_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+			interrupts = <33>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart2: serial@10020000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10020000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+				 <&syscrg JH7110_SYSCLK_UART2_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+			interrupts = <34>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@10030000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x10030000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
+			interrupts = <35>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@10040000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x10040000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
+			interrupts = <36>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@10050000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x10050000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
+			interrupts = <37>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		uart3: serial@12000000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+				 <&syscrg JH7110_SYSCLK_UART3_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+			interrupts = <45>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart4: serial@12010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12010000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+				 <&syscrg JH7110_SYSCLK_UART4_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+			interrupts = <46>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart5: serial@12020000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12020000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+				 <&syscrg JH7110_SYSCLK_UART5_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+			interrupts = <47>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@12030000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x12030000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
+			interrupts = <48>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@12040000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x12040000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
+			interrupts = <49>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@12050000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x12050000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
+			interrupts = <50>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@12060000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x12060000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
+			clock-names = "ref";
+			resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
+			interrupts = <51>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		syscrg: clock-controller@13020000 {
+			compatible = "starfive,jh7110-syscrg";
+			reg = <0x0 0x13020000 0x0 0x10000>;
+			clocks = <&osc>, <&gmac1_rmii_refin>,
+				 <&gmac1_rgmii_rxin>,
+				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+				 <&tdm_ext>, <&mclk_ext>;
+			clock-names = "osc", "gmac1_rmii_refin",
+				      "gmac1_rgmii_rxin",
+				      "i2stx_bclk_ext", "i2stx_lrck_ext",
+				      "i2srx_bclk_ext", "i2srx_lrck_ext",
+				      "tdm_ext", "mclk_ext";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		sysgpio: pinctrl@13040000 {
+			compatible = "starfive,jh7110-sys-pinctrl";
+			reg = <0x0 0x13040000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
+			resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
+			interrupts = <86>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		aoncrg: clock-controller@17000000 {
+			compatible = "starfive,jh7110-aoncrg";
+			reg = <0x0 0x17000000 0x0 0x10000>;
+			clocks = <&osc>, <&gmac0_rmii_refin>,
+				 <&gmac0_rgmii_rxin>,
+				 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+				 <&syscrg JH7110_SYSCLK_APB_BUS>,
+				 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
+				 <&rtc_osc>;
+			clock-names = "osc", "gmac0_rmii_refin",
+				      "gmac0_rgmii_rxin", "stg_axiahb",
+				      "apb_bus", "gmac0_gtxclk",
+				      "rtc_osc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		aongpio: pinctrl@17020000 {
+			compatible = "starfive,jh7110-aon-pinctrl";
+			reg = <0x0 0x17020000 0x0 0x10000>;
+			resets = <&aoncrg JH7110_AONRST_IOMUX>;
+			interrupts = <85>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};

Hi Hal,

Quoted 18 lines

From: Emil Renner Berthing <[email protected]>

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +11 -0

new file mode 100644
index 000000000000..d484ecdf93f7
@@ -0,0 +1,509 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {

Quoted 4 lines

+
+    soc {
+        compatible = "simple-bus";
+        interrupt-parent = <&plic>;

Do we really need this interrupt-parent? Seems it is causing a dependency cycle:

platform soc: Fixed dependency cycle(s) with /soc/interrupt-controller@c000000

And seems fu740 dts doesn't have this.

Quoted 53 lines

+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;

arch/riscv/boot/dts/starfive/jh7110.dtsi new file +49 -0

+
+        clint: timer@2000000 {
+            compatible = "starfive,jh7110-clint", "sifive,clint0";
+            reg = <0x0 0x2000000 0x0 0x10000>;
+            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+                          <&cpu1_intc 3>, <&cpu1_intc 7>,
+                          <&cpu2_intc 3>, <&cpu2_intc 7>,
+                          <&cpu3_intc 3>, <&cpu3_intc 7>,
+                          <&cpu4_intc 3>, <&cpu4_intc 7>;
+        };
+
+        ccache: cache-controller@2010000 {
+            compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+            reg = <0x0 0x2010000 0x0 0x4000>;
+            interrupts = <1>, <3>, <4>, <2>;
+            cache-block-size = <64>;
+            cache-level = <2>;
+            cache-sets = <2048>;
+            cache-size = <2097152>;
+            cache-unified;
+        };
+
+        plic: interrupt-controller@c000000 {
+            compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+            reg = <0x0 0xc000000 0x0 0x4000000>;
+            interrupts-extended = <&cpu0_intc 11>,
+                          <&cpu1_intc 11>, <&cpu1_intc 9>,
+                          <&cpu2_intc 11>, <&cpu2_intc 9>,
+                          <&cpu3_intc 11>, <&cpu3_intc 9>,
+                          <&cpu4_intc 11>, <&cpu4_intc 9>;
+            interrupt-controller;
+            #interrupt-cells = <1>;
+            #address-cells = <0>;
+            riscv,ndev = <136>;
+        };
+
+        uart0: serial@10000000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x10000000 0x0 0x10000>;
+            clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+                 <&syscrg JH7110_SYSCLK_UART0_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+            interrupts = <32>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            status = "disabled";
+        };
+

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi new file +4 -0

+	aliases {
+		i2c0 = &i2c0;
+		i2c2 = &i2c2;
+		i2c5 = &i2c5;

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi new file +4 -0

+	};
+
+	memory@40000000 {
+		device_type = "memory";

Hi Hal,

Quoted 7 lines

+    aliases {
+        i2c0 = &i2c0;
+        i2c2 = &i2c2;
+        i2c5 = &i2c5;
+        i2c6 = &i2c6;
+        serial0 = &uart0;
+    };

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi line 26

Quoted 7 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi new file +7 -0

+
+    chosen {
+        stdout-path = "serial0:115200n8";
+    };
+
+    cpus {
+        timebase-frequency = <4000000>;

Is mtime frequency on JH7110 could be modified?  If not, I think it's better

to put it into jh7110.dtsi.

Quoted 5 lines

+    };

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi new file +3 -0

+
+    memory@40000000 {
+        device_type = "memory";

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi line 40

Quoted 10 lines

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi new file +10 -0

+        reg = <0x0 0x40000000 0x1 0x0>;
+    };
+
+    gpio-restart {
+        compatible = "gpio-restart";
+        gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+        priority = <224>;
+    };
+};
+

Best regards,

Shengyu

This patch series adds basic clock, reset & DT support for StarFive JH7110 SoC.

@Stephen and @Conor, I have made this series start with the shared dt-bindings, so it will be easier to merge.

@Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the same with the patch [1] I submitted before, which you had accepted but not merge it into your branch.

Hey Hal,

Quoted 5 lines · Hal Feng

This patch series adds basic clock, reset & DT support for StarFive JH7110 SoC.

@Stephen and @Conor, I have made this series start with the shared dt-bindings, so it will be easier to merge.

Thanks. I probably should have asked for that, makes my life easier that's for sure!

Quoted 4 lines

@Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the same with the patch [1] I submitted before, which you had accepted but not merge it into your branch.

I hadn't merged that into anywhere, so I just went and dropped the original incarnation of that branch and have re-created it. I don't recall there being a maintainers pattern error (from running scripts/get_maintainer.pl --self-test=patterns) with what I had done in my branch, but with your patch 1 applied I see one. To save myself a complaint from LKP, I stripped out the MAINTAINERS bits from patch 1 into their own patch that can go with the clock/reset bits.

I squashed 22 into "riscv: dts: starfive: Add initial StarFive JH7110 device tree" since there's no reason to add something knowingly incorrect IMO.

I've gone and pushed out the following as riscv-jh7110_initial_dts:
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
riscv: dts: starfive: Add StarFive JH7110 pin function definitions
riscv: dts: starfive: Add initial StarFive JH7110 device tree
dt-bindings: riscv: Add SiFive S7 compatible
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

And the rest as riscv-jh7110_clk_reset:
MAINTAINERS: generalise StarFive clk/reset entries

reset: starfive: Add StarFive JH7110 reset driver
clk: starfive: Add StarFive JH7110 always-on clock driver
clk: starfive: Add StarFive JH7110 system clock driver
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: starfive: Extract the common JH71X0 reset code
reset: starfive: Factor out common JH71X0 reset code
reset: Create subdirectory for StarFive drivers
reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
clk: starfive: Factor out common JH7100 and JH7110 code
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

<https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/refs>

As it looks like everything has been resolved in terms of comments on v6, provided LKP doesn't complain or people don't spot something else, my plan is to send Stephen a PR around Wednesday for the driver bits.

Please LMK if I screwed up anything,
Conor.

Quoted 4 lines · Conor Dooley

On Sat, Apr 01, 2023 at 07:19:12PM +0800, Hal Feng wrote:

And the rest as riscv-jh7110_clk_reset:
MAINTAINERS: generalise StarFive clk/reset entries

For this patch, I find something to improve.
1. Could you please help me sort the StarFive entries in MAINTAINERS? "STARFIVE JH71X0 CLOCK DRIVERS" should be added after "STARFIVE JH7110 MMC/SD/SDIO DRIVER".

2. A "S" should be added at the end of
"STARFIVE JH7100 RESET CONTROLLER DRIVER".

I have tested your branch and have no comments on the other patches.

This patch series adds basic clock, reset & DT support for StarFive JH7110 SoC.

@Stephen and @Conor, I have made this series start with the shared dt-bindings, so it will be easier to merge.

@Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the same with the patch [1] I submitted before, which you had accepted but not merge it into your branch.

You can simply review or test the patches at the link [2]. Hope this series will be merged soon.

[1]: https://lore.kernel.org/all/[email protected]/
[2]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

Changes since v6:
- Rebased on v6.3-rc4.
- Made the dt-bindings patches (patch 11, 12) be the first two patches. Merged all maintainers changes into the first dt-bindings patch.
Patch 13:
- Moved the reset related functions from clk-starfive-jh71x0.c to clk-starfive-jh7110-sys.c.
- Moved the declaration of jh7110_reset_controller_register() to a new header clk-starfive-jh7110.h.
- Dropped the include <linux/clk.h> and added <linux/auxiliary_bus.h>.
- Included "clk-starfive-jh7110.h" instead of "clk-starfive-jh71x0.h".
- Set the qspi clock flags as 0.
- Set the flag of clock gmac?_gtxc as 0 and added CLK_SET_RATE_NO_REPARENT flag for the clock gmac1_tx.
- Removed the PLL clock return in jh7110_sysclk_get().
- Used "else" instead of "else if (pidx >= JH7110_SYSCLK_PLL0_OUT && \
pidx <= JH7110_SYSCLK_PLL2_OUT)".
- Renamed the reset aux device name from "reset-sys" to "rst-sys" avoiding exceeding the maximum length of auxiliary_device_id name.
Patch 14:
- Dropped the include <linux/clk.h>
- Included "clk-starfive-jh7110.h" instead of "clk-starfive-jh71x0.h".
- Added CLK_SET_RATE_NO_REPARENT flag for the clock gmac0_tx.
- Renamed the reset aux device name from "reset-aon" to "rst-aon". Patch 15:
- Changed the auxiliary_device_id name from "clk_starfive_jh71x0.reset-*" to "clk_starfive_jh7110_sys.rst-*".

v6: https://lore.kernel.org/all/[email protected]/

Changes since v5:
- Rebased on v6.3-rc3.
Patch 1:
- Set obj-y for starfive/ in drivers/clk/Makefile.
Patch 2:
- Sorted the StarFive entries alphabetically in MAINTAINERS. Patch 3:
- Fixed the build error which caused by renaming the header without changing the users of the header.
Patch 4:
- Fixed the errors reported by checkpatch.pl.
Patch 6:
- Set obj-y for starfive/ in drivers/reset/Makefile. Patch 13:
- Set the timer clock flags as 0.

v5: https://lore.kernel.org/all/[email protected]/

Changes since v4:
- Rebased on v6.3-rc1.
- Added two patches to replace SOC_STARFIVE with ARCH_STARFIVE.
- Added Tested-by tag for Tommaso.
Patch 9:
- Set GMAC1 related clocks as optional inputs.
- Dropped PLL clock definitions.
Patch 10:
- Set GMAC0 related clocks and RTC oscillator as optional inputs.
- Sorted the clocks.
Patch 11:
- Replaced SOC_STARFIVE with ARCH_STARFIVE.
- Added macros for PLL clocks and adjusted the code properly to make it easier to add the PLL clock driver later.
- Updated the clock flags.
Patch 12:
- Built as a module by default.
- Sorted the clocks.
- Updated the clock flags.
Patch 13:
- Replaced "default CLK_STARFIVE_JH7110_SYS" with "default ARCH_STARFIVE".
- Renamed "reset_info" struct to "jh7110_reset_info" and moved its definition into the driver.
- Put jh7110_sys_info and jh7110_sys_info before the probe(). Patch 17:
- Dropped "_zicsr" in ISA.
- Sorted the external clocks alphabetically.
- Put the ccache node before the plic node according to their addresses.
- Sorted the clock inputs of the aoncrg node.
Patch 19:
- Replaced SOC_STARFIVE with ARCH_STARFIVE.
- Sorted the nodes alphabetically.

v4: https://lore.kernel.org/all/[email protected]/

Changes since v3:
- Suggested by Conor, Merged clock & reset series and DT series together so that they could go via the same tree as the dt-binding headers are required by both driver & devicetree.
- Rebased on tag v6.2.

[Clock & reset]
Patch 2:
- Split patch 2 into two. One for renaming file and one for renaming variables. (by Conor)
Patch 4:
- Split patch 4 into two. One for code movement and one for extraction. (by Conor)
Patch 5 & 9 & 10 & 11:
- Fixed the issues reported by kernel test robot.
Patch 9:
- Set (&priv->base) as driver data instead of (priv->base).
- Set the frequency of clock PLL0 as 1000MHz for Synchronizing with the lastest u-boot setting from StarFive. (by Emil)
- Used devm_kzalloc() instead of kzalloc() when registering aux device. Patch 10:
- Set (&priv->base) as driver data instead of (priv->base). Patch 11:
- Used (*base) to get the register base address instead of (base).

[Device tree]
- Dropped patch 1, 4, 5 because they were accepted.
- Added a new patch to add SiFive S7 compatible. (by Conor)
- Added a new patch to add JH7110 pin function definitions. Patch 6:
- Changed the label "S76_0" to "S7_0" and used compatible "sifive,s7" for core 0.
- Updated ISA of each cores. (by Conor)
- Made the node names generic. (by Krzysztof)
- Added clock-output-names for all external clocks.
- Added i2c0~6 nodes.
- Changed the node name "gpio" to "pinctrl". Changed the label "gpio" and "gpioa" to "sysgpio" and "aongpio". (by Conor)
Patch 7:
- Separated the long lines into more lines in Makefile. (by Conor)
- Renamed jh7110-starfive-visionfive-2-va.dts and jh7110-starfive-visionfive-2-vb.dts to jh7110-starfive-visionfive-2-v1.2a.dts and jh7110-starfive-visionfive-2-v1.3b.dts.
Changed the model and compatible to match v1.2A and v1.3B which are printed on the silkscreen of VisionFive 2 board. (by Emil)
- Configured pins for i2c0/2/5/6 and enabled them.

clock & reset v3: https://lore.kernel.org/all/[email protected]/
DT v3: https://lore.kernel.org/all/[email protected]/

Changes since v2:
[Clock & reset]
- Rebased on tag v6.1.
- Added "JH71X0" to the StarFive driver headers in MAINTAINERS.
- Removed Co-developed-by tag of Hal in patch 1 and patch 4.
- Changed the commit author from Hal to Emil in patch 2 and patch 5. Removed Co-developed-by tag of Emil in patch 2 and patch 5. (by Emil)
- Improved the coding style of patch 11, 12 and 13.
- Dropped patch 14. (by Emil)
Patch 4:
- Passed the "owner" member of reset_controller_dev structure directly in reset_starfive_jh7100_register(). (by Emil)
- Added MAINTAINERS changes.
Patch 7:
- Split patch 7 into sys part and aon part. Merged them into patch 9 and patch 10 respectively. (by Krzysztof)
- Renamed include/dt-bindings/clock/starfive-jh7110.h to include/dt-bindings/clock/starfive,jh7110-crg.h. (by Krzysztof)
- Synchronized the definitions with the latest changes from Emil. Patch 8:
- Split patch 8 into sys part and aon part. Merged them into patch 9 and patch 10 respectively. (by Krzysztof)
- Renamed include/dt-bindings/reset/starfive-jh7110.h to include/dt-bindings/reset/starfive,jh7110-crg.h. (by Krzysztof)
- Fixed the date of Copyright. (by Emil)
- Dropped weird indentations. (by Krzysztof)
- Synchronized the definitions with the latest changes from Emil. Patch 9:
- Improved the description of clocks. (by Emil and Krzysztof)
- Added MAINTAINERS changes.
Patch 10:
- Improved the description of clocks. (by Emil and Krzysztof)
- Changed the clock-name "clk_rtc" to "rtc_osc" and "apb_bus_func" to "apb_bus".
Patch 11:
- Removed the flags of trace/debug clocks and set the flags of core clocks as CLK_IS_CRITICAL. (by Emil)
- Deleted the extra 1-1 clocks and synchronized the clock tree with the latest changes from Emil. (by Emil)
- Selected RESET_STARFIVE_JH7110 in Kconfig option CLK_STARFIVE_JH7110_SYS. Patch 12:
- Changed the macro JH7110_AONCLK_RTC to JH7110_AONCLK_RTC_OSC and JH7110_AONCLK_APB_BUS_FUNC to JH7110_AONCLK_APB_BUS.
- Synchronized the clock tree with the latest changes from Emil.
- Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db. Patch 13:
- Removed the "asserted" member in reset_info structure and always pass NULL when calling reset_starfive_jh71x0_register(). (by Emil)

[Device tree]
- Rebased on tag v6.1.
- Dropped patch 8 because it was merged.
Patch 1:
- Made the links into "Link:" tags. (by Conor)
- Corrected the board name to "VisionFive 2" instead of "VisionFive V2" and added compatibles for version A and version B of VisionFive 2. (by Emil)
Patch 4:
- Used "sifive,ccache0" compatible string to match. (by Conor) Patch 5:
- Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
- Dropped "starfive,jh7110-ccache" compatible in drivers/soc/sifive/sifive_ccache.c.
Patch 6:
- Removed all "clock-frequency = <0>". (by Conor)
- Sorted the nodes after their addresses. (by Emil)
- Renamed "clk_rtc" to "rtc_osc".
- Added "sifive,ccache0" compatible in the cache-controller node.
- Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and renamed "apb_bus_func" to "apb_bus".
Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB". Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB". Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
- Removed "reg-names" in gpio nodes.
Patch 7:
- Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
- Renamed jh7110-starfive-visionfive-v2.dts to jh7110-starfive-visionfive-2.dtsi.
- Added dts for VisionFive 2 version A and version B boards.
- In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end" and changed the value of "stdout-path" to "serial0:115200n8".
- Changed the bias of uart0 "rx-pins" to
"bias-disable; /* external pull-up */".
- Renamed "clk_rtc" to "rtc_osc".
- Moved the gpio node behind the uart0 node.

clock & reset v2: https://lore.kernel.org/all/[email protected]/
DT v2: https://lore.kernel.org/all/[email protected]/

Changes since v1:
[Clock & reset]
- Rebased on tag v6.1-rc5.
- Rewrote the clock and reset drivers using auxiliary bus framework, so patch 8, 9, 15 were dropped and all patches changed a lot. (by Stephen)
- Split Patch 14 into two patches. One is for factoring out the common JH71X0 code, the another one is for renaming. (by Stephen)
- Created a subdirectory for StarFive reset drivers.
- Factored out common JH71X0 reset code.
- Renamed the common clock and reset code from "*starfive*" or "*STARFIVE*" to "*jh71x0*" or "*JH71X0*".
- Combined JH7110 system and always-on clock DT binding headers in one file named "include/dt-bindings/clock/starfive-jh7110.h".
- Renamed clock definitions "JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK" and "JH7110_SYSCLK_U2_PCLK_MUX_PCLK" to "JH7110_SYSCLK_PCLK2_MUX_FUNC" and "JH7110_SYSCLK_PCLK2_MUX".
- Rewrote the DT bindings of clock and reset for using auxiliary bus.
- Registered an auxiliary device for reset controller in clock drivers.
- Changed clock names "CODAJ*" and "WAVE*" to "codaj*" and "wave*". Changed clock names "u2_pclk_mux_func_pclk" and "u2_pclk_mux_pclk" to "pclk2_mux_func" and "pclk2_mux".
- Changed the flags of clock apb0 and noc_bus_isp_axi to CLK_IS_CRITICAL as suggested by StarFive SDK group.
- Registered clock gmac0_gtxc as a gate clock instead of a div clock as suggested by StarFive SDK group.
- Changed the frequency of clock pll2_out to 1188MHz as suggested by StarFive SDK group.
- Fixed the bug that the clock JH7110_AONCLK_GMAC0_GTXCLK was not handled in JH7110 always-on clock driver.
- Registered the reset driver as an auxiliary driver.
- Reworded the commit messages.

[Device tree]
- Rebased on tag v6.1-rc5.
- Added blank line in patch 1. (by Krzysztof)
- Rebased patch 4 and 6 on the newest code. (by Conor)
- Dropped patch 5. (by Conor)
- Removed the quirk of JH7100 in patch 6, considering this patch series should only add support for JH7110.
- For patch 27, added Co-developed-by tag for Jianlong and me. Renamed cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts. Rewrote clock-controller nodes and deleted reset-controller nodes for using auxiliary bus. Rewrote gpio nodes following generic pinctrl bindings. Removed the redundant second reset entry of uart nodes.
- For patch 28, added Co-developed-by tag for Jianlong and me. Added a chosen node. Removed reserved-memory node. Added fixed frequency clock nodes for overriding the "clock-frequency" properties. Rewrote the gpio nodes following generic pinctrl bindings.
- Dropped patch 30. (by Conor)
- Reworded the commit messages.

v1: https://lore.kernel.org/all/[email protected]/

Emil Renner Berthing (16):
dt-bindings: clock: Add StarFive JH7110 system clock and reset
generator
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset
generator
clk: starfive: Factor out common JH7100 and JH7110 code
clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: Create subdirectory for StarFive drivers
reset: starfive: Factor out common JH71X0 reset code
reset: starfive: Extract the common JH71X0 reset code
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
clk: starfive: Add StarFive JH7110 system clock driver
clk: starfive: Add StarFive JH7110 always-on clock driver
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
riscv: dts: starfive: Add initial StarFive JH7110 device tree
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
tree

Hal Feng (5):
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
reset: starfive: Add StarFive JH7110 reset driver
dt-bindings: riscv: Add SiFive S7 compatible
riscv: dts: starfive: jh7110: Correct the properties of S7 core

Jianlong Huang (1):
riscv: dts: starfive: Add StarFive JH7110 pin function definitions

 .../clock/starfive,jh7110-aoncrg.yaml         | 107 +++
 .../clock/starfive,jh7110-syscrg.yaml         | 104 +++
 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 .../bindings/timer/sifive,clint.yaml          |   1 +
 MAINTAINERS                                   |  16 +-
 arch/riscv/boot/dts/starfive/Makefile         |   6 +-
 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++
 .../jh7110-starfive-visionfive-2-v1.2a.dts    |  13 +
 .../jh7110-starfive-visionfive-2-v1.3b.dts    |  13 +
 .../jh7110-starfive-visionfive-2.dtsi         | 215 ++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 500 ++++++++++++
 drivers/clk/Makefile                          |   2 +-
 drivers/clk/starfive/Kconfig                  |  33 +-
 drivers/clk/starfive/Makefile                 |   6 +-
 .../clk/starfive/clk-starfive-jh7100-audio.c  |  74 +-
 drivers/clk/starfive/clk-starfive-jh7100.c    | 716 +++++-------------
 drivers/clk/starfive/clk-starfive-jh7100.h    | 112 ---
 .../clk/starfive/clk-starfive-jh7110-aon.c    | 156 ++++
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 490 ++++++++++++
 drivers/clk/starfive/clk-starfive-jh7110.h    |  11 +
 drivers/clk/starfive/clk-starfive-jh71x0.c    | 333 ++++++++
 drivers/clk/starfive/clk-starfive-jh71x0.h    | 123 +++
 drivers/reset/Kconfig                         |   8 +-
 drivers/reset/Makefile                        |   2 +-
 drivers/reset/reset-starfive-jh7100.c         | 173 -----
 drivers/reset/starfive/Kconfig                |  20 +
 drivers/reset/starfive/Makefile               |   5 +
 .../reset/starfive/reset-starfive-jh7100.c    |  74 ++
 .../reset/starfive/reset-starfive-jh7110.c    |  70 ++
 .../reset/starfive/reset-starfive-jh71x0.c    | 131 ++++
 .../reset/starfive/reset-starfive-jh71x0.h    |  14 +
 .../dt-bindings/clock/starfive,jh7110-crg.h   | 221 ++++++
 .../dt-bindings/reset/starfive,jh7110-crg.h   | 154 ++++
 34 files changed, 3351 insertions(+), 862 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
 delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110.h
 create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
 delete mode 100644 drivers/reset/reset-starfive-jh7100.c
 create mode 100644 drivers/reset/starfive/Kconfig
 create mode 100644 drivers/reset/starfive/Makefile
 create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
 create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
 create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h

base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa --
2.38.1

This patch series adds basic clock, reset & DT support for StarFive JH7110 SoC.

@Stephen and @Conor, I have made this series start with the shared dt-bindings, so it will be easier to merge.

@Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the same with the patch [1] I submitted before, which you had accepted but not merge it into your branch.

[...]

From: Conor Dooley <[email protected]>

Quoted 6 lines · Hal Feng

This patch series adds basic clock, reset & DT support for StarFive JH7110 SoC.

@Stephen and @Conor, I have made this series start with the shared dt-bindings, so it will be easier to merge.

Quoted 5 lines

@Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the same with the patch [1] I submitted before, which you had accepted but not merge it into your branch.

[...]

Applied to riscv-dt-for-next, thanks!

[01/22] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

        https://git.kernel.org/conor/c/7fce1e39f019
[02/22] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
        https://git.kernel.org/conor/c/3de0c9103258

These two are shared with clk.

[16/22] dt-bindings: timer: Add StarFive JH7110 clint

        https://git.kernel.org/conor/c/1ff5482ab9a5
[17/22] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
        https://git.kernel.org/conor/c/8406d19ca049

I took these bindings too, as Palmer has done that in the past for new SoC support.

[18/22] dt-bindings: riscv: Add SiFive S7 compatible

        https://git.kernel.org/conor/c/8868caa2a073
[19/22] riscv: dts: starfive: Add initial StarFive JH7110 device tree
        https://git.kernel.org/conor/c/60bf0a39842e
[20/22] riscv: dts: starfive: Add StarFive JH7110 pin function definitions
        https://git.kernel.org/conor/c/e22f09e598d1
[21/22] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
        https://git.kernel.org/conor/c/54baba33392d

[22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core
(squashed)

Hal, can you get your folks to resend whatever dts bits that are now applicable? IOW, the dt-bindings for the entries are in a for-next branch for some subsystem.

Quoted 3 lines · Conor Dooley

Hal, can you get your folks to resend whatever dts bits that are now applicable? IOW, the dt-bindings for the entries are in a for-next branch for some subsystem.

Of course. As far as I know, these nodes include trng / pmu / mmc / qspi.

Quoted 7 lines · Hal Feng

Quoted 3 lines · Conor Dooley

Hal, can you get your folks to resend whatever dts bits that are now applicable? IOW, the dt-bindings for the entries are in a for-next branch for some subsystem.

Of course. As far as I know, these nodes include trng / pmu / mmc / qspi.

Just FYI, you can get the lads to resend them whenever, but it's too late for v6.4 now.