multiple cores and HT support
PATCH 1/2 multiple cores and HT support
This patch adds dual-core support to xen, and improves HT detection. The code is adapted from linux kernel 2.6.12.
Signed-off-by Nguyen Anh Quynh <[email protected]>
# diffstat core2.patch arch/x86/cpu/amd.c | 16 +++++++++------- arch/x86/cpu/common.c | 28 ++++++++++++++++++++-------- arch/x86/cpu/intel.c | 22 ++++++++++++++++++++++ arch/x86/dom0_ops.c | 4 ++-- arch/x86/setup.c | 1 - arch/x86/smpboot.c | 41 +++++++++++++++++++++++++++++++++++++---- common/dom0_ops.c | 4 ++-- include/asm-x86/processor.h | 1 + include/asm-x86/smp.h | 1 + include/xen/smp.h | 2 -- 10 files changed, 94 insertions(+), 26 deletions(-)
xen/arch/x86/cpu/amd.c +9 -7
@@ -193,7 +193,14 @@ static void __init init_amd(struct cpuin }display_cacheinfo (c); -detect_ht (c); + +if (cpuid_eax (0x80000000 ) >=0x80000008 ) { + c->x86_num_cores = (cpuid_ecx (0x80000008 ) &0xff ) +1 ; +if (c->x86_num_cores & (c->x86_num_cores -1 )) + c->x86_num_cores =1 ; + } + +detect_ht (c);#ifdef CONFIG_X86_HT /* AMD dual core looks like HT but isn't really. Hide it from the
@@ -203,13 +210,8 @@ static void __init init_amd(struct cpuinTBD tune the domain scheduler for dual core. */ if (cpu_has (c,X86_FEATURE_CMP_LEGACY )) smp_num_siblings =1 ; -#endif -if (cpuid_eax (0x80000000 ) >=0x80000008 ) { - c->x86_num_cores = (cpuid_ecx (0x80000008 ) &0xff ) +1 ; -if (c->x86_num_cores & (c->x86_num_cores -1 )) - c->x86_num_cores =1 ; - } +#endif }static unsigned int amd_size_cache (struct cpuinfo_x86 * c,unsigned int size)
xen/arch/x86/cpu/intel.c +22 -0
@@ -73,6 +73,26 @@ static void __init Intel_errata_workarou } } +/* +* find out the number of processor cores on the die +*/ +static int __init num_cpu_cores (struct cpuinfo_x86 *c) +{ +unsigned int eax; + +if (c->cpuid_level <4 ) +return 1 ; + + __asm__("cpuid" + :"=a" (eax) + :"0" (4 ),"c" (0 ) + :"bx" ,"dx" ); + +if (eax &0x1f ) +return ((eax >>26 ) +1 ); +else +return 1 ; +}static void __init init_intel (struct cpuinfo_x86 *c) {
@@ -136,6 +156,8 @@ static void __init init_intel(struct cpuif ( p )strcpy (c->x86_model_id, p); + c->x86_num_cores =num_cpu_cores (c); +detect_ht (c);/* Work around errata */
xen/arch/x86/dom0_ops.c +2 -2
@@ -179,8 +179,8 @@ long arch_do_dom0_op(dom0_op_t *op, dom0 {dom0_physinfo_t *pi = &op->u.physinfo; - pi->ht_per_core = ht_per_core; - pi->cores =num_online_cpus () / ht_per_core; + pi->ht_per_core = smp_num_siblings; + pi->cores = boot_cpu_data.x86_num_cores; pi->total_pages = max_page; pi->free_pages =avail_domheap_pages (); pi->cpu_khz = cpu_khz;
xen/arch/x86/setup.c +0 -1
@@ -66,7 +66,6 @@ boolean_param("noapic", skip_ioapic_setuint early_boot =1 ; -int ht_per_core =1 ;cpumask_t cpu_present_map;/* Limits of Xen heap, used to initialise the allocator. */
xen/arch/x86/smpboot.c +37 -4
105 lines not on this page · raw message
xen/common/dom0_ops.c +2 -2
@@ -184,8 +184,8 @@ long do_dom0_op(dom0_op_t *u_dom0_op)* domains will all share the second HT of each CPU. Since dom0 is on * CPU 0, we favour high numbered CPUs in the event of a tie. */ - pro = ht_per_core -1 ; -for ( i = pro; i <num_online_cpus (); i += ht_per_core ) + pro = smp_num_siblings -1 ; +for ( i = pro; i <num_online_cpus (); i += smp_num_siblings)if ( cnt[i] <= cnt[pro] ) pro = i;
xen/include/asm-x86/processor.h +1 -0
@@ -181,6 +181,7 @@ extern struct cpuinfo_x86 cpu_data[];#endif extern int phys_proc_id[NR_CPUS ]; +extern int cpu_core_id[NR_CPUS ];extern void identify_cpu (struct cpuinfo_x86 *);extern void print_cpu_info (struct cpuinfo_x86 *);
xen/include/asm-x86/smp.h +1 -0
@@ -34,6 +34,7 @@ extern void smp_alloc_memory(void);extern int pic_mode;extern int smp_num_siblings;extern cpumask_t cpu_sibling_map[]; +extern cpumask_t cpu_core_map[];extern void smp_flush_tlb (void );extern void smp_invalidate_rcv (void );/* Process an NMI */
xen/include/xen/smp.h +0 -2
@@ -58,8 +58,6 @@ static inline int on_each_cpu(void (*funreturn ret; } -extern int ht_per_core; -extern volatile unsigned long smp_msg_data;extern volatile int smp_src_cpu;extern volatile int smp_msg_id;
xen/arch/x86/cpu/common.c +20 -8
@@ -431,7 +431,7 @@ void __init dodgy_tsc(void)void __init detect_ht (struct cpuinfo_x86 *c) {u32 eax, ebx, ecx, edx; -int index_lsb, index_msb, tmp; +int index_msb, tmp;int cpu =smp_processor_id ();if (!cpu_has (c,X86_FEATURE_HT ))
@@ -443,7 +443,6 @@ void __init detect_ht(struct cpuinfo_x86if (smp_num_siblings ==1 ) {printk (KERN_INFO "CPU: Hyper-Threading is disabled\n" ); }else if (smp_num_siblings >1 ) { - index_lsb =0 ; index_msb =31 ;if (smp_num_siblings >NR_CPUS ) {
@@ -452,21 +451,34 @@ void __init detect_ht(struct cpuinfo_x86return ; } tmp = smp_num_siblings; -while ((tmp &1 ) ==0 ) { - tmp >>=1 ; - index_lsb++; - } - tmp = smp_num_siblings;while ((tmp &0x80000000 ) ==0 ) { tmp <<=1 ; index_msb--; } -if (index_lsb != index_msb ) +if (smp_num_siblings & (smp_num_siblings -1 )) index_msb++; phys_proc_id[cpu] =phys_pkg_id ((ebx >>24 ) &0xFF , index_msb);printk (KERN_INFO "CPU: Physical Processor ID: %d\n" , phys_proc_id[cpu]); + + smp_num_siblings = smp_num_siblings / c->x86_num_cores; + + tmp = smp_num_siblings; + index_msb =31 ; +while ((tmp &0x80000000 ) ==0 ) { + tmp <<=1 ; + index_msb--; + } + +if (smp_num_siblings & (smp_num_siblings -1 )) + index_msb++; + + cpu_core_id[cpu] =phys_pkg_id ((ebx >>24 ) &0xFF , index_msb); + +if (c->x86_num_cores >1 ) +printk (KERN_INFO "CPU: Processor Core ID: %d\n" , + cpu_core_id[cpu]); } }#endif
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