mips: mscc: Add multi-dtb support to luton+ocelot

This patch series add support for using multi-dtb on the MSCC luton and ocelot SOC reference boards. The appropriate board will be determined during startup, and the right DT will be selected.

The patch is based off u-boot-mips repo.

Lars Povlsen (6):
mips: luton+ocelot: Remove board-specific config options
mips: mscc: Add generic PHY MIIM utility functions
mips: mscc: Add generic GPIO control utility function
mips: luton: DT: Add pcb090
mips: luton: Add multi-dtb support
mips: ocelot: Add multi-dtb support

 arch/mips/dts/Makefile                        |  2 +
 arch/mips/dts/luton_pcb090.dts                | 36 +++++++++
 arch/mips/mach-mscc/Kconfig                   | 38 +++-------
 arch/mips/mach-mscc/Makefile                  |  2 +-
 arch/mips/mach-mscc/gpio.c                    | 33 +++++++++
 arch/mips/mach-mscc/include/mach/common.h     | 22 ++++++
 .../include/mach/luton/luton_devcpu_gcb.h     |  4 +
 .../mach/luton/luton_devcpu_gcb_miim_regs.h   | 26 +++++++
 .../include/mach/ocelot/ocelot_devcpu_gcb.h   |  2 +
 .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++++++
 arch/mips/mach-mscc/phy.c                     | 73 +++++++++++++++++++
 board/mscc/luton/luton.c                      | 46 +++++++++++-
 board/mscc/ocelot/ocelot.c                    | 52 +++++++++++--
 configs/mscc_luton_defconfig                  |  7 +-
 configs/mscc_ocelot_defconfig                 |  7 +-
 configs/mscc_ocelot_pcb120_defconfig          | 60 ---------------
 include/configs/vcoreiii.h                    |  2 +
 17 files changed, 333 insertions(+), 104 deletions(-)
 create mode 100644 arch/mips/dts/luton_pcb090.dts
 create mode 100644 arch/mips/mach-mscc/gpio.c
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
 create mode 100644 arch/mips/mach-mscc/phy.c
 delete mode 100644 configs/mscc_ocelot_pcb120_defconfig

2.19.2

As we are moving to multi-dtb and board detection, remove static board config options.

---
 arch/mips/mach-mscc/Kconfig | 38 ++++++++++---------------------------
 1 file changed, 10 insertions(+), 28 deletions(-)

index 0e35b77c9d..37ef432e48 100644
@@ -15,47 +15,29 @@ config SOC_VCOREIII
 config SYS_SOC
 	default "mscc"
 
+choice
+
+	prompt "SOC Family Variant"
+
 config SOC_OCELOT
-	bool
+	bool "Ocelot SOC Family"
 	select SOC_VCOREIII
+	select DESIGNWARE_SPI
 	help
 	  This supports MSCC Ocelot family of SOCs.
 
 config SOC_LUTON
-	bool
+	bool "Luton SOC Family"
 	select SOC_VCOREIII
+	select MSCC_BITBANG_SPI_GPIO
 	help
 	  This supports MSCC Luton family of SOCs.
 
+endchoice
+
 config SYS_CONFIG_NAME
 	default "vcoreiii"
 
-choice
-	prompt "Board select"
-
-config TARGET_OCELOT_PCB120
-	bool "MSCC PCB120 Reference Board (aka VSC5635EV)"
-	select SOC_OCELOT
-	help
-	  When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
-	  ocelot_pcb120
-
-config TARGET_OCELOT_PCB123
-	bool "MSCC PCB123 Reference Board (aka VSC7514EV))"
-	select SOC_OCELOT
-	help
-	  When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
-	  ocelot_pcb123
-
-config TARGET_LUTON_PCB091
-	bool "MSCC PCB091 Reference Board"
-	select SOC_LUTON
-	select MSCC_BITBANG_SPI_GPIO
-	help
-	  When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
-	  luton_pcb091
-endchoice
-
 choice
 	prompt "DDR type"
 

2.19.2

Am 19.12.18 um 13:42 schrieb Lars Povlsen:

This patch should be squashed into the last commit to not break bisectability. After only applying this patch you can't build any Ocelot/Luton baords anymore until the last patch is applied. Otherwise the series looks good.

- Daniel

Thank you for the comments - makes totally sense.

Actually then the first and the last two patches should be squashed, as the Kconfig and *_defconfigs need to go hand in hand.

I will send a new (v2) patch asap.

Cheers,

---Lars

The PHY MIIM utility functions can/will be used for board detection purposes.

---
 arch/mips/mach-mscc/Makefile                  |  2 +-
 arch/mips/mach-mscc/include/mach/common.h     | 20 +++++
 .../mach/luton/luton_devcpu_gcb_miim_regs.h   | 26 +++++++
 .../mach/ocelot/ocelot_devcpu_gcb_miim_regs.h | 25 +++++++
 arch/mips/mach-mscc/phy.c                     | 73 +++++++++++++++++++
 5 files changed, 145 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
 create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
 create mode 100644 arch/mips/mach-mscc/phy.c

index 6c60f26ca4..300c88b5cd 100644
@@ -2,5 +2,5 @@
 
 CFLAGS_cpu.o += -finline-limit=64000
 
-obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
 obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o

index 931ecd7985..92a055561e 100644
@@ -9,10 +9,12 @@
 #if defined(CONFIG_SOC_OCELOT)
 #include <mach/ocelot/ocelot.h>
 #include <mach/ocelot/ocelot_devcpu_gcb.h>
+#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h>
 #include <mach/ocelot/ocelot_icpu_cfg.h>
 #elif defined(CONFIG_SOC_LUTON)
 #include <mach/luton/luton.h>
 #include <mach/luton/luton_devcpu_gcb.h>
+#include <mach/luton/luton_devcpu_gcb_miim_regs.h>
 #include <mach/luton/luton_icpu_cfg.h>
 #else
 #error Unsupported platform

@@ -25,4 +27,22 @@
 
 #define VCOREIII_TIMER_DIVIDER 25	/* Clock tick ~ 0.1 us */
 
+/* Common utility functions */
+
+int mscc_phy_rd_wr(u8 read,
+		   u32 miim_controller,
+		   u8 miim_addr,
+		   u8 addr,
+		   u16 *value);
+
+int mscc_phy_rd(u32 miim_controller,
+		u8 miim_addr,
+		u8 addr,
+		u16 *value);
+
+int mscc_phy_wr(u32 miim_controller,
+		u8 miim_addr,
+		u8 addr,
+		u16 value);
+
 #endif				/* __ASM_MACH_COMMON_H */

new file mode 100644
index 0000000000..2303734894
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Microsemi Ocelot Switch driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_LUTON_MIIM_REGS_H_
+#define _MSCC_LUTON_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36))
+#define MIIM_MII_CMD(gi)    (0xa8 + (gi * 36))
+#define MIIM_MII_DATA(gi)   (0xac + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x)   (x ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)        (x ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x)      (GENMASK(29, 25) & (x << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x)      (GENMASK(24, 20) & (x << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x)     (GENMASK(19, 4) & (x << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x)  (GENMASK(2, 1) & (x << 1))
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS     GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x)   ((x >> 0) & GENMASK(15, 0))
+
+#endif

new file mode 100644
index 0000000000..4ad92214a3
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
+#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
+
+#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
+#define MIIM_MII_CMD(gi)    (0xa4 + (gi * 36))
+#define MIIM_MII_DATA(gi)   (0xa8 + (gi * 36))
+
+#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x)   ((x) ? BIT(3) : 0)
+
+#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x)        ((x) ? BIT(31) : 0)
+#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x)      (GENMASK(29, 25) & ((x) << 25))
+#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x)      (GENMASK(24, 20) & ((x) << 20))
+#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x)     (GENMASK(19, 4) & ((x) << 4))
+#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x)  (GENMASK(2, 1) & ((x) << 1))
+#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x)       ((x) ? BIT(0) : 0)
+
+#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS     GENMASK(17, 16)
+#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x)   (((x) >> 0) & GENMASK(15, 0))
+
+#endif

2.19.2

The GPIO control function can be used for controlling alternate functions associated with a GPIO.

---
 arch/mips/mach-mscc/Makefile                  |  2 +-
 arch/mips/mach-mscc/gpio.c                    | 33 +++++++++++++++++++
 arch/mips/mach-mscc/include/mach/common.h     |  2 ++
 .../include/mach/luton/luton_devcpu_gcb.h     |  2 ++
 .../include/mach/ocelot/ocelot_devcpu_gcb.h   |  2 ++
 5 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/mach-mscc/gpio.c

index 300c88b5cd..44538b7118 100644
@@ -2,5 +2,5 @@
 
 CFLAGS_cpu.o += -finline-limit=64000
 
-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
 obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o

new file mode 100644
index 0000000000..5e3a53372d
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void mscc_gpio_set_alternate(int gpio, int mode)
+{
+	u32 mask = BIT(gpio);
+	u32 val0, val1;
+
+	val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
+	val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
+
+	if (mode == 1) {
+		val0 |= mask;
+		val1 &= ~mask;
+	} else if (mode == 2) {
+		val0 &= ~mask;
+		val1 |= mask;
+	} else if (mode == 3) {
+		val0 |= mask;
+		val1 |= mask;
+	} else {
+		val0 &= ~mask;
+		val1 &= ~mask;
+	}
+
+	writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
+	writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
+}

index 92a055561e..d18ae78bfd 100644
@@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
 		u8 addr,
 		u16 value);
 
+void mscc_gpio_set_alternate(int gpio, int mode);
+
 #endif				/* __ASM_MACH_COMMON_H */

index 8c0b612325..a06cf819b0 100644
@@ -11,4 +11,6 @@
 #define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
 #define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
 
+#define GPIO_ALT(x)				(0x88 + 4 * (x))
+
 #endif

index f8aa97ba26..d3a76412e2 100644
@@ -18,4 +18,6 @@
 
 #define PERF_GPIO_OE                                      0x44
 
+#define GPIO_ALT(x)				(0x54 + 4 * (x))
+
 #endif

2.19.2

This prepares individual device trees for MSCC luton-based reference boards - pcb090 and pcb091.

Note: Even though the devices trees are quite common, they will differ significantly in coming patches.

---
 arch/mips/dts/luton_pcb090.dts | 36 ++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/mips/dts/luton_pcb090.dts

new file mode 100644
index 0000000000..a3f8926ad9
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+	model = "Luton26 PCB090 Reference Board";
+	compatible = "mscc,luton-pcb090", "mscc,luton";
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	spi-flash at 0 {
+		compatible = "spi-flash";
+		spi-max-frequency = <18000000>; /* input clock */
+		reg = <0>; /* CS0 */
+		spi-cs-high;
+	};
+};
+

2.19.2

This add single-binary support for the two MSCC luton-based reference boards - pcb090 and pcb091.

---
 arch/mips/dts/Makefile                        |  1 +
 .../include/mach/luton/luton_devcpu_gcb.h     |  2 +
 board/mscc/luton/luton.c                      | 46 +++++++++++++++++--
 configs/mscc_luton_defconfig                  |  7 ++-
 include/configs/vcoreiii.h                    |  2 +
 5 files changed, 52 insertions(+), 6 deletions(-)

index 647d2bf0d5..3d436b2248 100644
@@ -17,6 +17,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f at st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
+dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
 
 targets += $(dtb-y)
 

index a06cf819b0..a74a68593d 100644
@@ -13,4 +13,6 @@
 
 #define GPIO_ALT(x)				(0x88 + 4 * (x))
 
+#define CHIP_ID					(0x08)
+
 #endif

index d7476c4863..03922f5379 100644
@@ -5,7 +5,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
 CONFIG_DEBUG_UART_CLOCK=208333333
 CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_SOC_LUTON=y
 CONFIG_DDRTYPE_MT47H128M8HQ=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_MIPS_BOOT_FDT=y

@@ -16,7 +16,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_LOGLEVEL=7
 CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb091 # "
+CONFIG_SYS_PROMPT="luton # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_ELF is not set

@@ -39,6 +39,9 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m at 1m(linux)"
 # CONFIG_ISO_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_OF_LIST="luton_pcb090 luton_pcb091"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y

index df89cdaebf..4ea5f40ec5 100644
@@ -22,6 +22,8 @@
 #endif
 #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_MIPS_TIMER_FREQ
 
+#define CONFIG_BOARD_TYPES
+
 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 #define CONFIG_ENV_OFFSET		(1024 * 1024)
 #define CONFIG_ENV_SIZE			(256 * 1024)

2.19.2

This add single-binary support for the two MSCC ocelot-based reference boards - pcb120 and pcb123.

The PHY ids on specific ports are used to determine the board type.

---
 arch/mips/dts/Makefile               |  1 +
 board/mscc/ocelot/ocelot.c           | 52 +++++++++++++++++++++---
 configs/mscc_ocelot_defconfig        |  7 ++--
 configs/mscc_ocelot_pcb120_defconfig | 60 ----------------------------
 4 files changed, 51 insertions(+), 69 deletions(-)
 delete mode 100644 configs/mscc_ocelot_pcb120_defconfig

index 3d436b2248..b61afe6504 100644
@@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f at st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
+dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
 
 targets += $(dtb-y)
 

index 5fa74db2ff..66451000d9 100644
@@ -5,7 +5,6 @@ CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x70100000
 CONFIG_DEBUG_UART_CLOCK=250000000
 CONFIG_ARCH_MSCC=y
-CONFIG_TARGET_OCELOT_PCB123=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y

@@ -14,7 +13,7 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_LOGLEVEL=7
 CONFIG_DISPLAY_CPUINFO=y
-CONFIG_SYS_PROMPT="pcb123 # "
+CONFIG_SYS_PROMPT="ocelot # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_ELF is not set

@@ -40,6 +39,9 @@ CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 # CONFIG_ISO_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
+CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y

@@ -63,5 +65,4 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_LZMA=y

2.19.2