PPC405EX(r) ECC and SDRAM Initialization Clean-ups

The primary goal of these changes is to unify some of the low-level SDRAM and ECC initialization code for the PPC4xx processors that use a common DDR2 SDRAM controller.

In particular, in the case of the 405EX[r], it must initialize SDRAM before a primordial stack is available since OCM doesn't exist and the data cache does not work for such a purpose. As a consequence, the ECC (and SDRAM) initialization code must be stack-free.

This change creates such a stack-free ecc_init() routine that should, nonetheless, still be compatiable from a C runtime environment.

In addition, the change cleans-up the Kilauea and Makalu SDRAM initialization code by polling SDRAM0_MCSTAT[MIC} as recommended by the AMCC AN2131 rather than just waiting some arbitrary period of time. Also, the final controller initialization is generalized by ORing in SDRAM_MCOPT2_DCEN_ENBALE rather than just slamming 0x28000000 into the register. This is to make way for a future patch that uses CFG_SDRAM0_* values for boards that use such low-level initialization so they might share this SDRAM init code. Finally, while niether Kilauea nor Makalu have ECC memory, code is added to init.S for each to demonstrate how ecc_init() would be called if it were available as a reference.

---
 board/amcc/kilauea/init.S |   53 +++++++++++--
 board/amcc/makalu/init.S  |   53 +++++++++++--
 cpu/ppc4xx/Makefile       |    1 +
 cpu/ppc4xx/ecc.S          |  195 +++++++++++++++++++++++++++++++++++++++++++++
 cpu/ppc4xx/sdram.c        |   47 +----------
 5 files changed, 292 insertions(+), 57 deletions(-)

index 053fe19..7603fcf 100644
@@ -36,6 +36,10 @@
 	ori     r4,r4,value at l	;	\
 	mtdcr   memcfgd,r4	;
 
+#if defined(CONFIG_SDRAM_ECC)
+	.extern	ecc_init
+#endif /* defined(CONFIG_SDRAM_ECC) */
+
 	.globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)

@@ -126,12 +130,19 @@ ext_bus_cntlr_init:
 	/* SDRAM0_MCOPT2 (0X21) Start initialization */
 	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
 
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
+	/*
+	 * Step 5: Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+	 * completion of initialization.
+	 */
 
-pll_wait:
-	bdnz	pll_wait
+	li      r4,SDRAM_MCSTAT
+	lis	r2,SDRAM_MCSTAT_MIC_COMP at h
+	ori	r2,r2,SDRAM_MCSTAT_MIC_COMP at l
+0:	mtdcr   memcfga,r4
+	mfdcr   r3,memcfgd
+	clrrwi	r3,r3,31		// Clear all bits except MCSTAT[MIC].
+	cmpw	cr7,r3,r2		// Check if MCSTAT[MIC] = 1.
+	bne+	cr7,0b			// No, not ready yet, keep polling.
 
 	/* Step 6 */
 

@@ -147,8 +158,36 @@ pll_wait:
 	/* SDRAM_RFDC */
 	mtsdram_as(SDRAM_RFDC, 0x00000209);
 
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
+	/*
+	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+	 *
+	 *   mcopt2 = mfsdram(SDRAM_MCOPT2)
+	 */
+
+	li	r4,SDRAM_MCOPT2
+	mtdcr	memcfga,r4
+	mfdcr	r3,memcfgd
+
+	/*
+	 *   mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE)
+	 */
+
+	mtdcr	memcfga,r4
+	oris	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE at h
+	ori	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE at l
+	mtdcr	memcfgd,r3
+
+#if defined(CONFIG_SDRAM_ECC)
+	mflr	r13
+	lis	r3,CFG_SDRAM_BASE at h
+	ori	r3,r3,CFG_SDRAM_BASE at l
+	lis	r4,(CFG_MBYTES_SDRAM << 20)@h
+	ori	r4,r4,(CFG_MBYTES_SDRAM << 20)@l
+	bl	ecc_init
+	mtlr	r13
+#endif /* defined(CONFIG_SDRAM_ECC) */
 #endif /* #ifndef CONFIG_NAND_U_BOOT */
+	
+	/* SDRAM is now ready for use. Return to the caller. */
 
 	blr

index 178c5c6..f1e7ad2 100644
@@ -31,6 +31,7 @@ START	+= start.o
 SOBJS	:= cache.o
 SOBJS	+= dcr.o
 SOBJS	+= kgdb.o
+SOBJS	+= ecc.o
 
 COBJS	:= 40x_spd_sdram.o
 COBJS	+= 44x_spd_ddr.o

---
 board/amcc/kilauea/init.S |   53 +++++++++++--
 board/amcc/makalu/init.S  |   53 +++++++++++--
 cpu/ppc4xx/Makefile       |    1 +
 cpu/ppc4xx/ecc.S          |  195 +++++++++++++++++++++++++++++++++++++++++++++
 cpu/ppc4xx/sdram.c        |   47 +----------
 5 files changed, 292 insertions(+), 57 deletions(-)

index 053fe19..7603fcf 100644
@@ -36,6 +36,10 @@
 	ori     r4,r4,value at l	;	\
 	mtdcr   memcfgd,r4	;
 
+#if defined(CONFIG_SDRAM_ECC)
+	.extern	ecc_init
+#endif /* defined(CONFIG_SDRAM_ECC) */
+
 	.globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)

@@ -126,12 +130,19 @@ ext_bus_cntlr_init:
 	/* SDRAM0_MCOPT2 (0X21) Start initialization */
 	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
 
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
+	/*
+	 * Step 5: Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+	 * completion of initialization.
+	 */
 
-pll_wait:
-	bdnz	pll_wait
+	li      r4,SDRAM_MCSTAT
+	lis	r2,SDRAM_MCSTAT_MIC_COMP at h
+	ori	r2,r2,SDRAM_MCSTAT_MIC_COMP at l
+0:	mtdcr   memcfga,r4
+	mfdcr   r3,memcfgd
+	clrrwi	r3,r3,31		// Clear all bits except MCSTAT[MIC].
+	cmpw	cr7,r3,r2		// Check if MCSTAT[MIC] = 1.
+	bne+	cr7,0b			// No, not ready yet, keep polling.
 
 	/* Step 6 */
 

@@ -147,8 +158,36 @@ pll_wait:
 	/* SDRAM_RFDC */
 	mtsdram_as(SDRAM_RFDC, 0x00000209);
 
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
+	/*
+	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+	 *
+	 *   mcopt2 = mfsdram(SDRAM_MCOPT2)
+	 */
+
+	li	r4,SDRAM_MCOPT2
+	mtdcr	memcfga,r4
+	mfdcr	r3,memcfgd
+
+	/*
+	 *   mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE)
+	 */
+
+	mtdcr	memcfga,r4
+	oris	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE at h
+	ori	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE at l
+	mtdcr	memcfgd,r3
+
+#if defined(CONFIG_SDRAM_ECC)
+	mflr	r13
+	lis	r3,CFG_SDRAM_BASE at h
+	ori	r3,r3,CFG_SDRAM_BASE at l
+	lis	r4,(CFG_MBYTES_SDRAM << 20)@h
+	ori	r4,r4,(CFG_MBYTES_SDRAM << 20)@l
+	bl	ecc_init
+	mtlr	r13
+#endif /* defined(CONFIG_SDRAM_ECC) */
 #endif /* #ifndef CONFIG_NAND_U_BOOT */
+	
+	/* SDRAM is now ready for use. Return to the caller. */
 
 	blr

index 178c5c6..f1e7ad2 100644
@@ -31,6 +31,7 @@ START	+= start.o
 SOBJS	:= cache.o
 SOBJS	+= dcr.o
 SOBJS	+= kgdb.o
+SOBJS	+= ecc.o
 
 COBJS	:= 40x_spd_sdram.o
 COBJS	+= 44x_spd_ddr.o

There are a couple of problems with your posting:

- there is no signed-off-by line
- there is no explanation what you're actually trying to add or to fix.
- there are coding style violations: C++ comments, trailing white space, ...
- the code contains way too many empty lines / vertical white space.
- even in pseudo code, the Coding style requirements apply; i. e. instead of
+ /*

	+        *   if (start >= end) {
	+        *       return;
	+        *   }   
	+        */
  please write
  	+       /*
	+        *   if (start >= end)
	+        *       return;
	+        */

etc.

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Your own mileage may vary.

Stefan already asked this... I would also like to understand why the data cache cannot be used for initial RAM as we do on so many other systems?

I hesitate to throw away good C code in favour of hard to read, hard to maintain assembly, especially if this also breaks with some of the U-Boot design principles.

There are coding style violations: C++ comments, trailing white space, indentation not consequently by TABs.

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Chapter 1 -- The story so  far:
In the beginning the Universe was created. This has  made  a  lot  of
people very angry and been widely regarded as a bad move.

Agreed. The changes were based on the comments in the Kilauea and Makalu board ports indicating that this had been attempted--twice--and didn't work.

I am escalating with AMCC to find out if this is a processor errata, board issue or just a programming issue that needs to be investigated further.

Again, agreed wholeheartedly though I have to remark that I made a particular effort to make the assembly as readable and as generalized as possible.

Regards,

Grant

The cache trick works fine on 405CR/405GP. Is the cache redesigned for 405EX. Why would they still call it a 405 if the core was redesigned?

I already sent an update to Grant privately on this. Here again:

The main problem is that the board crashes with an exception (0x200: Data machine check) when init RAM in dcache is used. This happens upon calling trap_init() in board_init_r(). The exception must be pending and is "activated" upon the trap_init() call. Either Grant (or somebody else?) will look into this, or I will try to look into is (again) in a few days.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

For those following this thread, here are the result of my investigations today:

When using the Haleakala board and configuring include/configs/kilauea.h as follows:

    #define CFG_SDRAM_BASE          0x00000000
    #define CFG_INIT_DCACHE_CS      3
    #define CFG_INIT_RAM_ADDR       (CFG_SDRAM_BASE + (1 << 30))

I find the following results while tracking the various exception-related registers:

    1) At _start + 0:
    
          MSR           :  0x0000 0000
          ESR (0x3D4)   :  0x0000 0000
          DEAR (0x3D5)  :  0x0000 0000
          SRR0 (0x01A)  :  0x0000 0700
          SRR1 (0x01B)  :  0x0000 0000
          SRR2 (0x3DE)  :  0xFFFA 8678 (NfsStart + 0x2c)
          SRR3 (0x3DF)  :  0x0000 0000
          MCSR (0x23C)  :  0x0000 0000
          MCAR (0x23D)  :  0x0000 0000
          MCSRR0 (0x23A):  0x0000 0000
          MCSRR1 (0x23B):  0x0000 0000

          EBC0_BEAR     :  0x0000 0000
          EBC0_BESR     :  0x0000 0000

    
    2) After both invalidate_icache() and invalidate_dcache() have run:
    
          <same>
    
    3) After a NOP ext_bus_cntlr_init() has run:
    
          <same>
       
    4) After PBxAP and PBxCR have been set-up for the desired EBC region:
    
          <same>

    5) After the data cacheability has been set for this range:

          MSR           :  0x0000 0000
          ESR (0x3D4)   :  0x0000 0000
          DEAR (0x3D5)  :  0x0000 0000
          SRR0 (0x01A)  :  0x0000 0700
          SRR1 (0x01B)  :  0x0000 0000
          SRR2 (0x3DE)  :  0xFFFA 8678 (NfsStart + 0x2c)
          SRR3 (0x3DF)  :  0x0000 0000
          MCSR (0x23C)  :  0x0000 0000
          MCAR (0x23D)  :  0x0000 0000
          MCSRR0 (0x23A):  0x0000 0000
          MCSRR1 (0x23B):  0x0000 0000

          EBC0_BEAR     :  0x0000 0000
        * EBC0_BESR     :  0x4000 0000 PERR=1

    5) Immediately after the following instruction runs:
    
           lis  r1,CFG_INIT_RAM_ADDR at h
    
          MSR           :  0x0000 0000
          ESR (0x3D4)   :  0x0000 0000
          DEAR (0x3D5)  :  0x0000 0000
          SRR0 (0x01A)  :  0x0000 0700
          SRR1 (0x01B)  :  0x0000 0000
          SRR2 (0x3DE)  :  0xFFFA 8678 (NfsStart + 0x2c)
          SRR3 (0x3DF)  :  0x0000 0000
        * MCSR (0x23C)  :  0xA000 0000 MCS = 1, DPLBE = 1
          MCAR (0x23D)  :  0x0000 0000
          MCSRR0 (0x23A):  0x0000 0000
          MCSRR1 (0x23B):  0x0000 0000

          EBC0_BEAR     :  0x0000 0000
          EBC0_BESR     :  0x4000 0000 PERR=1

However, the overall operation does appear to be working in terms of priming the primordial stack with known values:

    (gdb) info registers r2
    r2             0x40000fc4

    (gdb) print /x *$r2
    $1 = 0xdeaddead

    (gdb) x /64xw 0x40000FC0
    0x40000fc0:    0x00000000    0xdeaddead    0xdeaddead    0xdeaddead
    0x40000fd0:    0xdeaddead    0xdeaddead    0xdeaddead    0xdeaddead
    0x40000fe0:    0xdeaddead    0xdeaddead    0xdeaddead    0xdeaddead
    0x40000ff0:    0xdeaddead    0xdeaddead    0xdeaddead    0xdeaddead
    0x40001000:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001010:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001020:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001030:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001040:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001050:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001060:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001070:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001080:    0x00000000    0x00000000    0x00000000    0x00000000
    0x40001090:    0x00000000    0x00000000    0x00000000    0x00000000
    0x400010a0:    0x00000000    0x00000000    0x00000000    0x00000000
    0x400010b0:    0x00000000    0x00000000    0x00000000    0x00000000

Other Experiments Tried:

Changing:

#define CFG_INIT_DCACHE_CS 3

to 4, 5, 6, or 7 doesn't seem to make any difference except I then also seem to get BOTH IPLBE=1 and DPLBE=1 in MCSR for 4, 5, 6 or 7.

While this seems to work OK on older 405 variants, is there something new or different about the PLB to OPB to EBC bridges in the 405EX[r] relative to those older 405 variants that cause this CFG_INIT_DCACHE_CS primordial stack trick to raise an exception where the others before it did not?

Regards,

Grant