No more software ECC in omap2.c NAND driver. Why?
Between 2.6.35 and 2.6.36 there have need quite a few changes in the NAND driver, including a change from software to hardware ECC.
The new code has hardware ECC forced on by:
#define CONFIG_MTD_NAND_OMAP_HWECC
I am surprised that this was done. Surely this should have been a Kconfig option to select either sw ECC or hw ECC?
Does moving to hardware ECC to the exclusion of software ECC reduce functionality?
Does the new hwecc scheme still support sub-page writes or does it only provide full page writes? If sub-page writes are lost then this has a ripple effect in breaking the way some UBI stuff works.
-- Charles
Quoted 14 lines
-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Charles Manning
Sent: Thursday, November 18, 2010 6:36 AM
To: [email protected]
Subject: No more software ECC inomap2.cNAND driver. Why?Between 2.6.35 and 2.6.36 there have need quite a few changes in the NAND driver, including a change from software to hardware ECC.
The new code has hardware ECC forced on by:
Quoted 7 lines
#define
CONFIG_MTD_NAND_OMAP_HWECCI am surprised that this was done. Surely this should have been a
Kconfigoption to select either sw ECC or hw ECC?Does moving to hardware ECC to the exclusion of software ECC reduce functionality?
[Ghorai] This is wrongly added by me, during last few patches. So I have send the fix as you mentioned too as.
[PATCH] omap: nand: remove hardware ECC as default
And please let me know still if it has any issue.
And I am re-working on the patches for the different ecc schema including s/w, h/w or different, to pass it form board file.
Quoted 5 lines
Does the new hwecc scheme still support sub-page writes or does it only provide full page writes? If sub-page writes are lost then this has a ripple
effect in breaking the way some UBI stuff works.
[Ghorai]
1. do you think this sub-page read/write support was there before, say in 2.6.35? And breaks in 2.6.36?
2. In that case would you please let know what are the size(s) used for sub-page/read write?
Quoted 7 lines
-- Charles
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Quoted 17 lines · Sukumar
Quoted 17 lines
-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Charles Manning
Sent: Thursday, November 18, 2010 6:36 AM
To: [email protected]
Subject: No more software ECC inomap2.cNAND driver. Why?Between 2.6.35 and 2.6.36 there have need quite a few changes in the NAND driver, including a change from software to hardware ECC.
The new code has hardware ECC forced on by:
#define
CONFIG_MTD_NAND_OMAP_HWECCI am surprised that this was done. Surely this should have been a
Kconfigoption to select either sw ECC or hw ECC?
Quoted 8 lines
Quoted 2 lines
Does moving to hardware ECC to the exclusion of software ECC reduce functionality?
[Ghorai] This is wrongly added by me, during last few patches. So I have send the fix as you mentioned too as.
[PATCH] omap: nand: remove hardware ECC as defaultAnd please let me know still if it has any issue.
For me it makes normal sw ECC page IO work, but for subpages to work I have to disable the prefetch option.
Quoted 4 lines
And I am re-working on the patches for the different ecc schema including s/w, h/w or different, to pass it form board file.
Quoted 1 line
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Does the new hwecc scheme still support sub-page writes or does it only provide full page writes? If sub-page writes are lost then this has a ripple
effect in breaking the way some UBI stuff works.[Ghorai]
1. do you think this sub-page read/write support was there before, say in 2.6.35? And breaks in 2.6.36?
It certainly was there for sw ECC as we've been using UBI from 2.6.27 to 2.6.35 just fine.
Quoted 2 lines
2. In that case would you please let know what are the size(s) used for sub-page/read write?
512 bytes.
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Quoted 32 lines
-----Original Message-----
From: Grazvydas Ignotas [mailto:[email protected]]
Sent: Friday, November 19, 2010 4:06 PM
To: Ghorai, Sukumar
Cc: Charles Manning; [email protected]
Subject: Re: No more software ECC inomap2.cNAND driver. Why?Quoted 8 lines · Sukumar
Quoted 8 lines
-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Charles Manning
Sent: Thursday, November 18, 2010 6:36 AM
To: [email protected]
Subject: No more software ECC inomap2.cNAND driver. Why?Between 2.6.35 and 2.6.36 there have need quite a few changes in the
NAND
Quoted 7 lines
Quoted 7 lines
driver, including a change from software to hardware ECC.
The new code has hardware ECC forced on by:
#define
CONFIG_MTD_NAND_OMAP_HWECCI am surprised that this was done. Surely this should have been a
KconfigQuoted 5 lines
Quoted 4 lines
option to select either sw ECC or hw ECC?
Does moving to hardware ECC to the exclusion of software ECC reduce functionality?
Quoted 8 lines
Quoted 5 lines
[Ghorai] This is wrongly added by me, during last few patches. So I have send the fix as you mentioned too as.
[PATCH] omap: nand: remove hardware ECC as defaultAnd please let me know still if it has any issue.
For me it makes normal sw ECC page IO work, but for subpages to work I have to disable the prefetch option.
[Ghorai] I was thinking that I have modularize some GPMC call and did not do anything prefetch related modificaiton. I will check this too.
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And I am re-working on the patches for the different ecc schema
including
Quoted 8 lines
s/w, h/w or different, to pass it form board file.
Quoted 5 lines
Does the new hwecc scheme still support sub-page writes or does it only provide full page writes? If sub-page writes are lost then this has a ripple
effect in breaking the way some UBI stuff works.
Quoted 7 lines
Quoted 2 lines
[Ghorai]
1. do you think this sub-page read/write support was there before, sayin
Quoted 1 line
2.6.35? And breaks in 2.6.36?
It certainly was there for sw ECC as we've been using UBI from 2.6.27 to 2.6.35 just fine.
[Ghorai] uoderstand.
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2. In that case would you please let know what are the size(s) used for sub-page/read write?
512 bytes.
[Ghorai] I feel still its support in 2.6.36 too. Let me check too. --
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Quoted 17 lines · Sukumar
Quoted 17 lines
-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Charles Manning
Sent: Thursday, November 18, 2010 6:36 AM
To: [email protected]
Subject: No more software ECC inomap2.cNAND driver. Why?Between 2.6.35 and 2.6.36 there have need quite a few changes in the NAND driver, including a change from software to hardware ECC.
The new code has hardware ECC forced on by:
#define
CONFIG_MTD_NAND_OMAP_HWECCI am surprised that this was done. Surely this should have been a
Kconfigoption to select either sw ECC or hw ECC?
Quoted 8 lines
Quoted 2 lines
Does moving to hardware ECC to the exclusion of software ECC reduce functionality?
[Ghorai] This is wrongly added by me, during last few patches. So I have send the fix as you mentioned too as.
[PATCH] omap: nand: remove hardware ECC as defaultAnd please let me know still if it has any issue.
Just recompiling with the CONFIG_MTD_NAND_OMAP_HWECC define commented out did not result in a working system. I suspect there is more tto the problem than this.
Quoted 4 lines
And I am re-working on the patches for the different ecc schema including s/w, h/w or different, to pass it form board file.
Quoted 8 lines
Quoted 4 lines
Does the new hwecc scheme still support sub-page writes or does it only provide full page writes? If sub-page writes are lost then this has a ripple
effect in breaking the way some UBI stuff works.[Ghorai]
1. do you think this sub-page read/write support was there before, say in 2.6.35? And breaks in 2.6.36?
2.6.35 works with subpages of 512 bytes. Tested with UBIFS.
Quoted 3 lines
2. In that case would you please let know what are the size(s) used for sub-page/read write?
AFAIK, 512 is all that is needed. There is no need for any smaller or larger.
sub-page reads are not available on all flash types and sub-page writing causes extra write disturb. However, 512-byte sub-page writing is valuable.
This of course needs the ECC to be partitioned and performed in chunks of 256 or 512 so that the subpages can be written individually.
-- CHarles
Quoted 3 lines · Charles Manning
Just recompiling with the
CONFIG_MTD_NAND_OMAP_HWECCdefine commented out did not result in a working system. I suspect there is more tto the problem than this.
FWIW, I had the exact same issues with my Mistral AM37x EVM board. I not only had to remove/deassert CONFIG_MTD_NAND_OMAP_HWECC, but also had to roll back nand_base.c and nand_bbt.c back to their 2.6.32 versions (later ones between .32 and .35 might have worked but I didn't bother trying) to be able to read, error-free and correctly, NAND that was erased and written with a .32-era kernel.
Best,
Grant Erickson
Quoted 16 lines
-----Original Message-----
From: Grant Erickson [mailto:[email protected]]
Sent: Monday, November 22, 2010 11:39 AM
To: Charles Manning
Cc: [email protected]; Grazvydas Ignotas; Ghorai, Sukumar
Subject: Re: No more software ECC inomap2.cNAND driver. Why?Quoted 1 line · Charles Manning
Just recompiling with the
CONFIG_MTD_NAND_OMAP_HWECCdefine commentedout did
Quoted 1 line
not result in a working system. I suspect there is more tto the problem
than
Quoted 1 line
this.
Quoted 8 lines
FWIW, I had the exact same issues with my Mistral AM37x EVM board. I not only had to remove/deassert
CONFIG_MTD_NAND_OMAP_HWECC, but also had to roll
backnand_base.candnand_bbt.cback to their 2.6.32 versions (later ones between .32 and .35 might have worked but I didn't bother trying) to be able
to read, error-free and correctly, NAND that was erased and written with a .32-era kernel.
[Ghorai] are you trying again?
How do you flush the FS (form u-boot or from kernel, nandwrite)? And let me know the test you are doing, to know the steps to reproduce in my platform - zoom/sdp.
Quoted 5 lines
Best,
Grant Erickson
Quoted 23 lines · Sukumar
Quoted 14 lines
-----Original Message-----
From: Grant Erickson [mailto:[email protected]]
Sent: Monday, November 22, 2010 11:39 AM
To: Charles Manning
Cc: [email protected]; Grazvydas Ignotas; Ghorai, Sukumar
Subject: Re: No more software ECC inomap2.cNAND driver. Why?Quoted 1 line · Charles Manning
Just recompiling with the
CONFIG_MTD_NAND_OMAP_HWECCdefine commentedout did
Quoted 1 line
not result in a working system. I suspect there is more tto the problem
than
Quoted 1 line
this.
Quoted 8 lines
FWIW, I had the exact same issues with my Mistral AM37x EVM board. I not only had to remove/deassert
CONFIG_MTD_NAND_OMAP_HWECC, but also had to roll
backnand_base.candnand_bbt.cback to their 2.6.32 versions (later ones between .32 and .35 might have worked but I didn't bother trying) to be able
to read, error-free and correctly, NAND that was erased and written with a .32-era kernel.
Quoted 4 lines
[Ghorai] are you trying again?
How do you flush the FS (form u-boot or from kernel, nandwrite)? And let me know the test you are doing, to know the steps to reproduce in my platform - zoom/sdp.
The board (Mistral AM37x) NAND (Micron 256 MiB) was originally bootstrapped over SD/MMC from u-boot using the following script:
mmc init
mw.b ${loadaddr} 0xff 0x40000
nand erase 0 0x40000
fatload mmc 0 ${loadaddr} mlo
nandecc hw
nand write.i ${loadaddr} 0 0x40000
mw.b ${loadaddr} 0xff 0x180000
nand erase 0x00040000 0x180000
nand erase 0x001c0000 0x180000
fatload mmc 0 ${loadaddr} u-boot.bin
nandecc sw
nand write.i ${loadaddr} 0x00040000 0x180000
nand write.i ${loadaddr} 0x001c0000 0x180000
mw.b ${loadaddr} 0xff 0x800000
nand erase 0x00400000 0x800000
nand erase 0x03a00000 0x800000
fatload mmc 0 ${loadaddr} uImage
nand write.i ${loadaddr} 0x00400000 0x800000
nand write.i ${loadaddr} 0x03a00000 0x800000
mw.b ${loadaddr} 0xff 0x2000000
nand erase 0x00c00000 0x2000000
nand erase 0x04200000 0x2000000
fatload mmc 0 ${loadaddr} root.jff
nand write.i ${loadaddr} 0x00c00000 0x2000000
nand write.i ${loadaddr} 0x04200000 0x2000000Following that, the board is updated, from Linux, using 'flash_eraseall -q' and 'nandwrite -p -q' on all partitions, except that containing MLO.
Best,
Grant
[..snip..]
Quoted 4 lines
The board (Mistral AM37x) NAND (Micron 256 MiB) was originally bootstrapped
over SD/MMC from u-boot using the following script:
[Ghorai] let me know the nand details - x8/x16, small/big page?
Quoted 1 line
[..snip..]
Quoted 1 line
nandecc sw
[..snip..]
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fatload mmc 0 ${loadaddr} root.jff[Ghorai] How you create the root.jff
mkfs.jffs2 --output=root.jffs2 --root=.. --pagesize=?? --eraseblock=?? -n
Quoted 2 lines
nand write.i ${loadaddr} 0x00c00000 0x2000000
nand write.i ${loadaddr} 0x04200000 0x2000000[Ghorai] why you writing in two places?
Quoted 4 lines
Following that, the board is updated, from Linux, using '
flash_eraseall- q'
and 'nandwrite -p -q' on all partitions, except that containing MLO.
[Ghorai]
1. can you send the exact comment you used to write in nand? Which partition?
2. What is the last kernel you used and was working perfectly?
3. If possible revert the following patches and let me know the status? f450d86790ebf72ac93c7ea5addd6fa278aae64c..2430f9df61e2ea47ea468dfe22b7e2db97111fb4 2c01946c6b9ebaa5a89710bc42ca224a7f52f227 948d38e799f0ab87cf8ed9113fcdaaee61acf321
Quoted 5 lines · Sukumar
Quoted 3 lines
The board (Mistral AM37x) NAND (Micron 256 MiB) was originally bootstrapped
over SD/MMC from u-boot using the following script:[Ghorai] let me know the nand details - x8/x16, small/big page?
It's the Micron 256 MiB x16 2 KiB page size, 128 KiB erase block size device on the Mistral AM37x board.
Quoted 4 lines
Quoted 1 line
fatload mmc 0 ${loadaddr} root.jff[Ghorai] How you create the root.jff
mkfs.jffs2 --output=root.jffs2 --root=.. --pagesize=?? --eraseblock=?? -n
% mkfs.jffs2 --little-endian --no-cleanmarkers --pad 2048 --pagesize 2048 --eraseblock 131072 -d /tmp/tmp.h9dKGpcNFw -D root.devices -o root.jffs2
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nand write.i ${loadaddr} 0x00c00000 0x2000000 nand write.i ${loadaddr} 0x04200000 0x2000000[Ghorai] why you writing in two places?
Redundant images.
Quoted 6 lines
Quoted 3 lines
Following that, the board is updated, from Linux, using '
flash_eraseall- q'
and 'nandwrite -p -q' on all partitions, except that containing MLO.[Ghorai]
1. can you send the exact comment you used to write in nand? Which partition?
flash_eraseall -q /dev/mtd7
nandwrite -p -q /dev/mtd7 root.jffs2
flash_eraseal -q /dev/mtd9
nandwrite -p -q /dev/mtd9 root.jffs2
Quoted 1 line
2. What is the last kernel you used and was working perfectly?
v2.6.32_OMAPPSP_03.00.01.06.patch1
Best,
Grant
[..snip..]
Quoted 19 lines
% mkfs.jffs2 --little-endian --no-cleanmarkers --pad 2048 --pagesize 2048 --eraseblock 131072 -d
/tmp/tmp.h9dKGpcNFw-D root.devices -o root.jffs2Quoted 4 lines
Quoted 2 lines
nand write.i ${loadaddr} 0x00c00000 0x2000000 nand write.i ${loadaddr} 0x04200000 0x2000000[Ghorai] why you writing in two places?
Redundant images.
Quoted 1 line
Quoted 1 line
Following that, the board is updated, from Linux, using '
flash_eraseall-
Quoted 5 lines
Quoted 2 lines
q'
and 'nandwrite -p -q' on all partitions, except that containing MLO.[Ghorai]
1. can you send the exact comment you used to write in nand? Which
partition?
Quoted 7 lines
flash_eraseall-q/dev/mtd7
nandwrite -p -q/dev/mtd7root.jffs2
flash_eraseal-q/dev/mtd9
nandwrite -p -q/dev/mtd9root.jffs2Quoted 1 line
2. What is the last kernel you used and was working perfectly?
v2.6.32_OMAPPSP_03.00.01.06.patch1
[Ghorai] I followed the steps you mentioned. Also I used the following command to mount the jffs2 FS and working fine. mount -t jffs2 /dev/mtdblock3 /mnt/nand
I have tested in zoom3 -
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xbc (Micron NAND 512MiB 1,8V 16-bit).
And using the latest kernel -
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Linux version 2.6.37-rc3-00102-gea49b16 (a0393553@omapldc12) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #20 SMP Wed Nov 24 17:27:21 IST 2010
Would you please share your latest log?