85xx - DDR with ECC: Why DMA ?
I have a question about the procedure
ddr_enable_ecc()
included in the U-Boot build only if
CONFIG_DDR_ECC is defined
CONFIG_ECC_INIT_VIA_DDRCONTROLLER is not defined
The routine is found in file
./cpu/mpc85xx/spd_sdram.c
so is for the 8540 and 8560 products.
Most of the work in the routine seems to concern programming the DMA registers rather than setting the DDR "enable" flag.
Why is this DMA configuration an essential step when ECC is used and apparently not necessary when it is not used? I can?t see the link between the two.
Thanks,
Charles.
--------------------------------------------------------------------------
Dr Charles J Gillan
The Institute of Electronics, Communications and
Information Technology (ECIT),???????????????
Queen's University Belfast, Titanic Quarter
Queen?s Road, Queen?s Island, Belfast, BT3 9DT
Northern Ireland, UK
?
Tel: +44 (0) 2890 971847
Fax: +44 (0) 2890 971702
??
--------------------------------------------------------------------------
Hi, Charles!
Quoted 6 lines · Charles J Gillan
Most of the work in the routine seems to concern programming the DMA registers rather than setting the DDR "enable" flag.
Why is this DMA configuration an essential step when ECC is used and apparently not necessary when it is not used? I can?t see the link between the two.
A simple thing:
After power on, the memory content is undefined.
If you enable ECC before cleaning the whole memory and start reading data from the memory, you will run into ECC errors over and over...
Pls. take care when you want to use the DMA on mpc85xx after u-boot touched it for cleaning the DDR. I ran into a problem described in:
http://ozlabs.org/pipermail/linuxppc-embedded/2005-July/019196.html
Greets,
Clemens Koller
_______________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Str. 45/1
81379 Muenchen
Germany
http://www.anagramm.de
Phone: +49-89-741518-50
Fax: +49-89-741518-19