ARM: refactor start.S files

PATCH Superseded Albert ARIBAUD 3 participants 10 messages Apr 15, 2014 – May 15, 2014

Subsystems (4)

Arm (32-bit) Arm i.MX and Layerscape Arm/Zynq architecture Arm/actions semi architecture

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Albert ARIBAUD

author

2014-04-15 14:13 UTC #0 lore raw

v3 cover ARM: refactor start.S files

This series aims at refactoring start.S files. Some of these files contain cache-related or cpu-reset-related core, which is moved where it belongs. Useless symbols are removed, and finally, exception vector code, common across all ARM CPUs, is moved in its own file.

At this point, the start.S files only contain CPU-specific reset sequences.

Changes in v3:
- factorized SPL/non-SPL code
- fixed socfpga_cyclone5 IRQ setting in save_boot_params

Changes in v2:
- fixed checkpatch issues in arch/arm/cpu/arm946es/cpu.c
- fixed checkpatch issues in arch/arm/cpu/sa1100/cpu.c
- rebased onto u-boot-arm/master (de4fdfc1)
- adjusted comment in Zynq linker script

Albert ARIBAUD (5):
arm1136: move cache code from start.S to cache.c
arm: move reset_cpu from start.S into cpu.c
arm: pxa: move SP check from start.S to cpuinfo.c
arm: remove unused _end_vect and _vectors_end symbols
arm: move exception handling out of start.S files

 arch/arm/cpu/arm1136/start.S                | 254 +-----------------------
 arch/arm/cpu/arm1176/start.S                | 198 +------------------
 arch/arm/cpu/arm720t/start.S                | 229 +---------------------
 arch/arm/cpu/arm920t/ep93xx/u-boot.lds      |   3 +-
 arch/arm/cpu/arm920t/start.S                | 216 +--------------------
 arch/arm/cpu/arm926ejs/mxs/start.S          |  92 +--------
 arch/arm/cpu/arm926ejs/spear/start.S        |  27 +--
 arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds |   1 +
 arch/arm/cpu/arm926ejs/start.S              | 262 +------------------------
 arch/arm/cpu/arm946es/cpu.c                 |  13 ++
 arch/arm/cpu/arm946es/start.S               | 246 +----------------------
 arch/arm/cpu/arm_intcm/start.S              | 228 +---------------------
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S  |  15 +-
 arch/arm/cpu/armv7/start.S                  | 253 +-----------------------
 arch/arm/cpu/armv7/zynq/u-boot.lds          |   2 +-
 arch/arm/cpu/pxa/cpuinfo.c                  |   6 +
 arch/arm/cpu/pxa/start.S                    | 253 +-----------------------
 arch/arm/cpu/sa1100/cpu.c                   |  14 ++
 arch/arm/cpu/sa1100/start.S                 | 225 +--------------------
 arch/arm/cpu/u-boot-spl.lds                 |   1 +
 arch/arm/cpu/u-boot.lds                     |   1 +
 arch/arm/lib/Makefile                       |   2 +-
 arch/arm/lib/cache.c                        |  13 +-
 arch/arm/lib/vectors.S                      | 291 ++++++++++++++++++++++++++++
 board/compulab/cm_t335/u-boot.lds           |   1 +
 board/freescale/mx31ads/u-boot.lds          |   1 +
 board/ti/am335x/u-boot.lds                  |   1 +
 27 files changed, 359 insertions(+), 2489 deletions(-)
 create mode 100644 arch/arm/lib/vectors.S

Signature · 1 line

1.8.3.2

Albert ARIBAUD

author

2014-04-15 14:13 UTC #1 lore raw

PATCH v3 1/5 arm1136: move cache code from start.S to cache.c

arch/arm/cpu/arm1136/start.S contain a cache flushing function. Remove the function and move its code into arch/arm/lib/cache.c.

Signed-off-by Albert ARIBAUD <[email protected]>

---

Changes in v3: None
Changes in v2: None

 arch/arm/cpu/arm1136/start.S | 10 ----------
 arch/arm/lib/cache.c         | 13 ++++++++++---
 2 files changed, 10 insertions(+), 13 deletions(-)

arch/arm/cpu/arm1136/start.S +0 ~~-10~~

index 3e2358e..0085754 100644
@@ -333,14 +333,4 @@ fiq:
 	bl	do_fiq
 
 #endif
-	.align 5
-.global arm1136_cache_flush
-arm1136_cache_flush:
-#if !defined(CONFIG_SYS_ICACHE_OFF)
-		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
-#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
-		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
-#endif
-		mov	pc, lr			@ back to caller
 #endif	/* CONFIG_SPL_BUILD */

arch/arm/lib/cache.c +10 -3

index 6cc136a..4f6b9f0 100644
@@ -12,16 +12,23 @@
 void  __flush_cache(unsigned long start, unsigned long size)
 {
 #if defined(CONFIG_ARM1136)
-	void arm1136_cache_flush(void);
 
-	arm1136_cache_flush();
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+	asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
 #endif
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+	asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
+#endif
+
+#endif /* CONFIG_ARM1136 */
+
 #ifdef CONFIG_ARM926EJS
 	/* test and clean, page 2-23 of arm926ejs manual */
 	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
 	/* disable write buffer as well (page 2-22) */
 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
+#endif /* CONFIG_ARM926EJS */
 	return;
 }
 void  flush_cache(unsigned long start, unsigned long size)

Signature · 1 line

1.8.3.2

Albert ARIBAUD

author

2014-04-15 14:13 UTC #2 lore raw

PATCH v3 2/5 arm: move reset_cpu from start.S into cpu.c

CPUs arm946es and sa1100 both define the reset_cpu() function in their start.S file. Move this cpu-specific code into cpu.c so that start.S only contains ARM generic code.

Signed-off-by Albert ARIBAUD <[email protected]>

---

Changes in v3: None
Changes in v2:
- fixed checkpatch issues in arch/arm/cpu/arm946es/cpu.c
- fixed checkpatch issues in arch/arm/cpu/sa1100/cpu.c

 arch/arm/cpu/arm946es/cpu.c   | 13 +++++++++++++
 arch/arm/cpu/arm946es/start.S | 23 -----------------------
 arch/arm/cpu/sa1100/cpu.c     | 14 ++++++++++++++
 arch/arm/cpu/sa1100/start.S   | 10 ----------
 4 files changed, 27 insertions(+), 33 deletions(-)

arch/arm/cpu/arm946es/cpu.c +13 -0

index 0c8d92d..e20e5a8 100644
@@ -16,6 +16,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/system.h>
+#include <asm/io.h>
 
 static void cache_flush(void);

@@ -51,3 +52,15 @@ static void cache_flush (void)
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
 }
+
+#ifndef CONFIG_INTEGRATOR
+
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+{
+	writew(0x0, 0xfffece10);
+	writew(0x8, 0xfffece10);
+	for (;;)
+		;
+}
+
+#endif	/* #ifdef CONFIG_INTEGRATOR */

arch/arm/cpu/arm946es/start.S +0 ~~-23~~

index 7d50145..534592f 100644
@@ -320,26 +320,3 @@ fiq:
 	bl	do_fiq
 
 #endif
-
-# ifdef CONFIG_INTEGRATOR
-
-	/* Satisfied by general board level routine */
-
-#else
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-
-	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0
-	strh	r3, [r1]	/* clear it */
-	mov	r3, #0x8
-	strh	r3, [r1]	/* force dsp+arm reset */
-_loop_forever:
-	b	_loop_forever
-
-rstctl1:
-	.word	0xfffece10
-
-#endif	/* #ifdef CONFIG_INTEGRATOR */

arch/arm/cpu/sa1100/cpu.c +14 -0

index 6651898..4c9752a 100644
@@ -17,6 +17,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/system.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;

@@ -52,3 +53,16 @@ static void cache_flush (void)
 
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
+
+#define RST_BASE 0x90030000
+#define RSRR	0x00
+#define RCSR	0x04
+
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+{
+	/* repeat endlessly */
+	while (1) {
+		writel(0, RST_BASE + RCSR);
+		writel(1, RST_BASE + RSRR);
+	}
+}

arch/arm/cpu/sa1100/start.S +0 ~~-10~~

index bf80937..472a595 100644
@@ -337,13 +337,3 @@ fiq:
 	bl	do_fiq
 
 #endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r0, RST_BASE
-	mov	r1, #0x0			@ set bit 3-0 ...
-	str	r1, [r0, #RCSR]			@ ... to clear in RCSR
-	mov	r1, #0x1
-	str	r1, [r0, #RSRR]			@ and perform reset
-	b	reset_cpu			@ silly, but repeat endlessly

Signature · 1 line

1.8.3.2

Albert ARIBAUD

author

2014-04-15 14:13 UTC #3 lore raw

PATCH v3 3/5 arm: pxa: move SP check from start.S to cpuinfo.c

PXA start.S has a PXA (variant) specific check in
start.S. Move it to cpuinfo.c.

Signed-off-by Albert ARIBAUD <[email protected]>

---

Changes in v3: None
Changes in v2: None

 arch/arm/cpu/pxa/cpuinfo.c | 6 ++++++
 arch/arm/cpu/pxa/start.S   | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

arch/arm/cpu/pxa/cpuinfo.c +6 -0

index 9d16079..17d8be5 100644
@@ -11,6 +11,12 @@
 #include <errno.h>
 #include <linux/compiler.h>
 
+#ifdef CONFIG_CPU_PXA25X
+#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
+#error "Init SP address must be set to 0xfffff800 for PXA250"
+#endif
+#endif
+
 #define	CPU_MASK_PXA_PRODID	0x000003f0
 #define	CPU_MASK_PXA_REVID	0x0000000f

arch/arm/cpu/pxa/start.S +0 -6

index ae0d13c..eb3243a 100644
@@ -23,12 +23,6 @@
 #include <config.h>
 #include <version.h>
 
-#ifdef CONFIG_CPU_PXA25X
-#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
-#error "Init SP address must be set to 0xfffff800 for PXA250"
-#endif
-#endif
-
 .globl _start
 _start: b	reset
 #ifdef CONFIG_SPL_BUILD

Signature · 1 line

1.8.3.2

Albert ARIBAUD

author

2014-04-15 14:13 UTC #4 lore raw

PATCH v3 4/5 arm: remove unused _end_vect and _vectors_end symbols

Signed-off-by Albert ARIBAUD <[email protected]>

---

Changes in v3: None
Changes in v2: None

 arch/arm/cpu/arm1136/start.S  | 2 --
 arch/arm/cpu/arm1176/start.S  | 2 --
 arch/arm/cpu/arm946es/start.S | 2 --
 arch/arm/cpu/armv7/start.S    | 3 ---
 arch/arm/cpu/pxa/start.S      | 2 --
 5 files changed, 11 deletions(-)

arch/arm/cpu/arm1136/start.S +0 -2

index 0085754..13567b9 100644
@@ -53,8 +53,6 @@ _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
-.global _end_vect
-_end_vect:
 
 	.balignl 16,0xdeadbeef
 /*

arch/arm/cpu/arm1176/start.S +0 -2

index ce62011..b353d69 100644
@@ -61,8 +61,6 @@ _pad:
 	. = _start + 64
 #endif
 
-.global _end_vect
-_end_vect:
 	.balignl 16,0xdeadbeef
 /*
  *************************************************************************

arch/arm/cpu/arm946es/start.S +0 -2

index 534592f..9806819 100644
@@ -56,8 +56,6 @@ _fiq:
 
 	.balignl 16,0xdeadbeef
 
-_vectors_end:
-
 /*
  *************************************************************************
  *

arch/arm/cpu/armv7/start.S +0 -3

index 27be451..eefe1ed 100644
@@ -55,9 +55,6 @@ _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
 
-.global _end_vect
-_end_vect:
-
 	.balignl 16,0xdeadbeef
 /*************************************************************************
  *

arch/arm/cpu/pxa/start.S +0 -2

index eb3243a..e3bf1c2 100644
@@ -61,8 +61,6 @@ _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
 #endif	/* CONFIG_SPL_BUILD */
-.global _end_vect
-_end_vect:
 
 	.balignl 16,0xdeadbeef
 /*

Signature · 1 line

1.8.3.2

Albert ARIBAUD

author

2014-04-15 14:13 UTC #5 lore raw

PATCH v3 5/5 arm: move exception handling out of start.S files

Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly.

Signed-off-by Albert ARIBAUD <[email protected]>

---

Changes in v3:
- factorized SPL/non-SPL code
- fixed socfpga_cyclone5 IRQ setting in save_boot_params

Changes in v2:
- rebased onto u-boot-arm/master (de4fdfc1)
- adjusted comment in Zynq linker script

 arch/arm/cpu/arm1136/start.S                | 242 +----------------------
 arch/arm/cpu/arm1176/start.S                | 196 +------------------
 arch/arm/cpu/arm720t/start.S                | 229 +---------------------
 arch/arm/cpu/arm920t/ep93xx/u-boot.lds      |   3 +-
 arch/arm/cpu/arm920t/start.S                | 216 +--------------------
 arch/arm/cpu/arm926ejs/mxs/start.S          |  92 +--------
 arch/arm/cpu/arm926ejs/spear/start.S        |  27 +--
 arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds |   1 +
 arch/arm/cpu/arm926ejs/start.S              | 262 +------------------------
 arch/arm/cpu/arm946es/start.S               | 221 +--------------------
 arch/arm/cpu/arm_intcm/start.S              | 228 +---------------------
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S  |  15 +-
 arch/arm/cpu/armv7/start.S                  | 250 +-----------------------
 arch/arm/cpu/armv7/zynq/u-boot.lds          |   2 +-
 arch/arm/cpu/pxa/start.S                    | 245 +----------------------
 arch/arm/cpu/sa1100/start.S                 | 215 +-------------------
 arch/arm/cpu/u-boot-spl.lds                 |   1 +
 arch/arm/cpu/u-boot.lds                     |   1 +
 arch/arm/lib/Makefile                       |   2 +-
 arch/arm/lib/vectors.S                      | 291 ++++++++++++++++++++++++++++
 board/compulab/cm_t335/u-boot.lds           |   1 +
 board/freescale/mx31ads/u-boot.lds          |   1 +
 board/ti/am335x/u-boot.lds                  |   1 +
 23 files changed, 316 insertions(+), 2426 deletions(-)
 create mode 100644 arch/arm/lib/vectors.S

arch/arm/cpu/arm1136/start.S +1 ~~-241~~

index 13567b9..1cfcca9 100644
@@ -15,46 +15,7 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
-.globl _start
-_start: b	reset
-#ifdef CONFIG_SPL_BUILD
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
-	ldr	pc, _hang
 
-_hang:
-	.word	do_hang
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678
-	.word	0x12345678	/* now 16*4=64 */
-#else
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-_pad:			.word 0x12345678 /* now 16*4=64 */
-#endif	/* CONFIG_SPL_BUILD */
-
-	.balignl 16,0xdeadbeef
 /*
  *************************************************************************
  *

@@ -68,26 +29,7 @@ _pad:			.word 0x12345678 /* now 16*4=64 */
  *************************************************************************
  */
 
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
+	.globl	reset
 
 reset:
 	/*

@@ -150,185 +92,3 @@ cpu_init_crit:
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SPL_BUILD
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
-	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
-
-	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
-	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
-	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp				@ save current stack into r0 (param register)
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	stmdb	r8, {sp, lr}^			@ Calling SP, LR
-	str	lr, [r8, #0]			@ Save calling PC
-	mrs	r6, spsr
-	str	r6, [r8, #4]			@ Save CPSR
-	str	r0, [r8, #8]			@ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
-
-	str	lr, [r13]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr			@ get the spsr
-	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13			@ switch modes, make sure moves will execute
-	mov	lr, pc				@ capture return pc
-	movs	pc, lr				@ jump to next instruction & switch modes.
-	.endm
-
-	.macro get_bad_stack_swi
-	sub	r13, r13, #4			@ space on current stack for scratch reg.
-	str	r0, [r13]			@ save R0's value.
-	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
-	str	lr, [r0]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr			@ get the spsr
-	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
-	ldr	lr, [r0]			@ restore lr
-	ldr	r0, [r13]			@ restore r0
-	add	r13, r13, #4			@ pop stack entry
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-#endif	/* CONFIG_SPL_BUILD */
-
-/*
- * exception handlers
- */
-#ifdef CONFIG_SPL_BUILD
-	.align	5
-do_hang:
-	bl	hang				/* hang and never return */
-#else	/* !CONFIG_SPL_BUILD */
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack_swi
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-#endif	/* CONFIG_SPL_BUILD */

arch/arm/cpu/arm1176/start.S +1 ~~-195~~

211 lines not on this page · raw message

arch/arm/cpu/arm720t/start.S +1 ~~-228~~

244 lines not on this page · raw message

arch/arm/cpu/arm920t/ep93xx/u-boot.lds +2 -1

index 9699404..623a635 100644
@@ -16,7 +16,8 @@ SECTIONS
 	.text      :
 	{
 		*(.__image_copy_start)
-	  arch/arm/cpu/arm920t/start.o	(.text*)
+		*(.vectors)
+		arch/arm/cpu/arm920t/start.o	(.text*)
 		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
 	  . = 0x1000;
 	  LONG(0x53555243)

arch/arm/cpu/arm920t/start.S +2 ~~-214~~

232 lines not on this page · raw message

arch/arm/cpu/arm926ejs/mxs/start.S +2 ~~-90~~

107 lines not on this page · raw message

arch/arm/cpu/arm926ejs/spear/start.S +1 ~~-26~~

index 7dbd5db..290ac2e 100644
@@ -17,29 +17,6 @@
 
 #include <config.h>
 
-.globl _start
-_start:
-	b	reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:
-_software_interrupt:
-_prefetch_abort:
-_data_abort:
-_not_used:
-_irq:
-_fiq:
-	.word infinite_loop
-
-infinite_loop:
-	b	infinite_loop
-
 /*
  *************************************************************************
  *

@@ -53,9 +30,7 @@ infinite_loop:
  *************************************************************************
  */
 
-/*
- * the actual reset code
- */
+	.globl	reset
 
 reset:
 /*

arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +1 -0

index b6d0f65..c7ee199 100644
@@ -21,6 +21,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text	:
 	{
+		*(.vectors)
 		arch/arm/cpu/arm926ejs/spear/start.o	(.text*)
 		*(.text*)
 	}

arch/arm/cpu/arm926ejs/start.S +1 ~~-261~~

277 lines not on this page · raw message

arch/arm/cpu/arm946es/start.S +1 ~~-220~~

236 lines not on this page · raw message

arch/arm/cpu/arm_intcm/start.S +1 ~~-227~~

243 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/lowlevel_init.S +1 ~~-14~~

index 1caaa27..2f2e9fc 100644
@@ -10,20 +10,7 @@
 /* Save the parameter pass in by previous boot loader */
 .global save_boot_params
 save_boot_params:
-	/* save the parameter here */
-
-	/*
-	 * Setup stack for exception, which is located
-	 * at the end of on-chip RAM. We don't expect exception prior to
-	 * relocation and if that happens, we won't worry -- it will overide
-	 * global data region as the code will goto reset. After relocation,
-	 * this region won't be used by other part of program.
-	 * Hence it is safe.
-	 */
-	ldr	r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
-	ldr	r1, =IRQ_STACK_START_IN
-	str	r0, [r1]
-
+	/* no parameter to save */
 	bx	lr

arch/arm/cpu/armv7/start.S +1 ~~-249~~

265 lines not on this page · raw message

arch/arm/cpu/armv7/zynq/u-boot.lds +1 -1

index f2a5965..69500a6 100644
@@ -88,7 +88,7 @@ SECTIONS
 	}
 
 	/*
-	 * Zynq needs to discard more sections because the user
+	 * Zynq needs to discard these sections because the user
 	 * is expected to pass this image on to tools for boot.bin
 	 * generation that require them to be dropped.
 	 */

arch/arm/cpu/pxa/start.S +1 ~~-244~~

263 lines not on this page · raw message

arch/arm/cpu/sa1100/start.S +1 ~~-214~~

230 lines not on this page · raw message

arch/arm/cpu/u-boot-spl.lds +1 -0

index 3e88668..4beddf0 100644
@@ -18,6 +18,7 @@ SECTIONS
 	.text :
 	{
 		__image_copy_start = .;
+		*(.vectors)
 		CPUDIR/start.o (.text*)
 		*(.text*)
 	}

arch/arm/cpu/u-boot.lds +1 -0

index 33c1f99..a7728e0 100644
@@ -18,6 +18,7 @@ SECTIONS
 	.text :
 	{
 		*(.__image_copy_start)
+		*(.vectors)
 		CPUDIR/start.o (.text*)
 		*(.text*)
 	}

arch/arm/lib/Makefile +1 -1

index e035d6a..585f1f7 100644
@@ -11,7 +11,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
 ifdef CONFIG_ARM64
 obj-y	+= crt0_64.o
 else
-obj-y	+= crt0.o
+obj-y	+= vectors.o crt0.o
 endif
 
 ifndef CONFIG_SPL_BUILD

arch/arm/lib/vectors.S new file +291 -0

291 lines not on this page · raw message

board/compulab/cm_t335/u-boot.lds +1 -0

index 0984dfe..c8ab716 100644
@@ -18,6 +18,7 @@ SECTIONS
 	.text :
 	{
 		*(.__image_copy_start)
+		*(.vectors)
 		CPUDIR/start.o (.text*)
 		board/compulab/cm_t335/built-in.o (.text*)
 		*(.text*)

board/freescale/mx31ads/u-boot.lds +1 -0

index 6da1d4b..61b83bf 100644
@@ -22,6 +22,7 @@ SECTIONS
 	  /* WARNING - the following is hand-optimized to fit within	*/
 	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
+	  *					(.vectors)
 	  arch/arm/cpu/arm1136/start.o		(.text*)
 	  board/freescale/mx31ads/built-in.o	(.text*)
 	  arch/arm/lib/built-in.o		(.text*)

board/ti/am335x/u-boot.lds +1 -0

index a9e3d34..2c5a0f8 100644
@@ -34,6 +34,7 @@ SECTIONS
 	.text :
 	{
 		*(.__image_copy_start)
+		*(.vectors)
 		CPUDIR/start.o (.text*)
 		board/ti/am335x/built-in.o (.text*)
 		*(.text*)

Signature · 1 line

1.8.3.2

Marek Vasut

2014-04-15 14:16 UTC #6 lore raw

PATCH v3 3/5 arm: pxa: move SP check from start.S to cpuinfo.c

In reply to Albert ARIBAUD

Quoted 8 lines · Albert ARIBAUD

PXA start.S has a PXA (variant) specific check in
start.S. Move it to cpuinfo.c.
Signed-off-by Albert ARIBAUD <[email protected]>
---
Changes in v3: None
Changes in v2: None

Acked-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Gerhard Sittig

2014-04-16 21:57 UTC #7 lore raw

v3 cover ARM: refactor start.S files

In reply to Albert ARIBAUD

Quoted 2 lines · Albert ARIBAUD

[ ... deeply nested 'git send-email' thread ... ]

May I suggest the following git config option?

[sendemail]
chainreplyto = false

This creates "shallow threads", and improves consumption on the receivers' side, allowing to more quickly tell patches from review feedback, and better follow the series' structure.

Just a thought, not picking at this specific submission, only following up when I saw one of those occurances (thus the list reply, too, for the archives) ...

virtually yours
Gerhard Sittig

Signature · 3 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

Albert ARIBAUD

author

2014-04-17 08:12 UTC #8 lore raw

v3 cover ARM: refactor start.S files

Hi Gerhard,

Quoted 9 lines · Gerhard Sittig

Quoted 2 lines · Albert ARIBAUD
[ ... deeply nested 'git send-email' thread ... ]
May I suggest the following git config option?
[sendemail]
chainreplyto = false

Quoted 7 lines

This creates "shallow threads", and improves consumption on the receivers' side, allowing to more quickly tell patches from review feedback, and better follow the series' structure.
Just a thought, not picking at this specific submission, only following up when I saw one of those occurances (thus the list reply, too, for the archives) ...

Thanks for th tip! Setting added on my ~/.gitconfig.

Quoted 2 lines

virtually yours
Gerhard Sittig

Amicalement,

Signature · 1 line

Albert.

Albert ARIBAUD

author

2014-05-15 14:26 UTC #9 lore raw

v3 cover ARM: refactor start.S files

In reply to Albert ARIBAUD

Quoted 47 lines · Albert ARIBAUD

This series aims at refactoring start.S files. Some of these files contain cache-related or cpu-reset-related core, which is moved where it belongs. Useless symbols are removed, and finally, exception vector code, common across all ARM CPUs, is moved in its own file.
At this point, the start.S files only contain CPU-specific reset sequences.
Changes in v3:
- factorized SPL/non-SPL code
- fixed socfpga_cyclone5 IRQ setting in save_boot_params
Changes in v2:
- fixed checkpatch issues in arch/arm/cpu/arm946es/cpu.c
- fixed checkpatch issues in arch/arm/cpu/sa1100/cpu.c
- rebased onto u-boot-arm/master (de4fdfc1)
- adjusted comment in Zynq linker script
Albert ARIBAUD (5):
arm1136: move cache code from start.S to cache.c
arm: move reset_cpu from start.S into cpu.c
arm: pxa: move SP check from start.S to cpuinfo.c
arm: remove unused _end_vect and _vectors_end symbols
arm: move exception handling out of start.S files
 arch/arm/cpu/arm1136/start.S                | 254 +-----------------------
 arch/arm/cpu/arm1176/start.S                | 198 +------------------
 arch/arm/cpu/arm720t/start.S                | 229 +---------------------
 arch/arm/cpu/arm920t/ep93xx/u-boot.lds      |   3 +-
 arch/arm/cpu/arm920t/start.S                | 216 +--------------------
 arch/arm/cpu/arm926ejs/mxs/start.S          |  92 +--------
 arch/arm/cpu/arm926ejs/spear/start.S        |  27 +--
 arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds |   1 +
 arch/arm/cpu/arm926ejs/start.S              | 262 +------------------------
 arch/arm/cpu/arm946es/cpu.c                 |  13 ++
 arch/arm/cpu/arm946es/start.S               | 246 +----------------------
 arch/arm/cpu/arm_intcm/start.S              | 228 +---------------------
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S  |  15 +-
 arch/arm/cpu/armv7/start.S                  | 253 +-----------------------
 arch/arm/cpu/armv7/zynq/u-boot.lds          |   2 +-
 arch/arm/cpu/pxa/cpuinfo.c                  |   6 +
 arch/arm/cpu/pxa/start.S                    | 253 +-----------------------
 arch/arm/cpu/sa1100/cpu.c                   |  14 ++
 arch/arm/cpu/sa1100/start.S                 | 225 +--------------------
 arch/arm/cpu/u-boot-spl.lds                 |   1 +
 arch/arm/cpu/u-boot.lds                     |   1 +

Quoted 8 lines

 arch/arm/lib/Makefile                       |   2 +-
 arch/arm/lib/cache.c                        |  13 +-
 arch/arm/lib/vectors.S                      | 291 ++++++++++++++++++++++++++++
 board/compulab/cm_t335/u-boot.lds           |   1 +
 board/freescale/mx31ads/u-boot.lds          |   1 +
 board/ti/am335x/u-boot.lds                  |   1 +
 27 files changed, 359 insertions(+), 2489 deletions(-)
 create mode 100644 arch/arm/lib/vectors.S

Applied to u-boot-arm/master.

Amicalement,

Signature · 1 line

Albert.